JPS58129553A - Pipeline computer - Google Patents

Abstract

PURPOSE:To prevent generation of an exceptional condition to the utmost, and to sufficiently display performance of a pipeline computer, by analyzing said condition and revising a progam, when the contents taken in advance have been uneffectuated due to generation of the exceptional condition. CONSTITUTION:A pipeline computer is constituted of a main storage device 1 and a CPU5 having a storage control processor 2, an advance taking processor 3 and an executing processor 4. In this state, when an exceptional condition for uneffectuating an instruction taken in advance and an operand data has been generated, the processor 3 generates an interruption request signal to an interruption request signal line 6, and inputs logic ''1'' to an AND circuit 8 of the executing processor 4. To the other input of this circuit 8, an interuption approval flag 7 which an operator sets is inputted, and by the executing processor 4, the interruption processing is executed in accordance with a program decided in advance. An executing program of this flag 7 is revised to a program for preventing generation of the exceptional condition to the utmost, and performance of the pipeline computer is displayed suffciently.

Description

[Detailed description of the invention] (3.1) Field to which the invention pertains This invention is a prefetch processor that prefetches instructions, operand data, etc., and executes the instructions and operand data that have been prefetched. - This relates to a pipeline computer that executes instructions in a processor.

(3.2) Configuration of conventional technology Figure 1 is a block diagram showing the main tanks of a pipeline computer, in which (1) is the main storage, (2) is the storage control processor, (3) is the prefetch processor, (4) is an execution processor, and (5) is (2), (3), (4)
It is a CPU (central processing unit t) including Y. The storage control processor (2) is equipped with a fast buffer storage for storing a copy of a portion of the contents of the main memory (1), and the look-ahead processor (3) and the execution processor (4) are connected to the main memory (1).
11 without requiring access to the storage control processor (
It is sufficient to access the high-speed buffer storage in 2), and this access can be performed at high speed.

The prefetch processor (3) prefetches instructions and data from the storage control processor (2), decodes the instructions, modifies the instructions,
Prefetching of operand data, prefetching of branch destination instructions, queuing of instructions and operand data
), etc., and the execution processor (4) executes the instruction using the prepared instruction and operand data.

(3.3) Operation of the prior art Figure 2 is a block diagram showing the main registers in the prefetch processor (3), where Q(I is a buffer register, aυ is an instruction register, and the mackerel is an instruction queue. In the embodiment shown, buffer register a consists of two sets of registers (10m) and registers (10b), each with a capacity of 4 words. Between the storage control processor (2) and buffer register a, 4M instructions are transferred simultaneously. transferred, i.e. 1s
The lowest two bits of the address of the instruction I are accessed and 4#, which are consecutive addresses, are simultaneously input to the buffer register (10m) or (10b). The four instructions in the buffer register a1 are fetched in address order to the instruction register αυ for one instruction and decoded, and preprocessing such as modification of the instruction and prefetching of operand data 9 is performed in accordance with the instruction.

When the 4@ instructions in the buffer register (10a) or (10b) are sequentially fetched into the instruction register aυ and the buffer register (10m) or (10b) becomes empty, the prefetch processor (3) receives instructions from the storage control processor (2). Prefetch 4-word instructions with consecutive addresses. Instructions that have been preprocessed are passed to the execution processor (4),
Operation of prefetch processor (3) and execution processor (4)
The instructions that the execution processor (4) attempts to execute by absorbing the difference in processing time between the two are always waiting in the preemption processor (3). An instruction queue α section is provided as shown in FIG. In the example shown in Figure 2, the instruction queue (13 is 4 queues (
12a), (12b), (12c), and (12d).

Prefetching of commands and operand data is performed as described above, but in some cases, this prefetching process becomes wasteful and it becomes necessary to perform a new prefetching process. For example, if you do a prefetch and the prefetch processor (3
), the main memory containing the imported instruction and operand data (for address 13,
Even though a write operation is performed by another CPU that is jointly using the main memory (1), the execution processor (4) must use the written instructions and operand data.
The instructions and operand data in the prefetch processor (3) may be from before the above write operation, or the prefetch processor (3) may assume that the condition is rAJ for a conditional branch instruction, and in that case, the pre-branch address may be However, as a result of execution by the execution processor (4), it turns out that the above condition is not rAJ, that is, when prediction of the branch destination address fails, the troublesome pack register a or (And) It is necessary to invalidate the contents of the queue (I3) and start the prefetch process again.

(3.4) Disadvantages of the conventional technology As mentioned above, when an exceptional condition occurs and the preempted contents are invalidated, the preemption processing must be repeated again, and the overall processing capacity of the computer is significantly reduced. Therefore, it is necessary to make sure that such exceptional conditions do not occur (it is necessary to modify the Niprogram), but with conventional equipment, there is no record of the occurrence of exceptional conditions, so
The drawback is that it is difficult to discover the location where an exceptional condition occurs and modify the program.

(3.5) Purpose of the present invention This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and includes an exception condition in which prefetched contents are invalidated until the program is sufficiently modified. Provided is a pipeline calculator having a means for collecting and storing information necessary for investigating information related to the occurrence of this exceptional condition and modifying the program to reduce the occurrence of the exceptional condition when the occurrence of the exceptional condition occurs. This is the purpose of this.

(3.6) Structure of the present invention The present invention will now be described in detail with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and they operate in the same way.
6) is an interrupt request signal line, (7) is an interrupt enable flag,
(8) is an AND circuit 〇(3.7) Operation of the present invention When the occurrence of an exceptional condition that invalidates the prefetched instruction or operand data is detected, the prefetch processor (3) interrupts An interrupt request signal (logic "1" signal) is output on the request signal line (6).

The signal logic of flag (7) can be set arbitrarily by the operator, but if a logic "1" signal (meaning interrupt permission) is set in flag (7), the AND circuit (8 )
The output of is a logic "1". When a logic "1" signal is output from the AND circuit (8), the execution processor (4) executes a predetermined interrupt processing program. This interrupt processing program determines at what instruction address and at what operand address the exception condition occurs.
Create an interrupt processing program that processes the data so that you can find out what caused it, how often it occurred, etc., and stores the processed data in nine predetermined locations. Therefore, the data stored in the interrupt processing program executed by the logic "1" signal from the AND circuit (8) is examined, and the program is designed to reduce the occurrence of the exception condition. can be corrected. In other words, in the ninth stage of creating a program, flag (7) is set to logic "
1" bit is set, and each time an exception condition occurs (2), the interrupt processing program is executed in execution process t(4), and as a result (2). After modifying the flag (
If the logic in 7) is rOJ, the operation of the circuit in Figure 3 is 21
The operation is similar to that of the circuit shown in the figure. In addition, the program has been modified to reduce the occurrence of exception conditions as much as possible, so the benefits of the pipeline computer can be fully utilized. software that is used repeatedly, scientific and technical software that is used repeatedly, etc.
The present invention can sufficiently reduce the chances of invalidating the contents of a buffer register or queue and performing prefetch processing again, making it possible to effectively utilize the advantages of a pipelined computer.

(3.8) Other embodiments of the invention In the above embodiment, the prefetched instruction and operand data are invalidated. It is possible to handle exception conditions in the same way.

(3.9) Effects of the present invention As described above, according to the present invention 42, when the contents that were pre-fetched from the occurrence of the exception condition ζ2 in the pipeline computer are invalidated, this is analyzed and the above-mentioned exception is invalidated. Since the program can be revised to prevent the occurrence of such conditions as much as possible, it has become easier to fully utilize the performance of the pipeline computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main components of a pipeline computer, FIG. 2 is a block diagram showing the main registers in the prefetch processor shown in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. (2)...Storage control processor, (3)...Preemption processor, (4)...
Execution processor, (6)...Interrupt request signal line, (7
)...Interrupt enable flag, (8)...AND circuit,
H...Buffer register, (11)...Instruction register, Address...Instruction queue. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Shin Kuzuno −

Claims (1)

[Claims] In a pipelined computer having a prefetch processor that performs prefetch processing of instructions, operand data, etc., and an execution processor that executes nine instructions prefetched by the prefetch processor, the occurrence of an exception condition that invalidates the prefetch contents is detected. means for requesting an interrupt from the preempting processor to the executing processor when the occurrence of this exceptional condition is detected; and setting a signal indicating whether or not to permit the interrupt in a flag provided in the executing processor. and a means for executing a predetermined interrupt processing program in the execution processor based on the interrupt from the preemption processor only when a signal to permit the interrupt is set in the flag, and one of the exception conditions in question is executed. A pipeline computer characterized by having a means for storing information necessary for investigating information related to occurrence and modifying a program to reduce occurrence of an exceptional condition.