JPH05274143A - Composite condition processing system - Google Patents

Abstract

PURPOSE:To curtail the use of a condition branching instruction that affects the parallel processings carried out at an instruction word level and to improve the effect of the high speed processing attained with the parallel execution of instructions. CONSTITUTION:The comparison operations are carried out by the comparison computing elements 2-1-2-3 to designate the independent comparison instructions. Then the genuineness value of these computing results are selected by a selector corresponding to the bit position in a flag register 6 that is designated by (an operand C of) a comparison instruction among those selectors 4-0-4-3. The selected genuineness value is set to a flip-flop F/F forming the bit position. The output of the register 6 is supplied to an instruction fetching address generating circuit 8 together with the mask value M designated by the condition branch instruction to be carried out after the comparison instruction. Thus an AND circuit of the circuit 8 secures an AND of each bit between the output value of the register 6 and the mask value M. Then a branching destination address or the next instruction address is selected and outputted as the address of the instruction to be carried out next in accordance with a fact whether the AND results are all equal to zero or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing apparatus for processing a plurality of instructions in parallel, and more particularly to a composite condition processing method suitable for executing judgments of respective conditions constituting a composite condition in parallel.

[0002]

2. Description of the Related Art Generally, a compound condition described in a source program is translated as shown in FIG. 5 by combining a comparison instruction (condition determination instruction) and a conditional branch instruction. For example, the C language source program if (X> 1 && X <10 && X! = 5) {} shown in FIG. 6A (“&&” indicates a logical product, and “! =” Must not be equal). Is shown in FIG.
It is translated into a machine language as shown in (b).

In FIG. 6B, "CMP A, B,
Instructions expressed in the form of C "compare A and B,
A comparison instruction for storing the magnitude comparison result (≦, ≧, or =) in the register C is shown.

In addition, "BLE C, L", "BGE"
Instructions expressed in the form of C, L ”,“ BEQ C, L ”check the comparison result stored in the register C,
Conditional branch instructions for branching to L (instruction at address L) when ≤, ≥, and = are shown.

The above example is for a processor that sequentially executes instructions one by one. If the parallel processing device can execute a plurality of instructions in parallel, the instruction execution cycle can be shortened by rearranging the instructions at the time of translation or at the time of execution and processing the comparison instruction in parallel prior to the conditional branch instruction. Is possible.

An example of such instruction relocation is shown in FIG.
FIG. 6C shows the case of the C language source program shown in FIG. In the example of FIG. 6C, three comparison instructions are executed in parallel, and after execution of these instructions, three conditional branch instructions are sequentially executed one by one.

[0007]

As described above, in the conventional parallel processing device, the comparison instruction can be executed in parallel in the complex conditional processing by the combination of the comparison instruction and the conditional branch instruction. I had to do it serially. For this reason, conventionally, there has been a problem that the compound condition processing cannot expect much speedup by parallel processing.

Moreover, since the conditional branch instruction processing has a larger number of processing cycles than an ordinary arithmetic instruction such as an obstacle to the instruction prefetch pipeline processing, the processing speed cannot be expected further.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide conditional branching which is an obstacle to parallel processing at an instruction word level in complex conditional processing in a parallel processing device capable of processing a plurality of instructions in parallel. An object of the present invention is to provide a compound condition processing method capable of reducing the use of instructions and improving the effect of speeding up by parallel execution of instructions.

[0010]

According to the present invention, in a parallel processing device capable of processing a plurality of instructions in parallel, each bit value depends on the true / false value of the execution result of a plurality of comparison instructions (condition determination instructions). A flag register means that can be set / reset independently and in parallel, a logical product means for taking a bitwise logical product of the content held in the flag register means and the mask value designated by the conditional branch instruction, and this logical product means An instruction fetch address selecting means for selecting the branch destination address specified by the conditional branch instruction or the address of the instruction next to the same instruction as the instruction address to be executed next, depending on whether or not the output value of It is characterized in that whether or not to execute a branch is determined by using the bit state of each bit position of the flag register means specified by the mask value as a composite condition. It is an.

[0011]

In the above structure, each bit of the bit position in the flag register means designated by the comparison instruction is set / reset independently and in parallel according to the true / false value of the execution result of the plurality of comparison instructions. When the conditional branch instruction is executed next, a bit-wise logical product of the mask value designated by the instruction and the content held in the flag register means is obtained. Depending on whether or not the result of the logical product is all zero,
It is determined whether or not a compound condition in which the bit states of each bit position of the flag register means designated by the mask value are combined by a logical product or a logical sum is satisfied. Then, based on this determination result, whether or not to execute the branch is determined, and the branch destination address or the next instruction address is selected as the instruction address to be executed next.

As a result of the above, the part of the compound condition which is connected only by the logical product or only by the logical sum requires only one conditional branch instruction, and compared with the conventional method which requires a plurality of conditional branch instructions, The overhead due to branch processing can be greatly reduced.

[0013]

FIG. 1 is a block diagram showing an embodiment of a parallel processing apparatus to which the present invention is applied.
Portions not related to the present invention are omitted. The present embodiment is a case where three comparison instructions (condition determination instructions) are implemented in a parallel processing device that can be executed in parallel.

In FIG. 1, reference numerals 1-1, 1-2, and 1-3 are comparison instruction decode buffers for storing operands designated by three comparison instructions executed in parallel for each instruction. The operands stored in the buffers 1-i (i = 1 to 3) are the operands A and B to be compared, and the bit position (described later) in the flag register 6 as the storage destination of the comparison result of the A and B. Here, there are three operands C indicating any one of bits 0 to 3).

The comparison instruction applied in this embodiment is SLE.
There are three types of comparison instructions: SGE comparison instructions and SEQ comparison instructions. The SLE comparison instruction is expressed in the form of "SLE A, B, C". A and B are compared, and when A≤B, "1" is set to the bit C of the flag register 6, and otherwise, "1" is set. Instruct to set "0".

The SGE comparison instruction is "SGE A, B, C".
It is instructed to compare A and B, and to set bit C of the flag register 6 to “1” when A ≧ B and to set “0” otherwise.

The SEQ comparison instruction is "SEQ A, B, C".
It is expressed in the form of, and A and B are compared, and when A = B, it is instructed to set the bit C of the flag register 6 to "1", and otherwise to "0".

Reference numerals 2-1, 2-2 and 2-3 denote comparison operators 3-1 and 3-1, respectively, which perform a comparison operation on the operands A and B in the comparison instruction decode buffers 1-1, 1-2 and 1-3, respectively. 3-2 and 3-3 are four output lines X0 to X3 corresponding to bits 0 to 3, respectively.
, Y0 to Y3, Z0 to Z3. The decode circuits 3-1, 3-2, 3-3 decode the operand C in the comparison instruction decode buffers 1-1, 1-2, 1-3, and output lines X0-X3, Y0-Y3, Z0, respectively. ~
The output line corresponding to the bit position designated by the operand C of Z3 is turned on.

4-0, 4-1, 4-2 and 4-3 are selectors (SE
L). The selector 4-i (i = 0 to 3) is one of the comparison results P, Q and R of the comparison calculators 2-1, 2-2 and 2-3.
The output lines Xi, Y of the decoding circuits 3-1, 3-2, 3-3.
Select according to the state of i and Zi. Here selector 4-i
As shown in FIG. 2, when Zi = 1 (on),
R is selected regardless of the states of Xi and Yi, and Yi = 1 and Z
If i = 0, select Q regardless of the state of Xi,
P is selected when Xi = 1 and Yi = Zi = 0.

As described above, in the present embodiment, when the same bit position is simultaneously designated by the operands C of different comparison instructions, the comparison result of the comparison operator 2-3 (stored in the comparison instruction decode buffer 1-3). The comparison result of the operands A and B that have been selected is given the highest priority, and then the comparison operator 2
The comparison result of -2 (the comparison result for the operands A and B stored in the comparison instruction decode buffer 1-2) is prioritized.

5-0, 5-1, 5-2, 5-3 are OR circuits, 6
Are four flip-flops (F / F) 6-0, 6- for holding the outputs of the selectors 4-0, 4-1, 4-2, 4-3.
It is a 4-bit flag register consisting of 1, 6-2 and 6-3. The OR circuit 5-i (i = 0 to 3) is the decoding circuit 3
The logical sum of the states of the output lines Xi, Yi and Zi of -1, 3-2 and 3-3 is calculated. The flip-flop 6-i is a flag register 6
The bit i of the selector 4-i is configured to latch the state of the output of the selector 4-i when the output of the OR circuit 5-i is "1". When the output of the OR circuit 5-i is "0", the state of the flip-flop 6-i does not change.

Reference numeral 7 is a branch instruction decode buffer for storing the operand designated by the conditional branch instruction. This operand is a 4-bit mask value M for the 4-bit output of the flag register 6.

The conditional branch instruction applied in this embodiment is B
There are two types, NZ conditional branch instructions and BEZ conditional branch instructions. The BNZ conditional branch instruction is expressed in the format of "BNZ M, L", and has M (mask value) and flag register 6
When the result (4 bits) of the logical product for each corresponding bit of the output of is not zero, it is instructed to branch to L (the address specified by).

The BEZ conditional branch instruction is "BEZ M, L".
When the result (4 bits) of the logical product of each corresponding bit of M (mask value) and the output of the flag register 6 is zero, branching to L (branch destination address) is performed. Give instructions.

Reference numeral 8 is an instruction fetch address generation circuit. This instruction fetch address generation time 8 takes a logical product of the mask value M in the conditional branch instruction decode buffer 7 and the output of the flag register 6 for each corresponding bit, and whether or not the result is zero and the conditional branch instruction BNZ or BEZ
Of the branch taken condition designating signal BTC (BTC = 1 in the case of BNZ and BTC = 0 in the case of BEZ) whose state is determined depending on which of the two is to be generated. Has been done.

FIG. 3 shows the configuration of the instruction fetch address generation circuit 8. 3, 81 is a mask value M and a flag register 6 in the branch instruction decode buffer 7 shown in FIG.
AND circuit for taking the logical product of the outputs of
Is a zero determination circuit that determines whether or not the 4-bit output value that is the logical product result of the logical product circuit 81 is zero (all zeros). The zero determination circuit 82 outputs a signal of "1" when the output value of the AND circuit 81 is zero, and outputs a signal of "0" otherwise.

An exclusive OR circuit 83 takes the exclusive OR of the output signal of the zero decision circuit 82 and the branch taken condition designating signal BTC, and outputs the result as a branch taken / not taken signal T / F. A program counter 85 generates / holds the next instruction address, and 85 is a selector (SEL). The selector 85 uses the branch destination address L or the next instruction address indicated by the program counter 84 (the instruction address next to the conditional branch instruction) as the address of the instruction to be executed next, from the exclusive OR circuit 83. Is selected according to the branch taken / not taken signal T / F.

Next, the operation of one embodiment of the present invention will be described with reference to FIG.
An example will be described in which the machine language instruction arranged as shown in FIG. 4B is executed corresponding to the same C language source program shown in FIG. 6A as shown in FIG. Note that FIG.
In (b), it is indicated that the three comparison instructions, that is, the SLE comparison instruction, the SGE comparison instruction, and the SEQ comparison instruction, which are arranged in the same row, are processed in parallel.

First, the three comparison instructions described above are decoded in parallel by a decoding circuit (not shown), and the three operands A, B, and C designated by the instructions are read from a general-purpose register or the like (not shown). .. If the instruction length has a margin, operands A to C may be included in the comparison instruction.

Then, the operands A, B and C designated by the first comparison instruction (SLE comparison instruction) located on the left side in FIG. 4B (here, as is clear from FIG. 4B, A = X, B = 1, C = 0) is stored in the comparison instruction decode buffer 1-1. In addition, the second comparison instruction (SGE comparison instruction) located at the center in FIG.
Operands A, B, and C designated by
As is clear from (b), A = X, B = 10, C =
1) is stored in the comparison instruction decode buffer 1-2.
Further, the operands A, B, designated by the third comparison instruction (SEQ comparison instruction) located on the right side in FIG.
C (here, as is clear from FIG. 4B, A =
X, B = 5, C = 2) is the comparison instruction decode buffer 1
Stored in -3.

Of the operands A, B and C stored in the decode buffers 1-1 to 1-3, A and B are supplied to the corresponding comparators 2-1 to 2-3 and C is the corresponding decode. It is supplied to the circuits 3-1 to 3-3.

The comparison operators 2-1, 2-2, 2-3 compare the magnitudes of the respective unique operands A, B supplied to themselves, and output the results as Boolean values P, Q, R. .. The outputs P, Q and R of the comparison calculators 2-1, 2-2 and 2-3 are supplied to selectors (SEL) 4-0 to 4-3, respectively.

On the other hand, the decoding circuits 3-1, 3-2 and 3-3 are
Each unique operand C supplied to itself is decoded and output lines X0-X3, Y0-Y3, Z0-
The output line corresponding to the bit position designated by the operand C of Z3 is turned on. Here, the decoding circuit 3-
The values of C supplied to 1, 3-2 and 3-3 are 0, 1 and 2, respectively, as described above, and therefore the decoding circuit 3
The output line X0 of -1, the output line Y1 of the decoding circuit 3-2, and the output line Z2 of the decoding circuit 3-3 are turned on.

The selectors 4-0, 4-1, 4-2 and 4-3 output the output lines X0 to Z0, X1 to Z1 of the decoding circuits 3-1 to 3-3.
According to the states of X2 to Z2 and X3 to Z3, the selecting operation according to the logic shown in FIG. 2 is performed. As a result, the output lines X0, Y1
, Z2 are turned on in this embodiment, the output P of the comparison operator 2-1 is output from the selector 4-0, the output Q of the comparison operator 2-2 is output from the selector 4-1 and the selector 4-2. From, the output R of the comparison calculator 2-3 is selectively output.

The OR circuits 5-0, 5-1, 5-2 and 5-3 output lines X0 to Z0, X1 to Z1, X2 to Z2 and X3 to Z3.
The logical sum of the logical states of. Here, the output lines X0, Y
Since 1 and Z2 are on ("1"), the outputs of the OR circuits 5-0, 5-1 and 5-2 are "1" and the outputs of the OR circuit 5-3 are "0".

The outputs of the selectors 4-0 to 4-3 are flip-flops (F / F) forming a 4-bit flag register 6.
6-0 to 6-3 are supplied as data signals. The outputs of the OR circuits 5-0 to 5-3 are also supplied to the flip-flops 6-0 to 6-3 as latch signals.

As a result, the flip-flops 6-0, 6-
Outputs of the selectors 4-0, 4-1 and 4-2, that is, FIG. 4 are provided to 1, 6-2 in accordance with the logical "1" outputs of the OR circuits 5-0, 5-1 and 5-2. As shown in (b), three comparison instructions processed in parallel (SLE comparison instruction, SGE comparison instruction, SEQ
The result of the comparison operation designated by the comparison instruction) is latched. The flip-flops 6-0, 6-1 and 6-2 correspond to the bit positions (bits 0, 1, 2) in the flag register 6 designated by (the operand C of) these three comparison instructions. Therefore, in this embodiment, the result of the comparison operation performed on the operands A and B respectively designated by the SLE comparison instruction, the SGE comparison instruction, and the SEQ comparison instruction processed in parallel is the flag register 6 designated by the operand C of the instruction. Will be stored in parallel at the bit positions (bits 0, 1, 2). Note that the content of bit 3 (flip-flop 6-3) of the flag register 6 does not change and the previous state is held (here, it is assumed to be "0").

When the parallel processing of the above three comparison instructions is completed, the processing of the conditional branch instruction (here, the BNZ conditional branch instruction) is started, as is apparent from FIG. Then, the BNZ conditional branch instruction is decoded by a decode circuit (not shown), and the 4-bit mask value M designated by the instruction is read from a general-purpose register or the like (not shown). The mask value M in this embodiment is "1110" (7 in hexadecimal notation), and specifies that the conditional branching according to the value of bits 0-2 of bits 0-3 of the flag register 6 is performed. It is also possible to have this mask value M in the conditional branch instruction. Further, by the above-mentioned BNZ conditional branch instruction decoding, the branch destination address L (here, $ 1) designated by the instruction is obtained, and the branch taken condition designation signal B is further obtained.
TC (here, "1") is generated.

The 4-bit mask value M designated by the BNZ conditional branch instruction is stored in the branch instruction decode buffer 7. The mask value M stored in this buffer 7 is 4
It is read out to the instruction fetch address generation circuit 8 together with the output of the bit flag register 6.

The logical product circuit 81 in the instruction fetch address generation circuit 8 and the 4-bit output value of the flag register 6 and 4
The logical product of each bit corresponding to the bit mask value M is calculated. The logical product result of the logical product circuit 81 is the zero determination circuit 8
2 is supplied. The zero determination circuit 82 is an AND circuit 81.
It is determined whether or not the 4-bit logical product results of all are "0", and if all are "0", a signal of "1" is output, and if not, a signal of "0" is output.

The output signal of the zero decision circuit 82 is supplied to the exclusive OR circuit 83 together with the branch taken condition designating signal BTC. When BTC = 0, the exclusive OR circuit 83 outputs the output signal (zero / non-zero determination result) of the zero determination circuit 82 as it is as the branch taken / not taken signal T / F. On the other hand, when BTC = 1 as in this embodiment,
The exclusive OR circuit 83 inverts the level of the output signal (zero / non-zero determination result) of the zero determination circuit 82 and outputs it as a branch taken / not taken signal T / F. The branch taken / not taken signal T / F output from the exclusive OR circuit 83 is used as a selection signal of the selector 85.

The selector 85, when T / F = 1,
The branch destination address L (here, $ 1) designated by the conditional branch instruction (here, the BNZ conditional branch instruction) is selected as the address of the instruction to be executed next, and when T / F = 0, The next instruction address indicated by the program counter 84,
That is, the instruction address next to this conditional branch instruction (BNZ conditional branch instruction) is selected as the address of the instruction to be executed next.

As described above, when the BNZ conditional branch instruction shown in FIG. 4B is executed, the address of the instruction to be executed next to the same instruction (branch destination address or next instruction address)
, But three comparison instructions executed in parallel prior to the same instruction (SLE comparison instruction, SGE comparison instruction, SEQ comparison instruction)
Is generated by the instruction fetch address generation circuit 8 according to the execution result of (compound condition consisting of).

Here, if even one of the execution results of the above three comparison instructions is satisfied, that is, if the composite condition shown in FIG. It becomes “0” indicating zero, and the branch taken / not taken signal T / according to the branch taken condition designating signal BTC of logic “1”.
Since F becomes "1", the branch destination address $ 1 designated by the BNZ conditional branch instruction is generated (selected). On the other hand, if all the execution results of the above three comparison instructions are not satisfied, that is, if the composite condition shown in FIG. 4A is satisfied, the output of the zero determination circuit 82 is zero. It becomes "1" as shown, and a branch taken condition designation signal BT of logic "1"
Since the branch taken / not taken signal T / F becomes "0" according to C, the next instruction address from the program counter 84 is generated (selected). Then, the instruction of the generated address is fetched.

Now, assuming that each instruction can be executed in one cycle, in the program processing of this embodiment shown in FIG. 4B, three comparison instructions are processed in parallel before the processing when the condition is satisfied. 2 cycles of 1 cycle for executing the next conditional branch instruction and 1 cycle for processing the next conditional branch instruction. On the other hand, in the example of the prior art shown in FIGS. 6B and 6C, 6 cycles and 4 cycles are required, respectively, and many cycles are required as compared with the present embodiment.

The comparison result held in the flag register 6 is held as it is, unless the same bit position is designated by another comparison instruction executed thereafter. Therefore, the comparison result should be reused. You can In this case, it is not necessary to execute the same comparison instruction again.

Although the composite condition processing for the composite condition combined by the logical product has been described above, it can be applied to the composite condition processing for the composite condition combined by the logical sum. However, the setting value for the flag register 6 needs to be "1" when the comparison judgment of the comparison instruction is not established contrary to the above-mentioned embodiment.

Further, although the case where the three comparison instructions are processed in parallel has been described above, the present invention is not limited to this, and the present invention can process a plurality of comparison instructions in parallel. It is applicable to all parallel processors. Further, the instructions to be processed in parallel do not have to be independent, and can be applied to a parallel processing device that applies an instruction having a plurality of instruction word fields (so-called VLIW instruction) in one instruction.

[0049]

As described in detail above, according to the present invention, each bit of the bit position in the flag register means designated by the comparison instruction is independently and independently according to the truth value of the execution result of the plurality of comparison instructions. When set / reset in parallel and then a conditional branch instruction is executed, it is determined whether or not branch is executed with the bit state of each bit position of the flag register means indicated by the mask value designated by the instruction as a composite condition. Since the configuration is such that it is determined, only one conditional branch instruction is required for the portions that are connected only by the logical product or only the logical sum. For this reason,
Compared to the conventional method that requires a plurality of conditional branch instructions, the overhead of branch processing can be significantly reduced, and the effect of speeding up by parallel processing of instructions can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a parallel processing device to which a compound condition processing method of the present invention is applied.

FIG. 2 is a view showing the logical states of output lines Xi to Zi of the decoding circuits 3-1 to 3-3 and the selector (SEL) 4-i in the embodiment.
The figure which shows the correspondence with the selection content of (i = 0-3).

FIG. 3 is a block diagram showing a configuration of an instruction fetch address generation circuit 8 in the same embodiment.

FIG. 4 is a diagram showing an example of a machine language instruction sequence corresponding to a source program accompanied by complex condition processing in the embodiment.

FIG. 5 is a diagram showing a basic form in which a compound condition described in a source program is expressed by a combination of a comparison instruction and a conditional branch instruction.

FIG. 6 is a diagram showing an example of a machine language instruction sequence corresponding to a source program for explaining a conventional compound condition process.

[Explanation of symbols]

2-1 to 2-3 ... Comparison arithmetic unit, 3-1 to 3-3 ... Decoding circuit,
4-0 to 4-3 ... selector (SEL), 5-0 to 5-3 ... logical sum circuit, 6 ... flag register, 6-0 to 6-3 ... flip-flop (F / F), 8 ... instruction fetch Address generation circuit,
81 ... AND circuit, 82 ... Zero determination circuit, 83 ... Exclusive OR circuit, 84 ... Program counter, 85 ... Selector (SEL, instruction fetch address selecting means).

Claims (2)

[Claims] 1. A parallel processing device capable of processing a plurality of instructions in parallel, and flag register means capable of setting / resetting bits independently and in parallel according to the true / false value of the execution result of a plurality of comparison instructions, and this flag. A logical product means for taking a bitwise logical product of the contents held in the register means and the mask value designated by the conditional branch instruction, and the conditional branch instruction depending on whether the output value of the logical product means is zero or not. Each of the bits of the flag register means designated by the mask value, comprising: an instruction fetch address selecting means for selecting a branch destination address designated by or the address of an instruction next to the same instruction as an instruction address to be executed next. A composite condition processing method characterized in that whether or not to execute a branch is determined by using a bit state of a position as a composite condition. 2. The composite condition processing method according to claim 1, wherein the bit position of the flag register means set / reset according to the execution result of the comparison instruction is designated by the comparison instruction.