JP3004108B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which handles a specific instruction having an immediate operand, and more particularly to an immediate operand extension method for extending an immediate operand.

[0002]

2. Description of the Related Art One of various instructions (instruction words) handled by an information processing apparatus such as a computer system is an instruction having an immediate operand. The instruction having the immediate operand has fields such as an instruction code (OP code) field and a destination field in addition to the immediate operand field. Therefore, the size of the immediate operand field that can be secured in the instruction word is limited.

Therefore, conventionally, in order to specify an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word, each function (functions such as an addition operation and a subtraction operation using the immediate operand) is required. For example, a method of preparing instructions corresponding to the size of the immediate operand was applied.

There has also been a system in which an instruction for modifying an immediate operand is prepared, and an immediate operand in a specific instruction word is replaced with a larger immediate operand specified by the instruction.

[0005] In addition, there has been a method in which an immediate operand is divided into an upper order and a lower order, a dedicated load instruction is prepared for each, and an immediate having a large size is used via a register.

[0006]

However, in order to specify an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word, an instruction corresponding to the size of the immediate operand is prepared for each function. In such a method, there is a problem that the number of instructions increases and the instruction system becomes complicated. Further, in this method, since the size of the OP code field in the instruction word becomes large, there is also a problem that the size of the operand designation field is compressed.

[0007] Further, in the method in which an immediate operand specified in an instruction word is simply replaced with an immediate operand specified by a dedicated instruction, there is a problem that an immediate operand having a size larger than the instruction word size cannot be specified.

Further, in the method in which the immediate operand is divided and used via the register, there is a problem that the use of the immediate operand involves an overhead of one fetch cycle or more. Further, in this method, there is a problem that performance degradation due to a register hazard may occur in an information processing device of a pipeline control method.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word.
It is an object of the present invention to provide an information processing apparatus capable of specifying a smaller instruction repertoire (type of OP code) without deteriorating performance.

Another object of the present invention is to provide a parallel processing type information processing apparatus in which an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word causes the number of instruction fetch cycles to increase at all. It is to be able to specify without having to.

[0011]

According to the present invention, there is provided a storage means in which an immediate extension instruction for specifying an immediate extension part of a specific instruction having a field of an immediate operand is arranged immediately before or immediately after the specific instruction; Before executing the instruction, coupling means for coupling the contents of the immediate operand field of the instruction to an immediate portion specified by the immediate extension instruction immediately before or immediately after the instruction is provided.
A specific instruction is executed using the immediate operand connected by the connecting means.

[0012]

The operation in the above configuration is described as VLIW (Very L).
An example in which the present invention is applied to an information processing apparatus (parallel processing unit) of a parallel instruction word (VLIW) type will be described. In a VLIW information processing apparatus,
Processing is performed in units of a predetermined number of fixed-length instructions. This group of a predetermined number of instructions is called a VLIW type instruction (or VLIW type instruction word).

First, in a VLIW information processing apparatus,
A VLI consisting of a predetermined number of fixed-length instructions (to be processed in parallel)
(W-type instruction) is fetched from a main memory or an instruction cache or other storage means. Here, if it is assumed that the VLIW type instruction including the specific instruction and the immediate extension instruction has been fetched, the immediate extension part specified by the immediate extension instruction (the OP code thereof) is (first selection instruction). (By means) and guided to the coupling means. The contents of the immediate operand field of the specific instruction placed immediately before or immediately after the above immediate extension instruction are also guided to this coupling means. As a result, the extended part of the immediate specified by the immediate extended instruction and the contents of the immediate operand field of the specific instruction are connected by the connecting means, and the immediate operand is expanded. If there is no immediate extension instruction, instead of the immediate extension part, for example, data whose value is all 0 is led to the linking means and linked with the contents of the immediate operand field.

The data linked by the linking means (the extended immediate operand if an immediate extension instruction is present) is fetched from the storage means when the specific instruction is executed (selected by the second selecting means). VLIW
It is supplied to the arithmetic unit at a position corresponding to the specific instruction in the type instruction. Thus, if the specific instruction and the VLIW type instruction including the immediate extension instruction immediately before or immediately after the specific instruction are fetched, the immediate extension field specified by the immediate extension instruction and the immediate operand field of the specific instruction The specified operation is performed using an operand concatenated with the contents of the above, that is, an extended immediate operand.

[0015]

FIG. 1 is a block diagram of a main part showing an embodiment of an information processing apparatus (parallel processing unit) of a VLIW system and a pipeline control system to which the present invention is applied.
Note that the pipeline in this embodiment has a four-stage configuration including a fetch (instruction fetch) stage F, a decode (instruction decode) stage D, an execution stage E, and a write-back (write result) stage W.

In FIG. 1, reference numeral 1 denotes a main memory for providing a storage area for various programs and data, and 11 denotes a main memory.
Is a VLIW type instruction stored in the. This VLIW
The type instruction 11 is a compound instruction including four 32-bit instructions I # 1 to I # 4. An instruction cache 2 stores a copy of a part of the instruction group stored in the main memory 1.

Reference numeral 3 denotes a 128-bit instruction register for holding the VLIW type instruction fetched from the instruction cache 2 in the fetch stage F. The instruction register 3 has four instruction fields 41 to 44 in which four instructions constituting a VLIW type instruction are held.

In FIG. 1, an immediate addition instruction having an OP code "add.i" designating immediate addition
1, the OP code “i” specifying the extension of the immediate operand
ext "in the instruction field 32,
The OP code “add.
An immediate addition instruction having "i" is placed in the instruction field 33, and a subtraction instruction having an OP code "sub" designating normal subtraction without using an immediate (subtraction using register data of a register file as an operand) is placed in the instruction field 34 , Respectively, are shown.

FIG. 2 shows the format of the main part of the above three types of instructions (immediate addition instruction, immediate expansion instruction, and subtraction instruction). As is apparent from FIG. 2, the immediate add instruction is a 6-bit immediate operand field i6 (bits 26 to 3).
1), and the immediate immediate instruction is an extended immediate operand field i2 in which a 26-bit extended immediate operand, which is an extended part of the immediate (6-bit immediate operand), is set.
6 (bits 6 to 31).

The OP code of the instruction word included in each instruction is basically composed of 9 bits (higher 9 bits) of bits 0 to 8. However, the OP code “iext” of the immediate extension instruction is substantially equal to the immediate extension instruction with only 5 bits of bits 0 to 4 in order to secure the 26-bit extended immediate operand field i26 (bits 6 to 31). , And is not affected by the contents of the four bits of bits 5 to 9.

In this embodiment, an immediate operation instruction is present in four VLIW instructions, and the immediate operation instruction is the first or third VLIW instruction. , The immediate operand of the immediate operation instruction can be extended. The immediate extension instruction designating the expansion of the immediate operand is placed immediately after the instruction (immediate operation instruction) having the immediate operand to be extended, that is, the second or fourth of the four VLIW instructions. It is supposed to be.

Referring again to FIG. 1, reference numerals 41 to 44 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3, and the OPs of the instruction held in the fields 31 to 34 are provided.
A decoding circuit (DEC) for decoding a code and outputting various decoding signals. Of the four decoding circuits 41 to 44, the decoding circuits 42 and 44 corresponding to the instruction fields 32 and 34 are the OPs to be decoded.
When the code is "iext", there is no operation for specific signals (referred to as mask signals) M2 and M4 of logic "1" and operation units 92 and 94 described later, that is, NOP (no operation) ) Has a decoding function of outputting a signal (not shown). Note that the decoding circuits 41 and 43 may have the same decoding function as the decoding circuits 42 and 44.

Reference numerals 52 and 54 denote inputs A for inputting outputs of the lower 26 bits (bits 6 to 31) of the instruction fields 32 and 34 of the instruction register 3, and decoding circuits 42 and 4, respectively.
AND having a mask input M for inputting mask signals M2 and M4 from H.4 and a 26-bit output Y
The gate. When the mask input M is "1", the AND gates 52 and 54 output the 26 bits of the input A directly to the output Y.
And when the mask input M is “0”, all 26 bits of the output Y are set to “0”.

Reference numeral 61 denotes an immediate value for connecting the 26 bits of the output Y of the AND gate 52 to the output of the lower 6 bits (bits 26 to 31) of the instruction field 31 of the instruction register 3 and transmitting it as immediate data 71 of 32 bits. Data line,
Reference numeral 62 denotes the lower 6 bits (bits 26 to 31) of the instruction field 32 of the instruction register 3 for 26-bit "0" data.
And an immediate data line for transmitting as 32-bit immediate data 72. 63 is an immediate data line for connecting the 26 bits of the output Y of the AND gate 54 to the output of the lower 6 bits (bits 26 to 31) of the instruction field 33 of the instruction register 3 and transmitting it as 32-bit immediate data 73; Reference numeral 64 denotes an immediate data line for linking 26-bit "0" data to the output of the lower 6 bits (bits 26 to 31) of the instruction field 34 of the instruction register 3 and transmitting it as 32-bit immediate data 74.

Numerals 81 to 84 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3. The input R for inputting 32-bit operand data extracted from a register file (not shown) and the immediate data line 61 are provided. To input the 32-bit immediate data 71 to 74, the 32-bit output Y, and the instruction fields 31 to
4 is an immediate operation instruction (having an immediate operand) (decode circuits 41 to 4).
4 from which the specific decode signal is derived). The selectors 81 to 84 switch the output Y to the input I or the input R according to the state of the input S.

Reference numerals 91 to 94 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3, respectively.
34 are arithmetic units that execute the operations designated by. Arithmetic units 91 to
To 94, 32 bits of the output Y of the selectors 81 to 84 are supplied.

Next, the operation of the configuration shown in FIG. 1 will be described. First, the instructions in the main memory 1 are fetched into the instruction register 3 at a fetch stage (fetch cycle) F of the instruction pipeline via the instruction cache 2 in groups of four instructions (that is, in units of VLIW type instructions). Be included. Thereby, V
The first instruction of the LIW type instruction is in the instruction field 31 of the instruction register 3, the second instruction is also in the instruction field 32, the third instruction is in the instruction field 33, and the fourth instruction is in the instruction field 34. Each is retained.

In the next decode stage (decode cycle) D, the instruction fields 31 to 3 of the instruction register 3 are set.
The decoding circuits 41 to 44 perform a process of decoding the OP code of each instruction stored in the instruction circuit 4. In this decode stage D, the immediate data lines 61 to 64
Bit immediate data 71 to 74 are generated. And
The immediate data 71 to 74 or the data from the register file is switched by the selectors 81 to 84 in accordance with the instructions in the instruction fields 31 to 34 (specific decode signals output from the decode circuits 41 to 44 based on the instructions).
It is passed to the computing units 91 to 94 for the next execution stage E.

Here, the generation of the immediate data 71 to 74 will be described in detail. First, the instruction fields 31 to 34
In the instruction fields 32 and 34, there is a possibility that an immediate extension instruction having the OP code "iext" is held as described above. The decode circuits 42 and 44 determine whether the OP code of the instruction held in the instruction fields 32 and 34 is “iext” (when the upper 5 bits of the OP code is a specific value unique to “iext”), When the instruction held in the fields 32 and 34 is an immediate extension instruction, mask signals M2 and M4 for validating the contents (26 bits of bits 6 to 31) of the extended immediate operand field i26 in the instruction. , And arithmetic unit 92,
A signal for instructing NOP is output to 94.

The mask signals M2 and M4 from the decode circuits 42 and 44 are guided to mask inputs M of AND gates 52 and 54. The lower 26 bits (bits 6 to 3) of the instruction fields 32 and 34 are input to the inputs A of the AND gates 52 and 54.
1) is derived.

The AND gates 52 and 54 have a mask input M
Is "1", that is, when the instruction held in the instruction fields 32 and 34 is an immediate extension instruction (having the OP code "iext"), 26 bits of the input A, that is, the instruction fields 32 and 34 Extended immediate operand field i26 which is the lower 26 bits (bits 6 to 31) of
Is output to the output Y as it is.

On the other hand, when the mask input M is "0", that is, when the instruction held in the instruction fields 32 and 34 is not an immediate extension instruction, the AND gate 52 outputs the output Y.
Are all "0" regardless of the contents of input A.

The 26 bits of the output Y of the AND gates 52 and 54 are guided to the upper side of the 32-bit immediate data lines 61 and 63. The remaining lower 6 of these immediate data lines 61 and 63
On the bit side, the contents of the lower 6 bits (bits 26 to 31) of the instruction fields 31 and 33 located immediately before the instruction fields 32 and 34 are led, and the 32-bit immediate data is 71 and 73 are generated.

As a result, if the instruction fields 32, 34
If the immediate extension instruction is held in the immediate data lines 61 and 63, the upper 26 bits of the immediate data 71 and 73 generated are the contents of the extended immediate operand field i26 of the immediate extension instruction (bits 6 to 31). 26 bits). The remaining lower 6 bits of the immediate data 71, 73 are the immediate operand field i6 of the instruction (in this case, always an immediate operation instruction) held in the instruction fields 31, 33 immediately before the instruction fields 32, 34. (6 bits of bits 26 to 31) itself.

That is, the instruction field 3 of the instruction register 3
When the immediate operation instruction is held in the instruction 1, 33, the immediate operand (6 in the immediate operand field i6) of the instruction is held.
Bit) is concatenated with the extended immediate operand (26 bits of the extended immediate operand field i26 of bits 6 to 31) of the immediate extended instruction if the instruction held in the instruction fields 32 and 34 is an immediate extended instruction. , 6
It is expanded from bits to 32 bits.

On the other hand, if the instruction held in the instruction fields 32 and 34 is not an immediate extension instruction, the immediate data 71 and 73 generated on the immediate data lines 61 and 63 will be described.
Are all "0". The remaining lower 6 bits of the immediate data 71 and 73 are the same as the 6 bits of bits 26 to 31 of the instruction held in the instruction fields 31 and 33 (the content of the immediate operand field i6 in the case of an immediate operation instruction). Become.

Therefore, when the instruction fields 31 and 33 hold an immediate operation instruction and the instruction fields 32 and 34 hold instructions other than the immediate extension instruction, the immediate data 71 on the immediate data lines 61 and 63 are stored. , 73 are 6 bits of the immediate operand field i6 of the immediate operation instruction of the instruction fields 31 and 33, which are directly expanded to 32 bits as unsigned data (all the upper 26 bits are “0”).

In the example shown in FIG. 1, the instruction fields 31, 32, 33, and 34 of the instruction register 3 respectively include an immediate addition instruction having an immediate operand, an immediate extension instruction having an extended immediate operand, and an immediate addition instruction having an immediate operand. ,
A normal subtraction instruction without an immediate operand is held. In the decode stage D in the state of FIG. 1, the mask signal M2 from the decode circuit 42 corresponding to the immediate value extension instruction becomes "1", and the mask signal M4 from the decode circuit 44 corresponding to the subtraction instruction becomes "0". . Further, a signal instructing NOP is output from the decode circuit 42 to the arithmetic unit 92.

When the mask signal M2 from the decode circuit 42 is "1", 26 bits of the extended immediate operand field i26 of the immediate extended instruction of the instruction field 32 are set to A bits.
The data is directly output to the upper side of the immediate data line 61 by the ND gate 52. To the remaining lower 6 bits of the immediate data line 61, 6 bits of the immediate operand field i6 of the immediate addition instruction of the instruction field 31 are led. As a result, on the immediate data line 61, 32-bit immediate data 71 is generated by extending the 6-bit immediate operand of the immediate addition instruction of the instruction field 31 with the 26-bit extended immediate operand of the immediate expansion instruction of the instruction field 32. FIG. 3 shows the relationship between the immediate operand of the immediate addition instruction and the extended immediate operand of the immediate extension instruction and the immediate data (71).

The immediate data 71 on the immediate data line 61 is guided to the input I of the selector 81. Input S of selector 81
Is supplied with a specific decode signal from the decode circuit 41 indicating that the instruction held in the instruction field 31 is an immediate operation instruction (here, an immediate addition instruction). In this case, the selector 81 switches the output Y to the input I side.
As a result, the expanded immediate data 71 guided to the input I of the selector 81 is selectively output from the output Y and passed to the computing unit 91, where it is calculated at the next execution stage E (addition in this case). Calculation).

As described above, in the present embodiment, the immediate addition instruction (immediate operation instruction) and the immediate extension instruction are combined, and
The specified operation (addition operation) can be performed using the extended immediate value as if it were one instruction having a 2-bit immediate value.

When the mask signal M4 from the decode circuit 44 is "0", the output Y of the
All bits are set to "0". This 26-bit "0"
The data is guided to the upper side of the immediate data line 63. On the remaining lower 6 bits of the immediate data line 63, an immediate operand field i6 of the immediate add instruction of the instruction field 33 is provided.
Are derived. Thereby, the immediate data line 63
Above, the 6-bit immediate operand of the immediate addition instruction in the instruction field 33 is simply extended as unsigned 6-bit data to 32 bits in form (the upper 26 bits are all "0").
The generated immediate data 73 is generated.

The immediate data 73 on the immediate data line 63 is guided to the input I of the selector 83. Input S of selector 83
, A specific decode signal from the decode circuit 43 indicating that the instruction held in the instruction field 33 is an immediate operation instruction (here, an immediate addition instruction). In this case, the non-extended immediate data 73 guided to the input I of the selector 83 is selectively output from its output Y and passed to the computing unit 93, where it is computed at the next execution stage E (here, (Addition operation).

Next, the instruction field 3 of the instruction register 3
In the computing unit 92 corresponding to No. 2, the computation is not performed by the signal indicating the NOP output from the decoding circuit 42 in response to the immediate extension instruction held in the instruction field 32. In this case, the immediate data 7 on the immediate data line 62
2 is discarded.

Next, the instruction field 3 of the instruction register 3
4, the data of the register file (of the register specifying field) of the normal subtraction instruction held in the instruction field 34 is stored in the input R
Is led to. To the input S of the selector 84, a specific decode signal from the decode circuit 44 indicating that the instruction held in the instruction field 34 is not an immediate operation instruction is led. In this case, the selector 84 switches the output Y to the input R side. As a result, the data of the register file guided to the input R of the selector 84 is selectively output from the output Y and passed to the computing unit 94, where the operation in the next execution stage E (subtraction operation in this case) is performed. To be served. In this case, the immediate data 74 on the immediate data line 64 is discarded.

According to this embodiment, assuming that the types of operation (functions) of the immediate operation instruction are, for example, six, the type of instruction to be increased is to expand the 6-bit immediate operand of the immediate operation instruction to 32 bits. There is only one kind of immediate extension instruction that designates that. On the other hand, in the conventional method in which instructions corresponding to the size of the immediate operand are prepared for each function, the number of instruction types to be increased is the number of operation (function) types of immediate operation, that is, six. It requires five more instructions than this method.

In the above-described embodiment, the case where the instruction to be extended by the immediate extension instruction (having an immediate value) is an immediate addition instruction has been described. However, the target instruction may be an immediate subtraction instruction, an immediate multiplication instruction, or the like. Other immediate operation instructions may be used, and the function of the immediate operation is not limited.

Further, in the above-described embodiment, the case where the instruction to be extended by the immediate extension instruction is arranged immediately before the immediate extension instruction has been described, but the present invention is not limited to this. For example, as shown in FIG. 4, the present invention can be applied to a case in which it is arranged immediately after. In this case, the decoding circuit 4 corresponds to the position in the VLIW type instruction where the immediate extension instruction is allowed to exist.
2 and 44, and AND gates 52 and
AND gate (or a selector for selecting one of the contents of the extended immediate operand field i26 of the immediate extended instruction and 26-bit data of all "0") corresponding to the instruction position immediately before it. Needless to say, it is necessary to provide immediate data lines corresponding to the immediate data lines 61 and 63.

In the above embodiment, the present invention is applied to the VLIW
The case where the present invention is applied to the information processing apparatus of the system has been described.
The present invention is also applicable to an information processing apparatus employing an SC type architecture. In this case, the sequence of the instructions to be extended (for example, an immediate addition instruction) and the immediate extension instruction and the generation of the immediate data (extended immediate) will be briefly described with reference to FIGS. I do. FIG. 5A shows a case where the instruction array is an immediate addition instruction and an immediate extension instruction in this order.
(B) shows a case where the instruction array is an immediate extension instruction and an immediate addition instruction in this order.

First, in the case of FIG. 5A, at the same time as decoding the immediate addition instruction, the next immediate expansion instruction is fetched. Immediately after fetching the immediate extension instruction, this instruction is replaced with the immediate operand (i) of the immediately preceding instruction (immediate addition instruction).
6) is recognized as an instruction for extending the instruction, the execution stage of the immediately preceding instruction (immediate addition instruction) is delayed, and the immediate operand is replaced with an extended instruction in the meantime, or by the next pipeline cycle. The immediate operand is replaced with the expanded one, the pipeline is advanced as it is, and the operation is executed using the expanded immediate operand (immediate data).

Next, in the case of FIG. 5B, it is recognized that the immediate extension instruction is decoded to extend the immediate operand of the next instruction (immediate addition instruction), and the next instruction (immediate addition instruction) is recognized.
Before execution of the instruction, the immediate operand of the instruction (immediate addition instruction) is replaced with an extended immediate operand (immediate data). In the method shown in FIG. 5B, compared to the method shown in FIG. 5A, from the recognition of the extension to the replacement with the extended immediate value,
A margin of two pipeline cycles can be secured.

In the above-described embodiment, the case where the size of the extended immediate operand set in the immediate extension instruction is limited to 26 bits is described. However, the present invention is not limited to this. May be set. However, it is necessary to prepare a plurality of types of immediate extension instructions corresponding to the size of the extended immediate operand. In addition, coupling means (immediate data lines) for coupling the immediate operand of the immediate operation instruction and the extended immediate operand of the immediate extension instruction are provided for the size of the extended immediate operand, and one of them is provided according to the immediate extension instruction. Must be selected.

In this method, for example, assuming that the operation (function) type of the immediate operation instruction is 6, and the size of the immediate operand is three types, that is, the immediate operand without extension and the two types of extended immediate operand, the instruction type which increases Is only 2 (two types of immediate extension instructions), which is the number of types of extended immediate operand sizes. On the other hand, in the conventional method in which instructions corresponding to the size of the immediate operand are prepared for each function, the number of instruction types to be increased is (operation (function) type × extended immediate operand size type = 6 × 2 = 12). Yes, it requires 10 more instructions than this method. The difference between the instruction types increases as the number of types of the extended immediate operand size increases.

[0054]

As described in detail above, according to the present invention,
An immediate extension instruction that specifies an immediate extension part of a specific instruction (immediate operation instruction) having a field of an immediate operand is provided, arranged immediately before or immediately after the specific instruction, and when executing the specific instruction, The extended immediate part specified by the immediate extension instruction immediately before or immediately after the instruction is concatenated with the contents of the immediate operand field of the instruction to generate an extended immediate operand. Since the configuration is such that the specific instruction is executed by using the instruction, the following effects can be obtained.

(1) Regardless of the type of an instruction having an immediate value (immediate operation instruction), immediate extension can be performed by an immediate extension instruction of the same type, so that an instruction repertoire (type of OP code)
Can be minimized. For this reason, OP
There is no danger that the size of the code field will increase, and the size of the operand designation field will not be squeezed.

(2) When the present invention is applied to a parallel processing type information processing apparatus, an immediate operation instruction and an immediate extension instruction to be extended to the same instruction (immediate operand) are combined, and one having an extended immediate operand is obtained. Since it can be handled as if it were one instruction, an immediate operand having a size exceeding the size of the immediate operand field that can be secured in the instruction word can be specified without increasing the number of instruction fetch cycles at all.

(3) Just by placing an immediate extension instruction immediately before or immediately after a normal immediate operation instruction, an extended immediate operand can be designated, and the immediate extension instruction alone can designate the immediate operand of the instruction itself. Therefore, the instruction system can be simplified, and thus the hardware configuration can be simplified, as compared with the conventional method that causes a significant increase in the instruction repertoire.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part showing an embodiment of an information processing apparatus (parallel processing unit) of a VLIW system and a pipeline control system to which the present invention is applied.

FIG. 2 is a diagram showing a format of a main part of an immediate addition instruction, an immediate expansion instruction, and a subtraction instruction used in the embodiment.

FIG. 3 is a view showing a relationship between an immediate operand of an immediate addition instruction and an extended immediate operand of an immediate expansion instruction arranged immediately after the instruction in the embodiment, and immediate data;

FIG. 4 shows the positions of an immediate addition instruction and an immediate extension instruction in FIG.
The figure which shows the relationship between the immediate data of the immediate operand of the immediate addition instruction | indication, the extended immediate operand of the immediate expansion instruction, and the immediate data in the case opposite to the example of FIG.

FIG. 5 is a diagram showing the relationship between immediate data of an immediate operand of an immediate addition instruction and an extended immediate operand of an immediate expansion instruction in an information processing apparatus employing a RISC architecture;

[Explanation of symbols]

1. Main memory, 2. Instruction cache, 3. Instruction register,
31 to 34: instruction field, 41 to 44: decoding circuit, 52, 54: AND gate (first selecting means), 6
1-64: immediate data line (connection means), 71-74 ... immediate data, 81-84 ... selector (second selection means),
91 to 94: arithmetic unit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-201133 (JP, A) JP-A-3-194621 (JP, A) JP-A-3-259340 (JP, A) JP-A-3-259340 218526 (JP, A) JP-A-62-107339 (JP, A) JP-A-54-129944 (JP, A) JP-A-57-45648 (JP, A) JP-A-62-125435 (JP, A) JP-A-62-297938 (JP, A) JP-A-62-3338 (JP, A) JP-A-3-147021 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (1)

(57) [Claims] 1. A method for processing a plurality of fixed-length instructions in parallel.
Parallel processing type information processing device having the same number of arithmetic units
The immediate value of a specific instruction with an immediate operand field
An immediate extension instruction that specifies the extension part is paired with the specific instruction.
Storage means arranged in parallel and a plurality of pieces to be processed in parallel fetched from this storage means
Instructions with the same number of instruction fields that hold the same instruction
A register is provided for each instruction field of the instruction register.
Immediate data in the data line and the corresponding instruction field.
From the lower data line connected to the part that can be placed
Among the immediate data lines and the instruction fields of the instruction register,
At least, the immediate extension instruction is allowed to be retained.
The first selection provided for each of the instruction fields
Selecting means for storing the instruction register from the storage means.
A plurality of instructions including a pair of the specific instruction and the immediate extension instruction
Is fetched, and the immediate
Field, the value of the immediate
Select the immediate extension part to be paired with the immediate extension instruction.
Immediate operand field contents of the specific instruction
Above the immediate data line with the lower data line from which
Output to the next data line, and
When an instruction other than the immediate extension instruction is held, the value is 0.
Select the fixed data of
First selecting means for outputting data to the command line;
(2) selecting means, wherein said corresponding instruction field has
If a specific instruction is held, the corresponding instruction field
Data on the immediate data line as an immediate operand
The above-described operation of selecting and executing an operation specified by the specific instruction.
And a second selecting means for outputting to the arithmetic unit.
Information processing device.