JP2583614B2 - Vector arithmetic unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a vector processing apparatus, and more particularly, to a vector operation apparatus which improves performance when scalar data is used as an operand of a vector operation. It is about.

[Prior Art] In recent years, in the field of scientific and technological calculations, vector processing apparatuses, such as so-called vector computers, having a vector operation function have become widespread.

In a conventional information processing apparatus, one instruction called a scalar instruction operates on one data, whereas in a vector processing apparatus, an instruction called a vector instruction is generally employed. It is.

Unlike a scalar instruction, a vector instruction has a function of calculating a plurality of data (referred to as a vector element) with one instruction and generating a plurality of results. That is, in the vector processing of the vector processing device, the vector operand to be processed usually includes a plurality of vector elements.

 FIG. 2 shows an example of an apparatus constituting the vector processing apparatus.

As shown in the figure, a vector processing device usually includes a main storage device (hereinafter abbreviated as MS) 103, a central processing device (hereinafter abbreviated as CPU) 200, and an input / output processing device (hereinafter abbreviated as IOP) 20.
1 and a vector operation device (hereinafter abbreviated as VF) 202.

The CPU 200 performs normal processing using a conventional scalar instruction. When a vector instruction further appears, the CPU 200 sends parameters and operand data accompanying the instruction to the VF 202.

 Then, a vector operation is performed in the VF 202.

By the combination of vector instructions, vector processing is
The first step of transferring a vector element from a register in the MS 103 or the CPU 200 to the VF 202, the second step of executing a vector operation in the VF 202, and finally extracting the result of the vector operation from the VF 202,
Can be divided into a third step of storing the data in the register inside the register.

When the processing steps are divided in this way, it is necessary to temporarily store the vector element that is the operand in the VF 202. Therefore, a general method of a vector processing device is to prepare a register group called a vector register for the purpose of temporarily holding a vector element.

Regarding the configuration of the vector register and the general specification of the vector instruction in the vector processing device described above, for example, “IBM System / 370” which is a publication issued by IBM Corporation
Vector Operations "(SA22-7125-0).

As is apparent from the above publication, floating point registers (hereinafter referred to as FR) are included in the vector instructions constituting the vector operation.
There is a QV-format Load instruction for performing a predetermined operation while expanding the scalar data, which is the content of the scalar data, into a series of elements of a vector register. This instruction converts scalar data into vector data.

Other instructions such as loading a zero into each element of the vector register, such as the Load Zero instruction, and a stride of 0
The VST format Load instruction also has a function of converting scalar data to vector data.

In other words, these instructions are intended to uniformly treat scalar data as vector data by converting them into vector data by expanding them into elements of a vector register in order to simplify processing and improve processing speed. .

[Problem to be Solved by the Invention] A conventional vector operation device which satisfies the function of loading the scalar data as a vector element into a vector register will be described with reference to FIG.

FIG. 4 is a block diagram showing a configuration around a vector register of a conventional vector operation device.

In the figure, control device 401, fixed value generation circuit 404, selector 40
5, input buffer register 406, element selection circuit 40
9. The output buffer register 408 belongs to the VF 202.

The scalar data to be loaded is sent from the FR 402, the MS 403 or the fixed value generation circuit 404 to the selector 405. The selector 405 selects one of the three inputs according to the type of the vector instruction decoded by the control device 401, and stores the input data of the vector register in the input buffer register.
Set to 406.

After that, the control device 401 writes the contents of the input buffer register 406 into the vector register 407 via the element selection circuit 409 in ascending order from element number 0.

This writing usually requires one machine cycle, even in the case where it is early for one element. Therefore, if the vector register is composed of N elements, it takes N machine cycles to load at least the scalar data into all the elements of the vector register. This has been one problem of performance improvement.

In order to solve such a problem, a method of simultaneously loading scalar data into a plurality of elements of the vector register is conceivable. However, according to this means, disadvantages on the apparatus such as the apparatus scale and cost are greatly increased. In practice, there is a limit to the number of elements that can be loaded simultaneously.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a vector operation device including a means for loading scalar data into a vector register, which can further improve the performance of vector processing without increasing disadvantages on the device, and an information processing device. It is in.

[Means for Solving the Problems] The present invention, in order to achieve the above object,
This is a vector operation method in which an operand stored in a vector register is read and a vector operation is executed. If the operand is scalar data, the scalar data is stored in a predetermined register in place of the vector register in advance, A vector operation method is provided in which, when a vector operation is performed, an operand is read from the predetermined register instead of the vector register and the operation is executed.

According to another aspect of the present invention, there is provided a vector operation apparatus having means for executing a vector operation using operands stored in a plurality of elements of a vector register, wherein the operand of the vector operation is scalar data. In some cases, instead of a vector register, a register for storing the scalar data, and when an operand of a vector operation is scalar data, the content of the register is replaced by the vector instead of the content stored in the vector register. Means for supplying to a means for executing an operation.

Further, the present invention is a vector operation device having means for executing a vector operation using operands stored in a plurality of elements of a vector register, and when the operand of the vector operation is scalar data, Instead, a register for storing the scalar data, a pointer indicating the correspondence between the contents stored in the register and the elements of the vector register, and the contents of the vector register or the contents of the register are vector-operated according to the state of the pointer. And a means for supplying to the means for executing the vector processing.

Further, according to the present invention, in order to achieve the above object, the vector operation device, a storage device, a central processing unit,
An information processing apparatus including an input / output device, particularly, a vector processing apparatus is provided.

[Operation] According to the vector operation device of the present invention, in addition to the conventional configuration for loading scalar data into the vector register shown in FIG. 4, the register is arranged in parallel with the conventional vector register, and the scalar data is stored in the vector register. Is issued, the scalar data is loaded into the register, but not into the vector register.

If the operand of the vector operation is scalar data, the contents of the register are supplied to the means for executing the vector operation instead of the contents stored in the vector register. The means for executing the vector operation executes the vector operation using the supplied data.

Since the register for loading the scalar data can have a smaller number of elements than the vector register, for example, when the number of elements is "1", the vector instruction is completed by loading the scalar data once. That is, conventionally, loading a vector register of scalar data required a load operation time at least as many times as the number of elements constituting the vector register, but the present invention completes a vector instruction with a smaller number of loads, so that a significant Performance can be improved. Incidentally, the register sets the number of elements to '1'.
It is preferred that

According to the vector operation device of the present invention, for example, as an example, scalar data is loaded into a register, the value of a pointer is set to '0', and the pointer has valid contents in the vector register. When the pointer is set to indicate the number of the last element storing the pointer, the elements of the vector register starting from 0 to the contents of the pointer minus 1 are valid, and the pointer is used as the vector element for the element number following the contents of the pointer. Indicates that the data stored in the register is valid. Therefore, when the pointer is '0', it means that no valid data exists in the vector register.

In this case, the pointer is stored in the vector register.
When vector data is written, each time data is loaded into each element, +1 is counted up. When a request to read the vector register is received, the contents of the vector register are sent in response to a request to read an element having a value smaller than the value of the pointer. Is sent out.

As a result, in the vector processing device according to the present invention, by providing the register in the vector operation device, the performance of loading the scalar data is significantly improved, and the vector register after the scalar data is loaded. , The function is equivalent to a case where scalar data is loaded in each element to the vector register.

Further, a pointer is provided, and the pointer is controlled to enable / disable the vector element in the vector register. When a read request of the vector register comes,
By dynamically switching the vector element in the vector register or the contents in the register, in the vector processing device according to the present invention, the vector instruction does not need to be aware of the existence of the register at all.

In addition to the scalar data, the required load time and the repeated data may be compressed by controlling the vector element data to be repeated to be represented by one or more data and stored in the register.

In this case, the contents of the register are sent to a vector element read request corresponding to the repeated vector element data to the vector register.

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a configuration centering on a vector register of a vector operation device according to the present embodiment.

The control device 101 is a control device that controls the entire system and sends a predetermined control signal to each unit according to the type of the vector instruction.

The control device 101 controls the selector A10 via the signal line 158.
5. The input buffer register 106 via the signal line 163, the shadow element pointer 111 via the signal line 164, the element selection circuit 109 via the signal line 160, and the signal line 157.
Are connected to the output buffer register 108 respectively.

FR102 is a register storing a scalar operand, and is connected to selector A105 via signal line 151. MS103 is a main storage device for storing vector elements, and is connected to the selector A105 via a signal line 152. The fixed value generating circuit 104 is a device for generating fixed value data such as all-zero data, and is connected to the selector A 105 via a signal line 153. Note that the fixed value generation circuit 10
4 does not need to be provided in a device that does not need to generate a fixed value.

The selector A105 is a selector for selecting data to be transferred to the vector register, and each of the signal lines 151, 152, 153, 158
And 154, FR102, MS103, fixed value generation circuit 10
4. It is connected to the control device 101 and the input buffer register 106.

The input buffer register 106 is a register for temporarily holding a vector register or a shadow vector register, and the selector A10 is connected via signal lines 154, 163 and 155, respectively.
5, connected to the control device 101, the vector register 107 and the shadow vector register 110.

The vector register 107 is a vector register including N elements for storing a plurality of vector elements, and is connected to the input buffer register 106, the element selection circuit 109, and the selector B 112 via signal lines 155, 159, and 156, respectively. .

The shadow vector register 110 is a register composed of a single element for storing scalar data.
155 and 161 are connected to the input buffer register 106 and the selector B 112, respectively.

The element selection circuit 109 is an element number generation circuit that selects a corresponding element when reading and writing to the vector register 107, and is connected to the vector register 107 and the control device 101 via signal lines 159 and 160, respectively.

The shadow element pointer 111 is a register that holds a pointer indicating in which range of the vector register element the contents of the vector register are valid and in which range the contents of the shadow vector register are valid. Via the control device 101
And selector B112.

The selector B112 is a selector for selecting either the output of the vector register or the output of the shadow vector register when there is a request to read data from the vector register. The selector B112 is connected to the vector register via signal lines 156, 161, 162 and 165, respectively. 107, shadow vector register 11
0, connected to the output buffer register 108 and the shadow element pointer 111.

The output buffer register 108 is a register for temporarily holding data sent from the selector B 112, and is a signal line 162
And 157 are connected to the selector B 112 and the control device 101.

 Hereinafter, the operation of the present invention will be described.

When decoding the vector instruction, the control device 101 determines the source of the vector operand according to the type of the instruction, if the decoded vector instruction is to load the vector element data into the vector register, and selects the selector A105. Sends a data selection signal to The selector A105 is based on the instruction from the control device 101, FR102, MS
The output of either 103 or the fixed value generation circuit 153 is selected and set in the input buffer register 106.

The decoding of the vector instruction can be realized by referring to a status register (not shown).

Thereafter, when the data to be loaded into the vector register is a vector element, the control device 101 writes the contents of the input buffer register 106 into a predetermined element of the vector register 107.

The above operation is repeated according to the decoded vector instruction.
Element 0 to element N of vector register 107
When the loading of the vector elements N times up to -1 is completed, the loading processing to the vector register is completed.

When the control device 101 decodes a vector instruction for loading scalar data into the vector register, the selector A 105 selects predetermined input data and sets the data in the input buffer register 106.

The data set in the input buffer register 106 is now set not in the vector register but in the shadow vector register 110 by a command sent from the control device 101 via the signal line 163.

At the same time, the control device 101 sets the content of the shadow element pointer 111 to zero, indicating that data corresponding to all elements of the vector register 107 exists in the shadow vector register 110.

Since the number of elements of the shadow vector register 110 is "1" in this embodiment, the execution of the vector instruction at this time is completed by one data load. At this time, the contents of the shadow element pointer are not changed.

The above operation requires N times of loading to execute a vector instruction to load a vector element into the vector register 107, whereas executing a vector instruction to load scalar data into the vector register 107 , Only one data load to the shadow vector register 110 is performed.

That is, in the conventional loading of the scalar data into the vector register as described above, the scalar data is expanded into each element of the vector register 107 by N times of loading by the same method as the vector element. The number of data loads is 1 / N, and the performance is greatly improved.

Next, after the scalar data is loaded into the shadow vector register 110 as described above, the control device 101
When the controller 101 decodes the vector instruction for reading the vector register, the control device 101 instructs to activate the shadow element pointer via the signal line 164.

At this time, since the shadow element pointer is set to '0' when scalar data is loaded, the selector B112
Determines that the data corresponding to elements 0 and subsequent elements of the vector register 107 has valid contents of the shadow vector register, selects the data of the signal line 161 which is the output of the shadow vector register 110, and passes through the output buffer register 108 Then, the request is sent to the control device 157 that is the request source.

In this case, the same data from the shadow vector register 110 is sent in response to a read request for all elements.

Thereafter, next, when the control device 101 decodes the vector instruction for loading the vector element into the vector register, the control device 101 recognizes that the previous load to the main vector register has been performed to the shadow vector register. , The update of the shadow element pointer is instructed via the signal line 164.

This update instruction is to sequentially add “1” each time a vector element is loaded to each element from element 0 of the vector register 107.

Therefore, the shadow element pointer sets its value to M
Then, the data corresponding to elements 0 to M-1 of the vector register 107 are stored in the vector register 10.
7 indicates that the content is valid, and data corresponding to elements M to N-1 indicates that the content of the shadow vector register 107 is valid.

Thus, when the vector instruction for loading the N vector elements into the vector register 107 is interrupted by some factor such as an interrupt, the shadow element pointer 111 stores the element number 0 and the element number N-1.
Is frozen on the way.

After this state, when the control device 101 decodes a vector instruction for reading the vector register 107, the selector B11
2 is to extract from the vector register 107 data with an element number equal to or less than the value of the shadow element pointer 111-1 and to extract from the shadow vector register 110 data with an element number equal to or more than the value of the shadow element pointer 111.

This is shown in FIG. In FIG. 3, the vector register 107 is loaded with vector elements from element 0 to element m-1, and the element m
Hereinafter, scalar data loaded with vector elements is assumed to be valid.

 At this time, the value of the shadow element pointer is m.

In this state, when the contents of the vector register are read, the selector B 112 in FIG.
7 is transmitted, and the contents of the shadow vector register 110 are transmitted for a read request specifying the element number indicated by b.

By the above-described processing using the shadow element pointer, the processing can be resumed from the point at which the processing interrupted due to an interrupt or the like is interrupted.

The shadow element pointer 111 may not be provided in a device that does not interrupt the load processing to the vector register due to an interrupt or the like. Also, therefore:
The processing using the shadow element pointer 111 need not be performed.

In the above-described embodiment, for convenience of explanation, the vector register 107, the shadow vector register 110, and the shadow element pointer 111 each represent one set, but the VF 202 usually includes a plurality of vector registers 107. Accordingly, a plurality of input buffer registers 106, output buffer registers 108, and the like are provided accordingly. In this case, a plurality of shadow vector registers and shadow element pointers may be provided correspondingly, and each may operate in the same manner as in the above embodiment.

As described above, the vector operation device according to the present embodiment
According to VF202, the operation of loading scalar data into the vector register 107 can be realized by a single loading operation regardless of the element capacity of the vector register, and a vector processing device with greatly improved vector instruction processing performance can be provided. . Further, it is possible to provide a vector processing device which also satisfies the conventional read function in the read operation itself of the vector register.

[Effects of the Invention] As described above, according to the present invention, a vector including a means for loading scalar data into a vector register can further improve the performance of vector processing without increasing disadvantages on the device. An arithmetic device and an information processing device, particularly, a vector processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration centering on a vector register in a vector operation device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a vector processing device according to an embodiment of the present invention. FIG. 4 is an explanatory diagram showing the concept of a vector register read process, and FIG. 4 is a block diagram showing a configuration centering on a vector register in a vector operation device according to a conventional technique. 101: control unit, 102: floating-point register (FR),
101: Main memory (MS), 104: Fixed value generation circuit, 105:
... Selector A, 106 ... Input buffer register, 107 ...
Vector register, 108 ... Output buffer register, 109
…… Element selection circuit, 110 …… Shadow vector register, 111 …… Shadow element pointer, 112 ……
Selector B.

Claims (2)

(57) [Claims] 1. Means for storing an operand of a vector operation in a plurality of elements of a vector register, and means for executing a vector operation using an operand stored in an element of the vector register which has been subjected to a vector operation. A vector operation device, wherein, when an operand of a vector operation is scalar data, a register that stores the scalar data in place of each element of a vector register, a register that stores the scalar data, and the register A pointer indicating the correspondence with the element that has replaced the data storage, and the fact that the element subjected to the vector operation corresponds to the register does not indicate that the element corresponds to the register. The contents of the targeted element Means for executing the vector operation by supplying the contents of the register to the means for executing the vector operation when the pointer indicates that the element subjected to the vector operation corresponds to the register; And a means for supplying to the vector processor. And means for storing operands of the vector operation in a plurality of elements of the vector register, and means for executing the vector operation using the operands stored in the elements of the vector register which are the targets of the vector operation. A vector operation device, comprising: a first register, means for determining whether or not an operand of a vector operation is scalar data, and, when the operand of a vector operation is scalar data, Means for storing in the first register instead of each element of the vector register, a second register for storing a pointer, and a range of a vector register element in which storing of the scalar data is replaced with the first register. Means for setting the value of the pointer as follows:
If the element subjected to the vector operation is not included in the range indicated by the pointer, the contents of the element subjected to the vector operation of the vector register are output to the means for executing the vector operation, and the vector operation is performed. And selecting means for outputting the contents of the first register to the means for executing the vector operation when the element targeted for is included in the range indicated by the pointer. apparatus.