JPH02148140A - Conditional branch control system for information processor - Google Patents

Abstract

PURPOSE:To increase the branch instruction processing speed by determining a condition code before completion of an operation instruction to control branch or non-branch at the time when the condition code can be determined in an early stage. CONSTITUTION:A time discriminating part 6 discriminates whether the condition code can be determined in an early stage by an auxiliary computing element 5 or not in accordance with input data. When the condition code can be determined in the early stage, branch or non-branch of the conditional branch instruction is controlled in accordance with the condition code obtained from the auxiliary computing element 5 before the arithmetic operation is completed by a main computing element 4; but the condition code from the main computing element 4 is used to control branch or non-branch only when the condition code cannot be determined in the early stage. Thus, the condition code is mainly determined independently of the execution time of the operation instruction to increase the processing speed of the conditional branch instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conditional branch control method in an information processing device, and particularly to a conditional branch control method suitable for an information processing device that employs a proactive control method.

[Conventional technology]

As is well known, when a conditional branch instruction is executed in an information processing device, the decision as to whether the conditional branch instruction branches or executes a subsequent instruction without branching is set in the program state word (psw). This is done depending on the value of the condition code. This condition code is determined by the operation result of the previous operation instruction, etc.
This is set to W.

On the other hand, in an information processing device that employs a proactive control method, a plurality of instructions are processed in parallel in a pipeline manner, so that instruction processing can be performed at high speed.

However, in the case of conditional branch instructions, the condition code is not determined until the previous arithmetic instruction is completed, and unless the condition code is determined, it cannot be determined whether or not to branch, resulting in a problem of slow execution. There is. Conventionally, as a method to solve this problem, as described in Japanese Patent Publication No. 55-17976, an auxiliary arithmetic unit is provided separately from the main arithmetic unit that executes arithmetic instructions, and the input data of the arithmetic instruction is processed in the auxiliary arithmetic unit. There is a method to quickly determine the condition code. As a result, execution of a branch instruction can be started before the previously executed arithmetic instruction is completed, and it can be determined whether or not the branch instruction causes a branch, so that instruction processing can be performed at high speed.

[Problem to be solved by the invention]

In the conventional technology described above, the auxiliary arithmetic unit uniformly determines the condition code within a fixed time based on the input data of the arithmetic instruction, so there is a problem that the amount of hardware for the auxiliary arithmetic unit increases, resulting in high costs. there were.

In addition, in recent years, information processing devices have become faster and more dense, so as the amount of hardware increases and the spatial floor space increases, signal propagation time increases, resulting in the problem of not being able to perform high-speed processing. be.

An object of the present invention is to determine a condition code before the execution of an arithmetic instruction is completed using a relatively small amount of hardware in a proactive control type information processing device or the like.

The purpose is to speed up branch instruction processing.

[Means to solve the problem]

In order to achieve the above object, the present invention changes the timing at which the control of a conditional branch instruction is determined depending on the input data of the arithmetic instruction.

Specifically, it is equipped with an auxiliary arithmetic unit that determines a condition code early based on part of the input data of an operation instruction, and a timing determination unit that determines when a condition code can be determined according to the value of the input data. If the code can be determined, the condition code is determined before the arithmetic instruction is completed, and whether or not to branch is controlled thereby.

[For production]

The timing determination unit determines whether the condition code can be determined early by the auxiliary computing unit according to the input data. If the condition code can be determined early, the branching/non-branching of the conditional branch instruction is controlled according to the condition code obtained from the auxiliary processor before the main processor completes the operation, and the condition code is determined early. Only when a decision cannot be made, a condition code from the main processor is used to control branching/non-branching.

As a result, most of the condition codes can be determined independently of the execution time of the arithmetic instruction, thereby speeding up the processing of conditional branch instructions. Also, the auxiliary computing unit.

Since there is no restriction that the condition code must be determined within a certain amount of time, the configuration can be configured with a small amount of hardware.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of an embodiment of an information processing apparatus according to the present invention, in which a storage unit 1 stores instructions and operands, an instruction unit 2 controls execution of instructions.
It consists of an execution unit 3 that executes instructions. In addition to the main arithmetic unit 4, the execution unit 3 includes an auxiliary arithmetic unit 5 that calculates a condition code from the input data of the arithmetic instruction, and a auxiliary arithmetic unit 5 that determines when the condition code can be determined according to the value of the input data of the arithmetic instruction. Timing determination section 6. A condition code selection circuit 7 is provided which selects the condition code output 1o from the main arithmetic unit 4 or the condition code output 11 from the auxiliary arithmetic unit 5 in response to the condition code selection signal 12 from the timing determination unit 6. 8 is an operand bus for calculations, and 9 is a data bus for calculation results.

First, the general operation shown in FIG. 1 will be explained. Under the control of the instruction unit 2, the instructions retrieved from the storage unit 1 are decoded by the instruction unit 2 and, if necessary, the operands are retrieved from the storage unit 1 again. The operand is sent to the execution unit 3 through the operation operand path 8, and the operation is executed by the main operation unit 4 in the execution unit 3. The calculation result is transferred to the calculation practical data bus 9.
Through the command unit 28 is returned. Further, the condition code at that time is obtained from the condition code output 10 of the main arithmetic unit 4, and is reported to the instruction unit 2 via the condition code selection circuit 7.

Now, in the information processing device using the advance control method, the instruction unit 2 and the execution unit 3 operate independently and in an overlapping manner.
Multiple instructions are processed in parallel in a pipeline. child\
Assume that each instruction is processed by pipeline control consisting of the following four stages.

(1) Decode (D stage): Decodes instructions and generates logical addresses.

(2) As5ociate (A stage): Converts a logical address to a physical address.

(3) Load (L stage); Reads the storage device.

(4) Execute (E stage): Execute the calculation.

In principle, the D, A, and L stages can complete execution in one cycle regardless of the type of instruction, but the E stage may take multiple cycles depending on the type of instruction. Even in the case of subtraction, the result and condition code can be obtained in one cycle in the case of a binary fixed point number, but it takes two or more cycles in the case of a binary floating point number.

Information on adopting the pipeline control method is shown in Figure 2 (,), which shows how the pipeline operates when there is a conditional branch instruction immediately after an arithmetic instruction whose E stage takes three cycles. In the processing equipment.

As long as the same stages do not overlap, multiple instructions can be processed at the same time, but the instruction following a conditional branch instruction cannot start execution until it is determined whether the branch instruction is a branch or not. In Figure 3 (a), the operation instruction immediately before the conditional branch instruction is in the E stage for 3 cycles or N, so the next instruction after the branch instruction has a waiting time of 2 cycles. This shows that this occurs.

Therefore, as shown in FIG. 1, an auxiliary calculator 5 is prepared separately from the main calculator 4, and the condition code is determined faster than the number of cycles of the E stage required to obtain the calculation result by the main calculator 4. I'll do what I do.

That is, when a condition code is obtained by the auxiliary arithmetic unit S, the condition code selection circuit 7 selects the condition code output 11 of the auxiliary arithmetic unit 5 and quickly reports the condition code to the instruction unit 2.

The operation of the pipeline at this time is shown in FIG. 2(b). In the case of FIG. 2(b), since the condition code is determined at the E stage of the first cycle when the arithmetic instruction is executed, execution of the next instruction can be started immediately after the D stage of the conditional branch instruction. Performance does not deteriorate.

By the way, if the auxiliary computing unit 5 is prepared separately from the main computing unit 4, the following problems arise. Generally E stage 2
An operation that takes more than or equal to N cycles is a complex operation such as a floating point operation, and the auxiliary operation unit 5 is effective when the condition code of such a complicated operation can be determined at high speed. but.

No matter what the operation is, the condition code is sent to the auxiliary operator 5.
If all the information is determined by , a large amount of hardware will be required for the configuration of the auxiliary computing unit 5, and the cost of the information processing device will increase.

In FIG. 1, the amount of hardware for the auxiliary calculator 5 can be reduced by providing the timing determining section 6 in parallel with the main calculator 4 and the auxiliary calculator 5.

The timing determination unit 6 determines the timing when the condition code can be determined according to the value of the operand of the operation instruction, and provides the determination result to the condition code selection circuit 7 as the condition code selection signal 12.The selection circuit 7 determines the timing. The condition code selection signal 12 from the section 6 causes the condition code output 1 of the main arithmetic unit 4 to be
Select either 0 or condition code output 11 of auxiliary operation W5.

Report to command unit 2. As a result, the auxiliary computing unit 5
Since it is only necessary to determine the condition code for a specific operand, the amount of hardware for configuring the auxiliary arithmetic unit 5 can be extremely reduced. Note that if the condition code cannot be determined by the auxiliary processor 5, it is necessary to wait for the condition code output 10 from the main processor 4, and the performance of advance control will deteriorate, but depending on the program, in such a case This rarely occurs, and there is no problem in practice.The operations of the auxiliary arithmetic unit 5 and the timing determination unit 6 will be described below, taking binary floating point subtraction as an example.

As shown in FIG. 3, a binary floating point number consists of a total of 64 bits: a 1-bit sign part, a 7-bit exponent part, and a 56-bit mantissa part. The binary floating point subtraction instruction uses two binary floating point numbers as operands and calculates the difference between them. Depending on whether the result is positive, negative, or 0, a condition code is generated depending on the magnitude relationship of the operands. This is an instruction to set.

In FIG. 1, the operation operand bus 8 is connected to the main operation unit 4. It is assumed that only the main processor 4 receives all 64-bit operands input to each of the auxiliary processor 5 and the timing determiner 6. As shown in Figure 3, the top 1 of each operand
Input only 2 bits. As a result, the amount of hardware required for the auxiliary processor 5 and the timing determining section 6, which have only 24-bit inputs, can be reduced compared to the main processor 4, which has 128-bit inputs.

FIG. 4 shows the timing determination unit 6 for a binary floating point subtraction instruction.
This is a flowchart showing the operation of the operation, which distinguishes between cases in which the magnitude relationship of the operands can be judged only by the upper 12 bits and cases in which it is not possible, and if it can be distinguished, the auxiliary operator 5 determines the condition code, and if it cannot be distinguished, it determines the condition code in the main operation. The condition code is determined by the device 4. In step 101, it is tested that the most significant digit of the mantissa part of both operands is not 0. This is a test to see if a floating point number is normalized or not, and since it is difficult to determine the magnitude relationship of unnormalized numbers by just comparing the sign and exponent part, the auxiliary arithmetic unit 5 This is to exclude them from processing by. In general, denormalized numbers rarely appear in floating-point arithmetic, so performance does not deteriorate because of this. Also, true 0 is considered to be processed by this test, but true 0 is treated as a floating point operand.
It is not a problem because the probability of this occurring is extremely low.
In step 102, the signs are compared, and if the signs are different, the auxiliary arithmetic unit 5 determines the magnitude relationship.

Since the possibility that the operands are 0 has been eliminated in step 101, if they have different signs, the magnitude relationship can be determined by simply checking one sign bit. In step 103, the exponent parts are compared, and if they are different, the auxiliary arithmetic unit 5 determines the magnitude relationship based on the exponent parts.

In step 104, the most significant digits of the mantissa parts are compared, and if they are different, the auxiliary arithmetic unit 5 also determines the magnitude relationship. If the magnitude relationship cannot be determined in step 104,
Since the magnitude relationship cannot be determined without referring to the lower bits of the mantissa, the main arithmetic unit 4 determines the condition code (step 105). This is a case where the upper 12 bits of the two operands are equal, so assuming that the values of the operands are distributed with equal probability, the probability that the condition code needs to be determined by the main processor 4 is as small as 1/4096, which is extremely low. In which case, the auxiliary calculator 5 can determine the condition code.

According to this embodiment, even if the conditional branch instruction immediately follows an arithmetic instruction that requires multiple cycles to obtain an arithmetic result, if the condition code can be determined by the auxiliary arithmetic unit 5, the conditional branch instruction can be executed at high speed. is executable, and can be determined by the auxiliary computing unit 5 in most cases.

Furthermore, although 2N deals with processing for binary floating-point numbers, the present invention can be applied even to binary fixed-point numbers if the condition code can be determined by referencing only the upper bits. The present invention can be applied even to a decimal fixed-point number having a sign in the least significant digit by inputting a part of the upper bits and the least significant sign digit to the auxiliary arithmetic unit.

Further, in the embodiment, the auxiliary arithmetic unit and the timing determination unit are provided in the execution unit, but they may also be provided in the instruction unit by taking advantage of the fact that the amount of hardware is small.

Further, as a modification of the embodiment, it is also possible to use the address calculation arithmetic unit and the conflict resolution advance arithmetic unit provided in the instruction unit as the auxiliary arithmetic unit.

Further, if a failure occurs in the auxiliary arithmetic unit, by always operating according to the condition code determined by the main arithmetic unit, it is possible to continue executing instructions even when the auxiliary arithmetic unit fails.

In addition, as a modification of the embodiment, the condition code output of the auxiliary computing unit is used only to control the instruction following the branch instruction, and the condition code output of the main computing unit is used for the condition code used thereafter. You can.

C. Effects of the Invention] As described above, according to the present invention, it is possible to quickly determine whether or not a conditional branch instruction branches with a small amount of hardware, and without increasing costs. It becomes possible to improve the performance of the information processing device.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a diagram showing the state of the pipeline when a conditional branch instruction is executed, and Figure 3 is an explanatory diagram of an example of binary floating point format. , FIG. 4 is a flowchart showing the operation of the timing determination section in FIG. 1...Memory unit, 2...Instruction unit, 3
...Execution units 3, 4...Main arithmetic unit, 5...Auxiliary arithmetic unit, 6...Time determination section, 7...Condition code selection circuit, 8...Operation operand bus, 9 ...Result data bus, 10...Condition code output from main arithmetic unit, 11...
Condition code output from auxiliary computing unit, 12...Condition code selection signal. Figure 1 Figure 3 Figure 4

Claims (2)

[Claims] (1) When a conditional branch instruction is executed, control of the conditional branch instruction is determined in an information processing device that is equipped with means for controlling whether or not to branch according to the operation of the arithmetic instruction before the conditional branch instruction. A conditional branch control method characterized in that the timing of executing the operation is changed according to the input data of the operation instruction. (2) In addition to the main arithmetic unit that executes an arithmetic instruction, there is an auxiliary arithmetic unit that performs a limited arithmetic operation based on a part of the input data of the arithmetic instruction, and when control of the conditional branch instruction is determined early. 2. The conditional branch control system according to claim 1, wherein whether or not to branch is determined before the arithmetic operation in the main arithmetic unit is completed based on the output of the auxiliary arithmetic unit.