JPH11353305A - Address specification for vector register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the increase of overhead in cost and complexity and the reduction of efficiency due to the execution of individual loading and storing operation. SOLUTION: Data values are transferred between a memory and a register in a register bank 38 by using a continuous block memory accessing instruction. A vector processing instruction specifies a processing operation series to be executed for a series of data values stored in the register. A register address is increased only by a value controlled by a slide value during the period of each operation. Thereby the register address can be increased only by a value '0', '1', '2', or '4' in each repetition. Consequently a mechanism for storing a block memory accessing instruction in continuous memory addresses while supporting a vector operation that data values required for repetition are not adjacent to each other in the memory can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to the field of data processing. More specifically, the present invention relates to a data processing system having a vector data processing register.

[0002]

2. Description of the Related Art Data processing instructions usually include an operation code (opcode) portion and one or more register specification fields. In some systems, registers can be treated as vector registers or scalar registers. Vector registers specify a sequence of registers, each storing its own data value. As the data processing instruction repeats its operation on each data value in the sequence, the data values undergo separate operations. Conversely, a scalar register is a single register that stores a single value that operates independently of other registers.

Data processing instructions that use vector registers have a number of advantages over purely scalar operations. The required instruction bandwidth can be reduced. Since a DSP (Digital Signal Processing) function such as an FIR filter is common, only a single data processing instruction is required to specify multiple similar data processing operations to be performed. It is. In the case of a single dispatch machine, which is desirable due to its simplicity (ie, one instruction is fetched and decoded per cycle), higher performance with multiple functional units executing in parallel on different vector instructions Can be achieved.

FIGS. 16 and 17 of the accompanying drawings respectively show a register bank of a Cray 1 processor and a Digital Equipment Corporation (Digital E).
3 shows a register bank of a multi-titanium processor of the Equipment Corporation. Both of these prior art processors provide a vector register and a scalar register.

[0005] In the case of Cray 1, a separate vector register bank 10 and a scalar register bank 12 are provided. The 16-bit instructions provide individual opcodes corresponding to different combinations of registers specified in the instructions being treated as vectors or scalars. Eight scalar registers and eight vector registers can be addressed by the 3-bit register specification fields R1, R2, R3. In practice, each vector register contains a number of registers, each register capable of storing a different data value, stored in the vector length value stored in the length register 16 and the mask register 18. It can be accessed based on the mask bits.

[0006] The Cray 1 processor is a scatter gather that allows loading and storing to non-adjacent addresses in memory.
er) mechanism is also utilized whereby one or both of the interleaved matrix and complex values stored in main memory can be loaded into the appropriate registers for later manipulation.

[0007] The Cray 1 architecture provides a great deal of flexibility in the operations that can be supported, but has the disadvantage of requiring a great deal of overhead in terms of cost and complexity.

[0008] In a MultiTitan processor, a single register bank 20 is provided, in which each register can operate as a scalar or as part of a vector register. The multi-titanium processor specifies its data processing operations by using 32-bit instructions. Instructions include:
Fields VS2, VS3 specifying whether the register is a vector or a scalar, and the length of the vector (L
en). Providing the vector length in the instruction itself makes it difficult to change the overall vector length without having to resort to self-modifying code. In contrast, if the data on which the processor is operating is one or both of an interleaved matrix and complex data, it should be manipulated by vector instructions by performing separate load and store operations. Each data item must be loaded and stored. This has the disadvantage of being inefficient.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to address at least some of the above system limitations.

[0010]

[Means for Solving the Problems] From one aspect,
The present invention provides a data processing device, comprising: a register bank having a plurality of registers for holding data values to be operated, wherein each of the registers has a register address. And a memory access circuit for performing a memory access between a plurality of contiguous address memory locations in the memory and a plurality of contiguous address registers in the register bank in response to at least one block memory access command And an instruction decoder responsive to at least one vector processing instruction for successively performing data processing operations on operands stored in the predetermined series of registers. During each execution of a data processing operation, the instruction decoder In response to the stride), is incremented by the amount specified register address of the register storing the operands used by the data processing operations by said stride value (increment).

According to the present invention, scatter gather (sca)
A simple implementation of contiguous block memory access instructions can be used without the cost and complexity of the tergather mechanism. The increment (variable between vectors) applied to the register address at each iteration allows the system to proceed through non-adjacent data values and select the appropriate matrix, real or imaginary value to be processed. . In practice, it has been found that limiting the increment between register addresses to a fixed value within the execution of a vector instruction is not a significant constraint. Many important real tasks are consistent with this behavior. In essence, the system can use efficient block memory access instructions to memory, which preserves the vector processing ability to specify a sequence of operations with a single instruction while maintaining uniform data. Are arranged in a simple format.

Although it is possible to provide each register specified in the vector processing operation with its own stride value, in a preferred embodiment, all registers operating as vector registers when executing the vector processing instruction are described above. The stride value applies.

It has been found that this feature simplifies implementation and is not a significant constraint in practice.

Similarly, it is possible to specify a stride value in the vector instruction itself. However, in a preferred embodiment of the present invention, the stride value is set regardless of the vector processing instruction.

[0015] This feature saves bit space in vector instructions without actually imposing any significant restrictions on the processing to be performed. In practice, the stride value usually remains constant for long periods of time, so the bit space saved in the instructions more than compensates for the occasional need to execute certain instructions that change the stride value. I understand.

It has been found to be particularly efficient to use an embodiment in which the stride value specifying the amount of the register address increment for all executed vector processing instructions is stored in a control register.

The register address adder increments the register address by adding a current register address input provided to a first adder input and the quantity input provided to a second adder input. By providing an embodiment included in the implementation, incrementing the register address between vector operations can be conveniently achieved.

Even if the operands are not arranged sequentially in memory in the order in which they are to be used, block memory access instructions can be used and data processing operations can be performed using vector instructions. In providing a possible system, such an embodiment has less cost and complexity overhead.

Although the stride value may directly represent the amount to be incremented, in a preferred embodiment of the present invention the stride value is an encoded representation of the amount.

In practice, the commonly given increment is a subset of all possible increment values, so having the stride value directly represent the quantity signifies the quantity rather than wasting bit space. It can be seen that it is more efficient to use the converted value as the stride value.

In embodiments where the register address is also incremented or controlled based on whether the register address is in a subset of registers in the register bank, sophistication is improved.

Due to this feature, poor operation codes (op
Additional instructions can be encoded by the register number used rather than the code) bits.

The increment applied may be to add a positive or negative number to the register address. However, the most useful increment has been found to be a positive natural power of two.

Viewed from another aspect, the present invention provides a data processing method. The data processing method includes the steps of: holding a data value to be operated in a register bank having a plurality of registers each having a register address; and responding to at least one block memory access command, Performing a memory access between a memory location at a plurality of contiguous addresses and a register at a plurality of contiguous addresses in the register bank; and responsive to at least one vector processing instruction, Successively performing a data processing operation on the operands stored in the data processing operation during each execution of the data processing operation in response to a stride value used in the data processing operation. Register address of the register that stores the operand It is incremented (increment) the amount specified by the stride value.

The present invention will be further described with reference to a preferred embodiment thereof shown in the accompanying drawings. These are only examples.

Section 1 FIG. 1 shows a data processing system including a main processor 24, a floating point co-unit processor 26, a cache memory 28, a main memory 30, and an input / output system 32. The main processor 24, the cache memory 28, the main memory 30, and the input / output system 32 are connected to the main bus 3
4 are linked. Coprocessor bus 36 links main processor 24 to floating point unit coprocessor 26.

The operation will be described. The main processor 24 (also called an ARM core) includes a cache memory 28, a main memory 30, and an input / output system 32.
Executes a stream of data processing instructions that control general types of data processing operations, including the interaction of Coprocessor instructions are embedded in the stream of data processing instructions. Main processor 24 recognizes these coprocessor instructions as being of a type to be executed by the associated coprocessor. In response, main processor 24 sends these coprocessor instructions on coprocessor bus 36. From this coprocessor bus 36, any attached coprocessors receive coprocessor instructions. In this case, the floating-point unit coprocessor 26 accepts and accepts the received coprocessor instruction detected as being addressed to itself and executes it. This detection is performed via a coprocessor number field in a coprocessor instruction.

FIG. 2 is a schematic diagram illustrating the floating point unit coprocessor 26 in more detail. Floating point unit coprocessor 26 includes a register bank 38 comprised of thirty-two 32-bit registers (only a few shown in FIG. 2). These registers contain 32
It can operate individually as single precision registers each storing a bit data value, or together can operate as a pair storing a 64-bit data value. In the floating point unit coprocessor 26, a pipeline type multiply-accumulate unit 40 and a load storage control unit 42 are provided. In appropriate circumstances, the multiply-accumulate unit 40
And the load storage control unit 42 can operate simultaneously. In this case, while the multiply-accumulate unit 40 is performing arithmetic operations (including multiply-accumulate operations and other operations) on the data values in the register bank 38, the load storage control unit 42 The data values not used by the unit 40 are exchanged with the floating-point unit coprocessor 26 via the main processor 24.

In the floating point unit coprocessor 26, the accepted coprocessor instruction is latched in the instruction register 44. In this simplified diagram, the coprocessor instruction consists of three register specification fields R1, R2 and R3 after the operation code (opcode) part.
(In fact, these fields may be split and expanded differently in the overall instruction). These register designation fields R1, R2, and R3 are used to specify the destination for the data processing operation being performed,
They correspond to registers in a register bank 38 serving as a first source (source) and a second source, respectively. The vector control register 46 can initialize and update the length and stride value according to the vector control register instruction. Since the vector length and stride values are globally applied in the floating point unit coprocessor 26, these values can be dynamically changed globally without having to resort to an auto-correct mode.

The register control-instruction dispatch unit 48, load storage control unit 42, and vector control unit 50 can be considered collectively to perform the major part of the instruction decoder role. The register control-command sending unit 48 responds to the operation code and the register specification fields R1, R2, and R3, and first outputs an initial register access (address) signal to the register bank 38. No action code is performed and there is no need to use the vector control unit 50. Such direct access to the initial register values helps to achieve a faster implementation. If a vector register is specified, the vector control unit 50 serves to generate the required sequence of register access signals using a 3-bit incrementer (adder) 52.
The vector control unit 50 responds to the length value and stride value stored in the vector control register 46 when addressing the register bank 38.
A register scoreboard 54 is provided for register locking so that the pipeline type multiply-accumulate unit 40 and the load storage control unit 42 operating at the same time do not cause a data consistency problem. Register control-instruction sending unit 48
May be considered a part of).

The operation code in instruction register 44 specifies the nature of the data processing operation to be performed (eg, whether the instruction is addition, subtraction, multiplication, division, loading, storing, etc.). This does not depend on the nature of the specified register vector or scalar. This further simplifies instruction decoding and multiply accumulate unit 40 settings.
First register specification value R1 and second register specification value R2
Together decode the vector / scalar nature of the operation specified by the operation code. For the three common cases supported by the encoding, S = S
* S (eg, a basic random calculation as created by a C compiler from a block of C code), V = V
opS (eg, to scale the elements of the vector), and V = VopV (eg, FIR filters, matrix operations such as graphic transformations) (note that in this context, “op”
Indicates a general operation, where the syntax is of the form destination = second operand op first operand). For some instructions (for example, compare, compare to zero or absolute value)
There may be no destination register (eg, the output is a condition flag), or there may be few input operands (only one input operand to compare to zero). In these cases, a larger opcode bit space is available to specify options such as vector / scalar properties, and the full range of registers can be made available for each operand (eg, ,
Whatever the register, the comparison may always be completely scalar).

The register control-instruction sending unit 48 and the vector control unit 50, which together play a major part in the role of the instruction decoder, respond to the first register specification field R1 and the second register specification field R2. And the vector of the specified data processing operation
After determining the nature of the scalar, control. If the length value stored in the vector control register 46 indicates a length of 1 (corresponding to a stored value of 0), this may be used as an initial indication of purely scalar operations. it can.

FIG. 3 is a flowchart showing the processing logic used to decode the vector / scalar property from the register specified value in single precision mode. In step 56, a test is made whether the vector length is set as a whole as 1 (length value equals 0). If the vector length is 1, at step 58 all registers are treated as scalars. At step 60, a test is made as to whether the destination register R1 is in the range S0 to S7. If this is the case, the operations are all scalars, in the form S = SopS, as shown in step 62. Step 6
If 0 or "no" is returned, the destination is determined to be a vector, as shown in step 64. If the destination is a vector, the encoding assumes that the second operand is also a vector. Therefore, the two possibilities remaining at this stage are: V = Vop
S and V = VopV. The distinction between these two possibilities is made by a test in step 66 which determines whether the first operand is one of S0 to S7. If this is the case, the operation is V = VopS, otherwise V = VopV. These states are recognized in steps 68 and 70, respectively.

It should be noted that when the vector length is set to 1, all 32 registers of the register bank 38 can be used as scalars. This is because the scalar nature of the operation is recognized at step 58 and it is not necessary to resort to the test of step 60 which limits the range of registers available for the destination. The test of step 60 is useful in recognizing scalar operations when mixed vector and scalar instructions are used. When operating in mixed vector and scalar mode, if the first operand is a scalar, it is S0
It can also be seen that if the first operand is a vector, it can be any of S8 to S31. When the first operand is a vector, doubling the number of available registers in the register bank is because the number of registers needed to hold the sequence of data values when using vector operations It is generally an adaptation to the growing.

It will be appreciated that the usual operation that one wants to perform is a graphics transformation. In the general case, the transformation to be performed can be represented by a 4 * 4 matrix.
The reuse of operands in such calculations means that it is desirable to store matrix values in registers that can be manipulated as vectors. Similarly, input pixel values are typically stored in four registers, which should also be able to be manipulated as vectors to aid reuse. The output of a matrix operation is typically a scalar (accumulated separate vector row multiplications) stored in four registers. If it is desired to double input and output values, 24 (= 16 + 4 + 4) vector registers and 8 (= 4 + 4) scalar registers are required.

FIG. 4 is a flow chart corresponding to the flow chart of FIG. 3, but in this case the double precision mode is shown. As described earlier, in double precision mode, register bank 38
Register slots operate in pairs and store 16 64-bit data values in logical registers D0 through D15. In this case, the encoding of the vector / scalar nature of the register is modified from that of FIG. 3 and the tests of steps 60 and 66 are respectively performed at steps 72 and 74 of "Is the destination one of D0 to D3?" And "Is the first operand one of D0 to D3?"

By encoding the vector / scalar properties of the registers in the register specification field as described above,
Although instruction bit space is saved significantly, certain difficulties arise for non-commutative operations such as addition and division. Given a register configuration V = VopS, the lack of symmetry between the first and second operands for non-commutative operations extends the instruction set to non-commutative operations. SUB, RSU representing two different operand options for
By including pairs of opcodes such as B, DIV, and RDIV, this can be overcome without the additional instruction of exchanging register values.

FIG. 5 shows the wrapping of the vectors in a subset of the register bank 38. In particular, in the single-precision mode, the register banks have addresses S0 to S7, S8.
To S15, S16 to S23, and S24 to S3
It is divided into four ranges of registers. These ranges are disjoint and adjacent. As shown in FIG. 2, the wrapping function for these subsets, including eight registers, can be provided by using a three-bit incrementer 52 in the vector control unit 50. In this way, the incrementer wraps back when crossing a subset boundary. This simple implementation is facilitated by aligning the subset on 8-word boundaries in the register address space.

Returning to FIG. 5, a number of vector operations are shown to aid in understanding register wrapping. The first vector operation is a start register S2, a vector length 4 (indicated by length value 3 in vector control register 46), and a stride value 0 in vector control register 46 (indicated by stride value 0 in vector control register 46).
Specify stride 1. Therefore, when executing a decoded instruction to refer to register S2 as a vector with these global vector control parameter sets, registers S2, S3, S4, and S5
The instruction is executed four times using each of the data values in. Since this vector does not cross the subset boundary,
No vector wrapping.

In the second example, the start register is S14
, The length is S14, and the stride is 1.
As a result, the instruction is executed six times, starting from register S14. The next register to be used is S15. When the register advances by the stride again, the register S1
Instead of using 6, it is wrapped in a register S8.
Next, by executing the instruction three more times, S14,
The entire sequence of S15, S8, S9, S10, and S11 is completed.

The last example in FIG. 5 shows the start register of S25, the length of 8, and the stride of 2. The first register used is S25, followed by S27, S29 and S31 according to the stride value 2.
Following use of register S31, the next register value wraps back to the start of the subset, passes through register S24 because it is stride 2, and uses register S25 to perform the operation. Incrementer 52
May take the form of a 3-bit adder that adds a stride to the current value as it moves between vector registers. Therefore, the stride can be adjusted by giving the adder different stride values.

FIG. 6 shows the register bank 3 in the double precision mode.
8 shows a wrapping of 8. In this mode, a subset of registers include D0 to D3, D4 to D7, and D8 to D1.
1, and D12 to D15. The minimum value input to the adder serving as the incrementer 52 in the double precision mode is 2. This corresponds to double precision stride 1. Double precision stride 2 requires input 4 to the adder. In the first example of FIG.
0, length 4, stride 1. As a result, D
A vector register sequence of 0, D1, D2 and D3 is obtained. There is no wrapping in this example because it does not cross the subset boundary. In the second example, the start register is D15, the length is 2, and the stride is 2. as a result,
A vector register series of D15 and D13 is obtained.

Referring to FIG. 2, it can be seen that load storage control unit 42 has a 5-bit incrementer at its output, so that multiple load / store operations are not subject to register wrapping applied to vector operations. This allows a single multiple load / store instruction to access as many consecutive registers as it requires.

An example of an operation that makes good use of this wrapping configuration is a FIR filter divided into four signal value units and four taps. The syntaxes R8-R11opR16-R19 are vector operations R8opR16, R9opR17, R10opR.
18, and R11opR19, FIR
The filter operation can be performed as follows.

Eight taps are loaded into R8-R15 and eight signal values are loaded into R16-R23.

Put R8-R11opR16-R19, and put the result in R24-R27. R9-R12opR1
6-R19, and place the results in R24-R27. R
10-R13opR16-R19 and the result as R24
-Put in R27. R11-R14opR16-R1
9, and place the result in R24-R27.

Reload new taps in R8-R11.

The results are accumulated in R12-R15opR16-R19, and the result is accumulated in R24-R27. R13-R8op
R16-R19 and the result are accumulated in R24-R27 (R15-> R8 wrap). R14-R9opR16
-R19, and accumulate the result in R24-R27 (R
15-> R8 wrap). R15-R10opR16-R
19, and accumulate the result in R24-R27 (R15
-> R8 wrap).

Reload new taps on R12-R15.

When there are no more taps, new data is reloaded into R16-R19.

Put R12-R15opR20-R23, and put the result in R28-R31.

Put R13-R8opR20-R23 and the result into R28-R31 (R15-> R8 wrap). R14-R9opR20-R23, and put the result in R28-R31 (R15-> R8 wrap). R
15-R10opR20-R23 and the result as R28
-Put in R31 (R15-> R8 wrap).

The rest is the same as above

As can be seen from the above, the loading can be done in parallel (ie, do double buffering) since the loading is done to different registers from multiple accumulations.

FIG. 7A is a schematic diagram showing how the main processor 24 examines coprocessor instructions. The main processor identifies the instruction as a coprocessor instruction by using a bit combination of the (splittable) field 76 in the instruction. Within the standard ARM processor instruction set, the coprocessor instructions include a coprocessor number field 78. The coprocessor (s) associated with the main processor use the coprocessor number field 78 to
Identify whether specific coprocessor instructions are targeting them. Different types of coprocessors, such as a DSP coprocessor (eg, a Piccolo coprocessor from ARM) or a floating point unit coprocessor, can be assigned different coprocessor numbers, and therefore have the same coprocessor bus 36. Can be addressed separately within a single system. The coprocessor instruction also includes an operation code (opcode) used by the coprocessor, and three 5-bit fields respectively specifying a destination, a first operand, and a second operand from the coprocessor registers. . For some instructions, such as coprocessor loads or stores, the main processor at least partially decodes the coprocessor instructions so that the coprocessor and the main processor together can complete a desired data processing operation. The main processor may respond to the data type encoded in the coprocessor number as part of the instruction decoding it does in such situations.

FIG. 7B illustrates how a coprocessor that supports both double and single precision operations interprets received coprocessor instructions. Such a coprocessor is assigned two adjacent coprocessor numbers. The coprocessor uses the three most significant bits of the coprocessor number to identify if it is the target coprocessor. In this way, the least significant bit of the coprocessor number is redundant for the purpose of identifying the target coprocessor, and is instead used to determine the data type to be used in executing that coprocessor instruction. Can be specified. In this example, the data type corresponds to whether the data size is single precision or double precision.

In the double precision mode, the number of registers is effectively 32.
From 16 to 16. It is possible to reduce the register field size accordingly, but in that case the decoding of the register to be used can be obtained directly from the complete field itself at a known location in the coprocessor instruction. No, depending on the decoding of other parts of the coprocessor instruction. This has the disadvantage of being complex and possibly slowing the operation of the coprocessor. Decoding the data type using the least significant bits of the coprocessor number means that the operation code can be completely independent of the data type, which also makes its decoding easier and faster. Is faster.

FIG. 7C illustrates how a coprocessor that supports only a single data type, which is a subset of the data types supported by the coprocessor of FIG. 7B, interprets coprocessor instructions. In this case, all coprocessor numbers are used to determine whether the instruction should be accepted. Thus, if the coprocessor instruction is of an unsupported data type, it corresponds to a different coprocessor number and will not be accepted. At this time, main processor 24 can rely on undefined instruction exception handling to emulate operations for unsupported data types.

FIG. 8 shows a data processing system serving as a main processor and communicating via a coprocessor bus 82 with a coprocessor 84 that supports both single and double precision data types. A coprocessor instruction including a coprocessor number is issued from the ARM core 80 onto the coprocessor bus 82 as it appears in the instruction stream. The coprocessor 84 then compares the coprocessor number with its own number and returns an accept signal to the ARM core 80 if they match. If the accept signal is not received, the ARM core recognizes that the instruction exception is undefined,
The exception handling code stored in the memory system 86 is referred to.

FIG. 9 shows the system of FIG. 8 modified by replacing coprocessor 84 with a coprocessor 88 that supports only single precision operation. In this case, coprocessor 88 recognizes only a single coprocessor number. Thus, double-precision coprocessor instructions in the original instruction stream that are executed by coprocessor 84 of FIG. 8 are not accepted by single-precision coprocessor 88. Thus, if it is desired to execute the same code, undefined exception handling code in memory system 86 may include a double precision emulation routine.

The need to emulate double-precision instructions slows down the execution of these instructions, but the single-precision coprocessor 88
If smaller, less expensive, and double-precision instructions are sufficiently rare, the net benefit is gained.

FIG. 10 shows an instruction latch circuit in a coprocessor 84 that supports both single and double precision instructions and has two adjacent coprocessor numbers. In this case, the three most significant bits CP # [3: 1] of the desired coprocessor number in the coprocessor instruction are compared with those assigned to that coprocessor 84. In this example,
If the coprocessor 84 has coprocessor numbers 10 and 11, by comparing the most significant three bits CP # [3: 1] of the coprocessor number with the binary 101,
This comparison can be made. If a match occurs, an accept signal is returned to ARM core 80 and the coprocessor instruction is latched for execution.

FIG. 11 shows an equivalent circuit in the single precision coprocessor 88 of FIG. In this case, only a single coprocessor number is recognized and single precision operation is used by default. The comparison made in determining whether to accept and latch the coprocessor instruction is made by comparing the entire four bits of coprocessor number CP # [3: 0] and the single embedded coprocessor number 2
This is performed between the decimal point 1010 and the decimal point 1010.

FIG. 12 is a flowchart showing how the undefined exception handling routine of the embodiment of FIG. 9 can be triggered to move the double precision emulation code. This is performed by detecting whether the instruction causing the undefined instruction exception is a coprocessor instruction whose coprocessor number is binary 1011 (step 90). If "yes", this is intended for a double-precision instruction, so that emulation can be performed in step 92 and then the flow returns to the main program. If not trapped in step 90, other exception types may be detected and processed in subsequent steps.

FIG. 13 shows each of the 32 registers in the register bank 220.
9 illustrates the use of a format register FPREG 200 to store information identifying the type of data stored in a bit register, ie, each data slot. As described above, each data slot may operate individually as a single precision register for storing a 32-bit data value (one data word), or may be paired with another data slot to provide a 64-bit data value. A double precision register for storing a value (two data words) can be provided. According to a preferred embodiment of the present invention, FPREG register 200 is configured to identify whether any particular data slot has single-precision or double-precision data stored therein. You.

As shown in FIG. 13, the register bank 22
Thirty-two data slots out of zero are arranged to provide 16 pairs of data slots. If a first data slot stores a single precision data value therein, the other data slot of the pair is configured to store only the single precision data value and the double precision data value is stored. It is not linked to any other data slot to store the value. Thus, any particular data slot pair is configured to store two single precision data values, or one double precision data value. This information is associated with each data slot pair in register bank 220
It can be identified by bit information. Thus, in the preferred embodiment, FPREG register 200 is configured to store 16 bits of information to identify the type of data stored in each data slot pair of register bank 220. Therefore, register FPREG200
May be embodied as a 16-bit register or F
For consistency with other registers in the PU coprocessor 26, it can be embodied as a 32-bit register with 16 spare bits of information.

FIG. 15 shows six pairs of data slots in register bank 220. According to the preferred embodiment, this 6
A pair of data slots can be used to store six double precision data values or twelve single precision data values. An example of data that can be stored in a data slot is shown in FIG. DH represents the 32 most significant bits of the double precision data value, DL represents the 32 least significant bits of the double precision data value, and S represents a single precision data value.

The corresponding entry in FPREG register 200 according to the preferred embodiment of the present invention is also shown in FIG. According to a preferred embodiment, the FPR is used to indicate that the corresponding data slot pair contains a double precision data value.
The value "1" is stored in the EG register 200, and the value "0" to indicate that at least one of the corresponding data slot pairs contains a single precision data value, or that both data slots have not been initialized. Is used. Therefore, if both data slots are uninitialized, one data slot is uninitialized and the other data slot in the pair contains single-precision data values, or both data pairs If the slot contains a single precision data value, a logic "0" value is stored in the corresponding bit of FPREG register 200.

As previously described, the FPU of the preferred embodiment
Processor 26 may be used to process single-precision or double-precision data values, and the coprocessor instructions issued by main processor 24 may be any particular instruction is a single-precision instruction or a double-precision instruction. (See FIG. 7B and accompanying description). When an instruction is accepted from the coprocessor, the instruction is sent to the register control-instruction sending unit 48 where it is decoded and executed. If the instruction is a load instruction, register control-instruction dispatch logic 48 instructs load storage control unit 42 to retrieve the identified data from memory and store the data in the designated data slot of register bank 220. . At this stage, the coprocessor knows whether a single precision data value or a double precision data value is being searched, and the load storage control unit 42 operates accordingly. Therefore,
The load storage control unit 42 sends a 32-bit single precision data value or a 64-bit double precision data value to the register bank input logic 230 via the path 225 for storage in the register bank 220.

The data is not only loaded into the register bank 220 by the load storage control unit 42, but is also provided to the format register FRPEG200.
As a result, it is possible to add information bits necessary to indicate whether each data slot pair receiving data intends to store single-precision data or double-precision data. In the preferred embodiment, after this data is stored in the format register FRPEG200, the data is loaded into the register bank,
This information is available to register bank input logic 230.

In the preferred embodiment, since the internal format of register bank 220 is the same as the external format, single precision data values in
It is stored as a 2-bit data value, and the double-precision data value is stored as a 64-bit data value. The register bank input logic 230 is a format register FRPEG2
00, the register bank input logic 23
A value of 0 indicates whether the data received is single precision or double precision. Thus, in such an embodiment, register bank input logic 230 would
It simply arranges the data received on path 225 for storage in the twenty appropriate data slot (s). However, in an alternative embodiment, if the internal representation in the register bank differs from the external format, register bank input logic 230 is configured to perform the necessary conversion. For example, a number is usually 1. ab
c. . . Is multiplied by a radix to obtain a power of a certain exponent. For efficiency, the usual single and double precision representations do not use data bits to represent the one to the left of the decimal point, and one is assumed to be implied. If, for any reason, the internal representation used in register bank 220 must specify 1, then register bank input logic 230 performs the necessary conversion of the data. In such an embodiment, the data slot is typically slightly larger than 32 bits to accommodate the additional data generated by register bank input logic 230.

In addition to loading data values into register bank 220, load storage control unit 42 may load data into one or more system registers of coprocessor 26, such as user status control register FPSCR 210. In the preferred embodiment, FPSCR register 2
10 includes configuration bits and exception status bits that can be accessed by the user. This is explained in more detail in the description of the architecture of the floating point unit at the end of the description of the preferred embodiment.

When the register control-instruction sending unit 48 issues a storage instruction representing a specific data slot in the register bank 220 whose contents are to be stored in the memory, the load storage control unit 42 is instructed accordingly, and The appropriate data word is called from the register bank 220 to the load storage control unit 42 via the register bank output logic 240. Register bank output logic 240 accesses the contents of FPREG register 200 to determine whether the data being read is single precision data or double precision data. Next, register bank output logic 240
Applies an appropriate data transformation to reverse the data transformation applied by register bank input logic 230,
The data is transferred to the load storage control unit 42 via a path 235.
Give to.

According to a preferred embodiment of the present invention, if the store instruction is a double-precision instruction, coprocessor 26 operates in a second mode of operation in which the instruction is applied to a double-precision data value. be able to. Since a double precision data value contains an even number of data words, any store instruction issued in the second mode of operation will normally
Its contents represent an even number of data slots to be stored in memory. However, according to a preferred embodiment of the present invention, if an odd number of data slots are specified, the load storage control unit 42 will read the contents of the FPREG register 200 and first store those contents in memory. rear,
It is configured to store an even number of identified data slots from the register bank 220. Usually, the data slot to be transferred is a base address representing a specific data slot in the register bank, followed by a number indicating the number of data slots to be stored (that is, the number of data words) counted from the data slot. Is represented by

Here, for example, when the storage instruction gives the first data slot of register bank 220 as the base address and designates 33 data slots, the contents of all 32 data slots are thereby specified. Is stored in the memory, but the content of the FPREG register 200 is also stored in the memory since the specified number of data slots is odd.

This approach uses a single instruction to store both the contents of the register bank and the contents of the FPREG register 200, which represents the type of data stored in the various data slots of the register bank 220. be able to. This eliminates the need to issue separate instructions to explicitly store the contents of FPREG register 200, and does not significantly affect processing speed during storage to memory or loading from memory processes.

In another embodiment of the present invention, taking this approach one step further, a single instruction can be used to add additional system registers, such as FPSCR register 210, if needed. It can be stored in memory. Therefore, considering the example of the register bank 220 having 32 data slots, as described above, when 33 data slots are represented by the storage instruction, the 32 data slots of the register bank 220 are stored. In addition to the contents of the slot, an FPREG register 200 is stored in memory. However, if a different odd number, for example, 35, which is greater than the number of data slots in the register bank, is represented by the load storage control unit 42,
In addition to the contents of the data slots in the FPREG register 200 and the register bank 220, the FPSCR register 210
Can also be interpreted as the need to store it in memory. The coprocessor may include additional system registers, for example, an exception register that indicates an exception that occurred during processing of the instruction by the coprocessor. If a different odd number, for example, 37 is represented in the storage instruction, the load storage control unit 42 stores this in the FPSCR register 21.
In addition to the contents of the 0, FPREG register 200, and register bank 220, the contents of one or more exception registers can be interpreted as a need to additionally store.

This technique is particularly useful because the code that initiates the store or load instruction does not know the contents of the register bank, and temporarily stores the contents of the register bank for later retrieval in the register bank. Only stored in memory. If the code knows the contents of the register bank, the contents of FPREG register 200 may not need to be stored in memory either. Representative examples of codes that may not know the contents of the register bank are context switch codes and procedural call entries and exit routines.

In such a case, the contents of the FPREG register 200 in addition to the contents of the register bank can be efficiently stored in the memory. In fact, as mentioned above,
Certain other system registers can also be stored as needed.

When a subsequent load instruction is received, a similar process is used. Therefore, when receiving a double-precision load instruction designating an odd number of data slots, the load storage control unit 42 loads the contents of the FPREG register 200 into the FPREG register 200, and then indicates the number of slots indicated by the load instruction. It is configured to store the contents of a system register followed by an even number of data words in a designated data slot of the register bank 220. So, given the example described earlier,
If the number of data slots specified by the load instruction is 33, the content of the FPREG register 200 is set to FPRE.
After being loaded into the G register 200, the contents of the 32 data slots are loaded. Similarly, when the number of data slots specified in the load instruction is 35, in addition to the above contents, the contents of the FPSCR
Loaded into SCR register. Finally, if the specified number of data slots is 37, in addition to the above contents, the contents of the exception registers are loaded into those exception registers. As will be apparent to those skilled in the art, the particular operation associated with the particular odd number is completely arbitrary and can be varied as desired.

FIG. 14 is a flowchart illustrating the operation of the register control and instruction dispatch unit 48 in accordance with a preferred embodiment of the present invention when executing store and load instructions.
Initially, at step 300, the number of data words (which in the preferred embodiment is the same as the number of data slots) is read from the instruction, along with the first register number represented in the instruction, the base register. Next, step 31
At 0, it is determined whether the instruction is a double precision instruction. At this stage, the coprocessor can obtain this information because it indicates whether the instruction is a double-precision instruction or a single-precision instruction, as described above.

If the instruction is a double precision instruction, the process proceeds to step 320. At step 320, it is determined whether the number of words specified in the instruction is odd. For this embodiment, assuming that the above technique is not used to selectively transfer various system registers in addition to the FPREG register 200, if the number of words is odd, then the FPREG register Indicating that the contents of 200 should be transferred, the contents of FPREG register 200 are transferred by load storage control unit 42 in step 325 accordingly. Next, at step 327, the number of words is reduced by one. The process proceeds to step 330. If step 320 determines that the number of words is even, the process proceeds directly to step 3
Go to 30.

At step 330, it is determined whether the number of words is greater than zero. If the number of words is not greater than zero, the instruction is considered completed and the process exits at step 340. However, if the number of words is greater than zero, the process proceeds to step 332. At step 332, the double precision data value (ie, the contents of the two data slots) is transferred to or from the first specified register number. Next, at step 334, the number of words is reduced by two, and at step 336, the register number is increased by one.
As explained earlier, for a double precision instruction, the register is actually composed of two data slots, so increasing the register count by one increases the data slot number by two.
It is equivalent to increasing only.

Next, the procedure returns to step 330. At step 330, it is determined whether the number of words is still greater than zero. If the number of words is greater than zero, the process repeats. When the number of words reaches zero, the process proceeds to step 3.
Exit at 40. If it is determined in step 310 that the instruction is not a double precision instruction, the process proceeds to step 350. At step 350, it is again determined whether the number of words is greater than zero. If the number of words is greater than zero, the process proceeds to step 352. At step 352, the single precision data value is transferred to or from the first register number represented in the instruction. Next, at step 354, the number of words is reduced by one, and at step 356, the register number count is increased by one to point to the next data slot. Next, the process returns to step 350. At step 350, it is determined whether the number of words is still greater than zero.
If the number of words is greater than zero, the process repeats,
When the number of words equals zero, the process exits at step 360.

The above approach provides considerable flexibility when executing codes that do not know the register bank contents, for example, context switch codes or procedure call entries and exit sequences. In these cases, it is desirable that the operating system does not know the contents of the registers and does not need to treat the registers differently depending on their contents. With the above approach, these code routines can be written with a single store or load instruction specifying an odd number of data words. If the coprocessor requires the use of register contents information, the coprocessor stores in memory the odd number of data words in the instruction and the format information needed to represent the contents of the data in the register bank. Interpret the need to store or load from memory. This flexibility eliminates the need for special operating system software to support coprocessors that require register content information.

This technique also eliminates the need to load and store register content information in separate operations in the code. Since the option to load and store register content information is built into the instruction, no additional memory access is required. This shortens the code length and possibly saves time.

The architecture of the floating-point unit incorporating the above method will be described below.

1. INTRODUCTION VFPv1 is a floating point system (FPS: FPS) designed to be implemented as a coprocessor for use with an ARM processor module.
Floating point system). An implementation of this architecture may incorporate features in hardware or software, or the implementation may use software to achieve full functionality or
EEE 754 compatibility may be provided. This specification is
It seeks to achieve full IEEE 754 compliance using a combination of hardware and software support.

The two coprocessor numbers are used by VFPv1. 10 is used for operations on single precision operands, while 11 is used for operations on double precision operands. Conversion between single-precision data and double-precision data is performed by two conversion instructions operating in the source operand coprocessor space.

The features of the VFPv1 architecture include:

Full compatibility with IEEE 754 on hardware with support code. -32 single precision registers, each addressable as a source operand or destination register. • Sixteen double-precision registers, each addressable as a source operand or destination register. (Double precision registers overlap with physical single precision registers). Vector mode significantly increases the floating point code density and the simultaneous operation of load and store operations. Four banks of eight circular single precision registers or four banks of four circular double precision registers to enhance dsp (digital signal processing) and graphics operations. Denormal processing options are either IEEE 754 compatible (intended to be supported from the floating point emulation package) or fast flash-to-zero (flash-t)
o-zero) Select function. A complete pipeline chain multiply-accumulate configuration,
Produces results that are compatible with IEEE754. Conversion of floating point to integer for C, C ++, and Java with the FFTOSIZ instruction.
The implementer may choose to implement VFPv1 entirely in hardware or to use a combination of hardware and support code. VFPv1 may be implemented entirely in software.

[0092] 2. Terminology The following terms are used in this specification.

Automatic Exception—An exception condition that always bounces to the support code regardless of the value of each exception enable bit. If there is a choice of which exceptions are automatic, it is an implementation option. Section 1-6. See exception handling. Bounce-an exception reported to the operating system that is handled entirely by support code without invoking a user trap handler or otherwise interrupting the normal flow of user code. CDP-Coprocessor Data Processing
ssor DataProcessing). In the case of FPS, the CDP operation is an arithmetic operation, not a load or store operation.

ConvertToUnsignedIn
teger (Fm) (conversion to unsigned integer)-Fm
Is converted to an unsigned 32-bit integer value. The result depends on the rounding mode for final rounding and handling of floating point values outside the range of 32-bit unsigned integers.
If the floating point input value is too large for a negative or 32-bit unsigned integer, an INVALID exception is possible. ConvertToSignedInteger (F
m) (Conversion to signed integer)-Convert the contents of Fm to a signed 32-bit integer value. The result is the final round and 32
Handling of floating point values outside the range of signed integer bits is governed by the rounding mode. If the floating point input value is too large for a 32-bit signed integer, an INVALID exception is possible. ConvertUnsignedIntToSingl
e / Double (Rd) (unsigned integer converted to single / multiple)-ARM interpreted as a 32-bit unsigned integer
Convert register contents (Rd) to single or double precision floating point values. If the destination precision is single precision, an INEXACT exception is possible in the conversion operation. ConvertSignedIntToSingle /
Double (Rd) (Convert signed integers to single / multiple)
Convert the ARM register contents (Rd) interpreted as a 32-bit signed integer to a single or double precision floating point value. If the destination precision is single precision, an INEXACT exception is possible in the conversion operation.

Denormalized value-range (-2 ^Emin <x <2
^Emin ). In the IEEE 754 format for single and double precision operands, the denormalized value or denormal has a zero exponent and the leading significand bit is zero instead of one. According to the IEEE 754-1985 specification, the generation and manipulation of denormalized operands must be performed with the same precision as for normal operands. Disabled Exception-FP
An exception for which the corresponding exception enable bit in the SCR is set to 0 is "disabled" (disabled).
Called d). For these exceptions, IEEE 754
The specifications are to return the correct result. Operations that raise an exception condition bounce to the support code and produce the results specified in IEEE 754. No exception is reported to the user exception handler. Enabled exceptions-Exceptions in which each exception enable bit is set to one. When this exception occurs, a trap to the user handler is performed. Operations that generate exceptional conditions will bounce to the support code, producing the results specified in IEEE 754. Next, the exception is reported to the user exception handler.

Exponent-A floating point component that typically represents an integer power of two in determining the value of a represented number. Sometimes the exponent is called a signed or unbiased exponent. Fraction-the field of the significand to the right of its implied binary point. Flash-to-zero mode-in this mode, all values in the range after rounding ( ^-2Emin <x < ^2Emin ) are treated as zero rather than being converted to denormalized values . High (Fn / Fm) —The upper 32 bits [63:32] of the double precision represented in memory.

IEEE 754-1985-American Institute of Electrical and Electronics Engineers, "IEEE Standard for Binary Floating-Point Arithmetic"
("IEEE Standard for Binar
yFloating-Point Arithmeti
c ", ANSI / IEEE Std 754-1985,
The Institute of Electric
al and Electronics Engineering
ers, Inc. New York, 10017). This standard, often referred to as the IEEE 754 standard, defines data types, correct operations, exception types and handling, and error bounds for floating point systems. Most processors are built according to hardware or a combination of hardware and software. IEEE7 used to represent infinity-∞
54 special formats. The exponent is maximum for accuracy and the significand is all zeros. Input exception-an exception condition in which one or more of the operands for a given operation is not supported by the hardware. The operation bounces to the support code for completion of the operation.

Intermediate result--an internal format used to store the result of a calculation before rounding. This format may have a larger exponent field and a significant field than the destination format. Low (Fn / Fm)-the lower 32 bits of the double precision [31: 0] represented in memory. MCR-"Move to Coprocesso
r from ARMRegister "(move from ARM register to coprocessor). In the case of FPS, this includes instructions to transfer data or control registers between ARM and FPS registers. Single MCR class Instructions may be used to transfer only 32 bits of information.

MRC-"Move to ARM"
Register from Coprocessor
r "(moved from coprocessor to ARM register) FP
For S, this includes instructions to transfer data or control registers between the FPS and ARM registers. A single MCR class instruction may be used to transfer only 32 bits of information. NaN-Nota number (not a number). The presence of a symbol encoded in floating point format. There are two types of NaN, signaling and non-signaling, i.e. stationary. Signaling NaNs cause invalid operand exceptions when used as operands. A stationary NaN propagates through almost all arithmetic operations without signaling exceptions. The format for NaN has an all-one exponent field with a nonzero significand. To represent the signaling NaN, the most significant bit of the decimal part is 0, whereas the static NaN has a bit set to 1.

Reserved-
A field in a control register or instruction format is "reserved" if the field is to be defined by an implementation. If the content of the field is not 0, it is unpredictable (UNPRE
DIC TABLE) results. These fields are reserved for use in future extensions of the architecture. That is, it is implementation specific. All reserved bits not used by the implementation must be written as zero and read as zero.

Rounding Mode--The IEEE 754 specification requires that all calculations be performed as if to infinite precision. That is, in multiplying two single precision values, the significand must be accurately calculated up to twice the number of bits of the significand. Significant rounding is often required to represent this value with destination precision. IEEE7
In the 54 standard, four rounding modes are specified. That is, rounding to the nearest (RN: round t
o nearest), rounding to zero, ie (RZ:
round tozero, plus rounding to infinity (RP: round to plus infinite)
y), and rounding to minus infinity (RM: run
d tominus infinity). The first rounding is done by rounding at the middle point, in which case the least significant bit of the significand is rounded up to "just" to zero. The second rounding effectively truncates any bits to the right of the significand. Thus, the second round always truncates and is used by the C, C ++, and Java languages for integer conversion. The latter two modes are used in interval arithmetic.

Significand--A component of a binary floating point number consisting of an explicit or implied leading bit to the left of the implied binary point and a fraction field to the right.

Support Code-Software that must be used to complement the hardware to achieve compliance with the IEEE 754 standard. The support code is designed to have two components. One component is a library of routines. Routines perform operations that are beyond the scope of the hardware, such as transcendental operations, and supported functions, such as inputs that can cause division or exceptions on unsupported inputs. Another component is a set of exception handlers. The exception handler handles exception conditions to comply with IEEE 754. The support code must perform the implemented functions in order to emulate the proper handling of unsupported data types or data representations (eg, denormalized or decimal data types). If care is taken to restore the user's state at the exit of the routine, the routine may be written to use the FSP for intermediate calculations.

Trap-Exception condition with each exception enable bit set in FPSCR. The user's trap handler is executed. UNDEFINED-Indicates an instruction that generates an undefined instruction trap. See the ARM Architecture Reference Manual for more information about ARM exceptions. UNPREDICTABLE-The result of an unreliable instruction or control register field value. Unpredictable instructions or results must not represent a security hole and should not halt any part of the processor or system.

Unsupported data (Unsuppo)
rtedData)-a particular data value that is not processed by hardware but is bound to a support code for completion. These data are infinite, NaN,
It may include non-normal values and zero. Implementations are free to choose which of these values are fully or partially supported in hardware, or require the help of supporting code to complete the operation. If the corresponding exception enable bit for an exception is set, any exception resulting from processing unsupported data is trapped in user code.

3. Register file

3.1 INTRODUCTION This architecture provides 32 single precision registers and 16 double precision registers. All of these can be individually addressed as source or destination operands in a well-defined 5-bit register index.

The 32 single precision registers overlap the 16 double precision registers. That is, the writing of the double-precision data to D5 is the overwriting of the contents of S10 and S11. A notice of register usage conflicts between the use of registers as single-precision data storage and the use of registers as half of double-precision data storage in overlapping implementations has been found by compiler or assembly language programmers. Work. No hardware is provided to limit the use of registers to one precision. If this is violated, the result is unpredictable (UNP
REDICTABLE).

VFPv1 is a scalar mode that creates a result using one, two, or three operand registers and writes the result to a destination register.
Or, provide access to these registers in vector mode where the specified operand references a group of registers. VFPv1 supports vector operations for up to eight elements in a single instruction for single precision operands and up to four elements for double precision operands.

Table 1 LEN bit coded LEN vector length coding 000 Scalar 001 Vector length 2 010 Vector length 3 011 Vector length 4 100 Vector length 5 101 Vector length 6 110 Vector length 7 111 Vector length 8

The vector mode is enabled by writing a non-zero value to the LEN field. LEN
If the field contains a 0, the FPS operates in scalar mode and the register field contains 32 individual single precision registers or 16
Are interpreted as addressing double precision registers. If the LEN field is non-zero, the FPS operates in vector mode and the register field is interpreted as addressing a vector of registers. L
See Table 1 for EN field encoding.

The means for mixing the scalar operation and the vector operation without changing the LEN field can be used by specifying the destination register. If the destination register is in the first bank of registers (S0-S7 or D0-D3), a scalar operation may be specified while in vector mode. See Section 1 for more information.

3.2 Use of Single-precision Register If the LEN field of the FPSCR is 0, S
Thirty-two single precision registers numbered 0 to S31 are available. Any register can be used as a source register or a destination register.

[0114]

[Outside 1] Illustration 1 Single precision register map

The register map of the single precision (coprocessor 10) can be drawn as shown in Illustration 1.

If the LEN field of the FPSCR is greater than 0, the register file behaves as four banks of eight circular registers, as shown in Illustration 2. The first bank of vector registers V0 to V7 overlap with the scalar registers S0 to S7 and are addressed as scalars or vectors depending on the register selected for each operand. See Section 1, 3.4 Using Registers for more information.

[0117]

[Outside 2] Illustration 2 Single precision register circulation

For example, when LEN of FPSCR is set to 3, reference vector V10 is stored in register S
10, S11, S12, and S13 are included in the vector operation. Similarly, V22 is S22, S23,
S16 and S17 are included in the operation. When the register file is accessed in vector mode, the register following V7 in order is V0. Similarly, V8 follows V15, V16 follows V23, and V24 becomes V31.
followed by.

3.3 Use of Double Precision Register When the LEN field of the FPSCR is 0, 1 is used.
Six double-precision scalar registers are available.

[0120]

[Outside 3] Illustration 3 Double precision register map

[0121] Any of the registers can be used as a source register or a destination register.
The register map can be drawn as shown in Illustration 3.

When the LEN field of the FPSCR is greater than 0, as shown in Illustration 4, four banks of four circular registers have four scalar registers and one
Six vector registers are available. The first bank of vector registers V0 to V3 overlap with the scalar registers D0 to D3. Each operand is addressed as a scalar or vector depending on the register selected. For more information, see Section 1,
See 3.4 Using registers.

[0123]

[Outside 4] Illustration 4 Circulation of double precision registers

As in the single precision example in section 1, double precision registers are circulated in the four banks.

3.4 Register Use These operations between scalars and vectors are supported.
Ported. (OP _TwoIs a floating-point coprocessor
The two operand operations supported by
Any may be used. OP_ThreeIs a three operand operator
Any of the options. )

In the following description, the "first bank" of the register file is the registers S0-S7 for single-precision operation, and D0 for double-precision operation.
-D3.

ScalarD = OP ₂ Scalar
A or ScalarD = ScalarA OP ₃
ScalarB or ScalarD = Scala
rA * ScalarB + ScalarD • VectorD = OP ₂ ScalarA or
VectorD = ScalarA OP ₃ Vector
B or VectorD = ScalarA * Vec
torB + VectorD • VectorD = OP ₂ VectorA or
VectorD = VectorA OP ₃ Vector
B or VectorD = VectorA * Vec
torB + VectorD

3.4.1 Scalar Operation Under two conditions, the FPS operates in scalar mode.

1? LEN field of FPSCR is 0
It is. The destination and source registers may be any of scalar registers 0 through 31 for single precision operation, or any of scalar registers 0 through 15 for double precision operation. The operation is performed only on registers explicitly specified in the instruction.

2? The destination register is in the first bank of the register file. The source scalar can be any of the other registers. This mode allows a mix of scalar and vector operations without having to change the LPS field of the FPSCR.

3.4.2 Operation Involving Scalar and Vector Source with Vector Destination To operate in this mode, the LEN field of the FPSCR is greater than zero and the destination register is located in the first bank of the register file. Not in The scalar source register may be any register in the first bank of the register file, but may be any of the remaining registers for VectorB. If the source scalar register is a member of VectorB, or if less than LEN elements VectorD is Vector
orB, the behavior is unpredictable (UNP
REDICTABLE). VectorD and Ve
ctorB must be the same vector or completely different for all members. See section 1 summary table.

3.4.3 Operations Including Only Vector Operations To operate in this mode, the LEN field of the FPSCR is greater than zero and the destination vector register is not in the first bank of the register file.
The individual elements of VectorA are combined with the corresponding elements of VectorB and written to VectorD. For VectorA, any registers not in the first bank of the register file can be used,
All vectors are available for ctorB.
As in the second case, if either of the source vectors and the destination vector overlap with fewer elements than LEN, the behavior is unpredictable (UNPRED
ICTABLE). They must be the same or completely different on all members. See section 1 summary table.

Note that for FMAC family of operations, the destination register or vector is always an accumulation register or vector.

3.4.4 Operation Summary Table The following table shows the register usage options for single and double precision instructions with two and three operands. "Any" means the availability of all registers of that precision for the specified operand.

Table 2 Single-precision three-operand registers used LEN destination destination second first operation type field source source register register register 0 optional optional optional S = SopS or S = S * S + S non-zero 0-7 optional optional S = SopS or S = S * S + S Non-08-31 0-7 Arbitrary V = SopV or V = S * V + V Non-08-31 8-31 Arbitrary V = VopV or V = V * V + V

Table 3 Single-precision two-operand registers used LEN destination source operation type field register register 0 any optional S = opS non-zero 0-7 optional S = opS non-zero 8-31 0-7 V = opS non-zero 8 −31 8−31 V = opV

Table 4 Use of Double-precision 3 Operand Registers LEN Destine First Second Operation Type Field Source Source Register Register Register 0 Optional Optional Optional S = SopS or S = S * S + S Non-zero 0-3 Optional Optional S = SopS or S = S * S + S Non0 4-15 0-3 Any V = SopV or V = S * V + V Non0 4-15 4-15 Any V = VopV or V = V * V + V

Table 5 Double-precision 2-operand register use LEN destination source operation type field register register 0 any optional S = opS non-zero 0-3 optional S = opS non-zero 4-15 0-3 V = opS non-zero 4 -15 4-15 V = opV

4. Instruction Set FPS instructions can be divided into three categories. -Transfer operations between MCR and MRC-ARM and FPS-Load and store operations between LDC and STC-FPS and memory-CDP-Data processing operations

4.1 Instruction Concurrency The intent of the FPS architecture specification is two levels:
That is, there is concurrency in parallel load / store operations by the pipeline-like functional unit and the CDP function. Supporting load and store operations that do not have register dependencies on these operations to execute in parallel with the operations currently being processed provides significant performance advantages.

4.2 Instruction Serialization The FPS completes all currently executing instructions,
The FPS specifies a single instruction that causes the ARM to wait busy until each exception status is known. If an exception has occurred, the serializing instruction is suspended and exception handling begins in the ARM. The serialization instructions in the FPS are as follows. • FMOVEX-Read or write to floating point system registers

[0142] Any reading or writing to the floating point system registers is halted until the current instruction is completed. FMO for system ID register
VX (FPSID) triggers an exception caused by a preceding floating point instruction. Reading / modifying / writing (using FMOVEX) on the User Status-Control Register (FPSCR) can be used to clear the exception status bit (FPSCR
[4: 0]).

4.3 Conversion Including Integer Data Conversion between floating point data and integer data is a two-step process of the FPS composed of a data transfer instruction including integer data and a CDP instruction for conversion. . If you try any arithmetic operation on integer data in the FPS register in integer format, the result is unpredictable (U
NPREDICTABLE) and any such operation should be avoided.

4.3.1 Converting Integer Data to Floating-Point Data in FPS Register Using the FMOVS instruction of the MCR, either ARM
Integer data can be loaded from registers to floating point single precision registers. At this time, by the operation of the integer-floating family, the integer data in the FPS register can be converted into a single-precision or double-precision floating-point value and can be written to the destination FPS register. If an integer value is no longer needed,
The destination register may be a source register. The integer can be a signed or unsigned 32-bit number.

4.3.2 Converting Floating-Point Data in FPS Registers to Integer Data The instructions in the floating-integer family allow the values in the single or double precision registers of the FPS to be signed or unsigned 32 bits. It can be converted to a bit integer format. The resulting integer is placed in a single-precision destination register. Integer data can be stored in the ARM register using the MRC FMOVS instruction.

4.4 Register File Addressing Instructions that operate in single precision space (S = 0) use the five bits available in the instruction field for operand access. The upper 4 bits are Fn, F
m or in the operand field denoted Fd. The least significant bits of the address are in N, M, or D, respectively.

An instruction operating in a double-precision space (S = 1) uses only the upper 4 bits of the operand address.
These four bits are in the Fn, Fm, and Fd fields. The N, M, and D bits must contain 0 when the corresponding operand field contains an operand address.

4.5 MCR (Move from ARM Register to Coprocessor) MCR operation involves the transfer or use of data in the ARM register by the FPS. This includes
Moving data from an ARM register in single-precision format or moving data from a pair of ARM registers to a FPS register in double-precision format; loading signed or unsigned integer values from an ARM register to a single-precision FPS register; And loading the contents of the ARM register into the control register.

The format for the MCR instruction is shown in FIG.

[Outside 5] Figure 5 MCR instruction format

Table 6 Definition of MCR bit field Bit definition field Opcode 3-bit operation code (see Table 7) Rd ARM source register encoding S Operation operand size 0-Single precision operand 1-Double precision operand N Single precision operation: Least Significant Bit of Destination Register Double precision operation: Must be set to 0, otherwise operation is undefined (UNDEFINED) System register moved Reserved Fn Single precision operation: Destination register address upper 4 bits Double precision operation: Destination register address System register move: 0000-FPID (coprocessor ID number) 0001-FPSCR (user status Status - Control Register) 0100-fpreg (Register File Content Register) Other register coding is reserved, may differ in a variety of implementations. R Reserved bit

Table 7 Definition of MCR Operation Code (opcode) Field Opcode Field Name Operation 000 FMOVS Fn = Rd (32 bits, coprocessor 10) 000 FMOVELD Low (Fn) = Rd (double precision lower 32 bits, coprocessor 11) 001 FMVHD High (Fn) = Rd (double precision upper 32 bits, coprocessor 11) 010- Reserved 110 111 FMOVEX system register = Rd (space of coprocessor 10)

Note: Only 32-bit data operations are supported by the FMOVE [S, HD, LD] instruction.

Only the data in the ARM register or single precision register is moved by the FMOVS operation. To transfer double precision operands from the two ARM registers, the FMOVED and FMOVED instructions move the lower half and the upper half, respectively.

4.6 MRC (from coprocessor to ARM
Move to Register / Compare Floating Register) MRC operation involves transferring data from the FPS register to the ARM register. This involves converting the result of converting a single-precision value or floating-point value to an integer into one A
Moving to the RM register, or moving the double-precision FPS register to two ARM registers, and modifying the status bits of the CPSR with the results of a previous floating point compare operation. The format of the MRC instruction is shown in FIG.

[0155]

[Outside 6] Illustration 6 MRC instruction format

Table 8 Definition of MRC bit field Bit definition field Opcode 3-bit FPS operation code (see Table 9) Rd ARM destination * register encoding S Operation operand size 0-single precision operand 1-double precision operand N single Precision operation: Least significant bit of destination register Double precision operation: Must be set to 0, otherwise operation is undefined (UNDEFINED) System register moved Reserved M Reserved Fn Single precision operation: Destination register address upper 4 Bit Double-precision operation: Destination register address System register move: 0000-FPID (coprocessor ID number) 0001-FPSCR (User Status-Control Register) 0100-FPREG (Register File Content Register) Other register encodings are reserved and may differ in various implementations. Fm Reserved R Reserved

* In the case of the FMOVEX FPSCR instruction, R
When R15 (1111) is contained in the d field,
The upper 4 bits of the CPSR are updated with the resulting condition code.

Table 9 Definition of MRC Operation Code Field Opcode Field Name Operation 000 FMOVS Rd = Fn (32 bits, coprocessor 10) 000 FMOVED Rd = Low (Fn). The lower 32 bits of Dn are transferred. (Lower 32 bits of double precision, coprocessor 11) 001 FMOVHD Rd = High (Fn). The upper 32 bits of Dn are transferred. (Double precision upper 32 bits, coprocessor 11) 010- Reserved 110 111 FMOVX Rd = system register

Note: See the note for the MCR FMOV instruction.

4.7 LDC / STC (Load / Store F
(PS register) The LDC and STC operations perform data transfer between the FPS and the memory. Floating point data can be transferred with either precision in single data transfer or multiple data transfer. At this time, the ARM address register is updated or left unchanged. Both full descending stacks and empty ascending stacks are supported, along with multiple operand access to data structures in moving multiple operations. See Table 11 for a description of the various options for LDC and STC. LDC and ST
The format of the C instruction is shown in FIG.

[0161]

[Outside 7] Illustration 7 LDC / STC instruction format

Table 10 Definition of LDC / STC Bit Field Bit Definition Field P Pre / Post Indexing (0 = Post, 1 = Pre) U Up / Down Bit (0 = Down, 1 = Up) D Single Precision Operation: Source / Destination register least significant bit double precision operation: Must be set to 0 W write back bit (0 = non-write back, 1 = write back) L direction bit (0 = store, 1 = load) Rn ARM Base register encoding Fd Single-precision operation: upper 4 bits of source / destination register address Double-precision operation: source / destination register address S Operation operand size 0-single-precision operand 1-double-precision operand offset / Unsigned 8-bit offset or number of single precision registers to be transferred for FLDM (IA / DB) and FSTM (IA / DB) (twice the count of double precision registers). The maximum number of words in a transfer is 16, which is 16 single-precision values or 8 double-precision values.

4.7.1 General Notes on Load and Store Operations Multiple register load and store operations are performed through the register file without wrapping across the four or eight register boundaries used by vector operations. It is done linearly. Attempting to load past the end of the register file is unpredictable (UNPREDICTABLE)
It is.

If the offset for a dual load or multiple store contains an odd register count of 17 or less, the implementation may write another 32-bit data item, or write another 32-bit data item. May be read, but there is no need to do so. Additional data items can be used to identify the contents of the registers as they are loaded and stored. This is useful in implementations where the register file format differs from the IEEE 754 format for its precision, and each register has the type information needed to identify it in memory. If the offset is odd and the number is greater than the number of single-precision registers, this may be used to trigger a context switch on the register and all system registers

Table 11 Load and Store Addressing Mode Option P W Offset / Addressing Mode Name Transfer Number Type 0 Transfer: Multiple Load / Store 0 0 Transfer Without Write Back FLDM <cond><S / D> Multiple load / register number Rn, <register storage list> FSTM <cond><S / D> Rn, <register list> Load / store multiple registers from the execution start address of Rn, and do not modify Rn. The number of registers can be 1 to 16 for single precision and 1 to 8 for double precision. The offset field contains a 32-bit transfer number. This mode can be used to load transformation matrices for graphic operations and points for transformations. Example: FLDMEQS r12, {f8-f11} is r1
Load four single precision data from two addresses into four floating point registers. s8, s9, s10, and r12 do not change. FSTMEQD r4, @f
0｝ stores one double-precision data from d0 at the address of r4. r4 does not change. Type 1 transfer: Load / store multiplex using Rn post index and write back. 0 1 FLDM <cond> IA <S / D> to be transferred Multiple load / number of registers Rn! , <Register memory list> FSTM <cond> IA <S / D> Rn! , <Register list> Load / store multiple registers from the start address of Rn and write back the next address after the last transfer to Rn. The offset field is a 32-bit transfer number. Write back to Rn is Offset * 4. The maximum number of words transferred in the multiple load is 16. The U bit must be set to one. this is,
To store in an empty ascending stack or to load from a full descending stack, or to store transformed points and advance the pointer to the next point, and to load and store multiplexed data in a filter operation for,
used. Example: FLDMEQIAS r13! , ｛F12-f1
5 # loads four floating-point registers s12, s13, s14, and s15 from the address of r13, and updates r13 with an address indicating the next data in the series. Type 2 transfer: Load / store one register using pre-index or Rn without write-back. 10 Offset FLD <cond><S / D> Offset [Rn, # + /-offset], Load / Fd storage FST <cond><S / D> [Rn, # + /-offset], Fd Rn Load / store a single register using address pre-increment and no write back. The offset value is Offset * 4, and addition (U = 1)
Alternatively, an address is generated by subtracting (U = 0) from Rn. This is useful for operand access to structures and is a typical method used to access memory for floating point data. Example: FSTEQD f4, [r8, # + 8] is 32 (8
* 4) The double-precision data is stored in d4 from the address of r8 which is offset by an amount. r8 does not change. Type 3 transfer: Load / store multiple registers using pre-index and write-back. 11 1 FLDM <cond> DB <S / D> to be transferred Number of predecreme registers Rn! , <Register with multiplex list> Load / FSTM <cond> DB <S / D> Store Rn! , <Register list> Pre-decrement the address of Rn and load / store the multiplex register into Rn with the new destination address. The offset field contains a 32-bit transfer number. The write-back value is Offset * 4 subtracted from Rn. This mode is used to store in a full descending stack or to load from a free ascending stack.
used. Example: FSTMEQDBS r9! , {F27-f29}
Is the last entry address in r9 and s2
7. Store the three single precision data from 7, s28 and s29 in the empty descending stack. r9 is updated with the point to the new last entry.

4.7.2 Summary of LDC / STC Operation Table 12 shows the LDC / STC operation codes P,
5 tabulates allowable combinations for the W and U bits, and the function of the offset field for each valid operation.

[0167] Table 12 LDC / STC Operation Summary P W U Offset operation field 0 0 0 UNDEFINED 0 0 1 Register FLDM / FSTM Count 0 1 0 UNDEFINED 0 1 1 register FLDMIA / FSTMIA Count 1 0 0 Offset FLD / FST 1 0 1 Offset FLD / FST 110 Register FLMDDB / FSTMDB Count 1 1 1 UNDEFINED

4.8 CDP (Coprocessor Data Processing) CDP instructions include all data processing operations that involve operands from a floating point register file and that result in being written back to the register file. Of particular interest is FMAC (multiplication-
(Cumulative chain) operation, an operation of multiplying two of the operands and adding a third operand. This operation differs from the fused multiply-accumulate operation in that an IEEE rounding operation is performed on the product, followed by a third operand addition. By using the FMAC operation, the speed of the multiply-accumulate operation can be increased as compared with the operation of performing the multiplication separately after adding the Java code by using the FMAC operation.

The two instructions in the CDP group are useful in converting a floating point value in an FPS register to its integer value. FFTOUI [S / D] uses the current rounding mode in the FPSCR to convert single or double precision content to unsigned integers in the FPS register. FF
TOUI [S / D] performs conversion into a signed integer.
FFTOUIZ [S / D] and FFTOSIZ [S / D]
Performs the same function, but ignores the FPSCR rounding mode for the transform and truncates the fractional bits. FFTOS
The function of IZ [S / D] requires C, C ++, and Java in the conversion from floating point to integer. The FFTOSIZ [S / D] instruction provides this function and does not require adjustment of the rounding mode bits from FPSCR to RZ for conversion. The cycle count for the conversion is only the cycle count of the FFTOSIZ [S / D] operation, saving four to six cycles.

The compare operation uses the CDPCMP instruction followed by the MRC FMOVEX FPSCR instruction to execute the ARM CP with the resulting FPS flag bit.
This is done by loading the SR flag bit.
If one of the comparison operands is NaN, INV
A comparison operation is provided with and without potential ALID exceptions. If one of the comparison operands is NaN, FCMPE and FCMP
While E0 is signaling an exception, FCMP and FCMP0
Does not convey INVALID. FCMP0 and FCMP
E0 compares the operand in the Fm field with 0, and sets the FPS flag accordingly. ARM flags N, Z, C, and V are defined as follows after the FMOVEX FPSCR operation.

Less than N Z equal to or greater than C or disorder V disorder

The format of the CDP instruction is shown in FIG.

[0173]

[Outside 8] Illustration 8 CDP instruction format

Table 13 Definition of CDP bit field Bit definition field Opcode 4-bit FPS operation code (see Table 14) D Single precision operation: Least significant bit of destination register Double precision operation: Must be set to 0 Fn Single precision Operation: Extend upper 4 bits of source A register or upper 4 bits of opcode Double precision operation: Extend source A register address or upper 4 bits of opcode Fd Single precision operation: Upper 4 bits of destination register Double precision operation: Destination register Address S Operation operand size 0-Single precision operand 1-Double precision operand N Single precision operation: Source A register Lower bits opcode least significant bit extended Double precision operation: must be set to 0 opcode least significant bit extended M Single precision operation: Source B register least significant bit Double precision operation: must be set to 0 Fm single precision Operation: Upper 4 bits of source B register address Double precision operation: Source B register address

4.8.1 Operation Code (Opcode) Table 14 lists the main operation codes for the CDP instruction. All mnemonics are [OPERAT
ION] [COND] [S / D].

Table 14 CDP Operation Code Specification Opcode Operation Operation Field Name 0000 FMAC Fd = Fn * Fm + Fd 0001 FNMAC Fd = − (Fn * Fm + Fd) 0010 FMSC Fd = Fn * Fm-Fd 0011 FNMSC Fd = − (Fn * Fm -Fd) 0100 FMUL Fd = Fn * Fm 0101 FNMUL Fd =-(Fn * Fm) 0110 FSUB Fd = Fn-Fm 0111 FNSUB Fd =-(Fn-Fm) 1000 FADD Fd = Fn + Fm 100+ Fn / Fm 1101 FRDIV Fd = Fm / Fn 1110 FMD Fd = Fn% Fm (Fd = decimal part after Fn / Fm) 1111 Extend Two operands Using the Fn register for specifying operations on Bae configuration (see Table 15)

4.8.2 Extended Operations Table 15 lists the extended operations available using extended values in the operation code field. Except for the serialization instruction and the FLSCB instruction, all instructions have the format [OPERATION] [COND] [S / D]. The instruction encoding for the extended operation is formed similar to the index into the register file for the Fn operand. That is, ｛Fn
[3: 0], N}.

Table 15 CDP Extension Operation Fn | N Name Operation 000000 FCPY Fd = Fm 00001 FABS Fd = abs (Fm) 00010 FNEG Fd = − (Fm) 00011 FSQRT Fd = sqrt (Fm) 00100− Reserved 001111F1000g FC : = Fd @ Fm 01001 FCMPE * Flags: = Fd @ Fm Exception Report Available 01010 FCMP0 * Flags: = Fd @ 0 01011 FCMPE0 * Flags: = Fd @ 0 Exception Report Available 01100 Reserved -01110 D111FVT FCV Fm (single-precision register encoding) converted from <cond> S * to double-precision (coprocessor 10) 01111 FCVTS Fd (single-precision register encoding) = double-precision <cond> Fm converted from D * to single-precision (double-precision register encoding) (coprocessor 11) 10000 FUITO * Fd = unsigned integer Convert to double (Fm) 10001 FSITO * Fd = Convert signed integer to single / multiple (Fm) 10010-Reserved 10111 11000 FFTOUI * Fd = Convert to unsigned integer (Fm) {Current RMODE} 11001 FFTOUIZ * Fd = Conversion to unsigned integer (Fm) {RZ mode} 11010 FFTOSI * Fd = Conversion to signed integer (Fm) {Current RMODE} 11011 FFTOSIZ * Fd = Conversion to signed integer (Fm) RZ mode II 11100- Reserved 11111

* Non-vectorizable operations. L
The EN field is ignored and the scalar operation is performed on the specified register.

5. System register

5.1 System ID Register (FPSI
D) The FPSID contains an identification value defined in the FPS architecture and implementation. This word can be used to determine the model, feature set, and revision of the FPS, as well as the mask set number. FPSID is read-only, FPSID
Writing to is ignored. See Illustration 9 for the layout of the FPSID register.

[0182]

[Outside 9] Fig. 9 Encoding of FPSID register

5.2 User Status Control Register (FPSCR) The FPSCR register contains user accessible configuration bits and exception status bits. Configuration options include exception enable bits, rounding control, vector stride and length, processing and results of subnormal operands,
And use of debug mode. This register contains the user and operating system code
To query the status of completed operations. It must be saved and restored during a context switch. Bits 31-28 contain the flag values from the most recent compare instruction. Bits 31 through 28 contain F
It can be accessed using a PSCR read. The FPSCR is shown in Illustration 10.

[0184]

[Outside 10] Illustration 10 User status-control register (FP
SCR)

5.2.1 Status Comparison and Processing Control Bytes Bits 31 through 28 contain the results of the most recent comparison operation and a number of useful bits to specify the operation response of the FPS in special situations. Contains control bits. The format of the status comparison and processing control bytes is shown in FIG.

[0186]

[Outside 11] Illustration 11 FPSCR status comparison and processing control bytes

Table 16 FPSCR Status Comparison and Processing Control Byte Field Definition Register Name Function Bit 31 N Comparison Result was Smaller 30 Z Comparison Result was Equal 29 C Comparison Result was Above or Disordered 28 V Comparison Result 27:25 Reserved 24 FZ Flash to zero 0: IEEE754 underflow processing (default) 1: Flow very small results to zero Results are smaller than the normal range for destination accuracy If so, a zero is written to the destination. The UNDERFLOW exception is not used.

5.2.2 System Control Byte The system control byte controls the rounding mode, vector stride, and vector length fields. The bits are designated as shown in illustration 12.
The VFPv1 architecture incorporates a register file stride mechanism for use with vector operations. STRIDE bit is 00
, The next register selected by the vector operation is the register immediately following the previous register in the register file. The regular register file wrapping mechanism is not affected by the stride value. A STRIDE of 11 increments all of the input registers and the output registers by two.

For example, FMULEQS F8, F16, F24 perform the following non-vector operations. FMULEQS F8, F16, F24 FMULEQS F10, F18, F26 FMULEQS F12, F20, F28 FMULEQS F14, F22, F30 The operand for the multiplication in the register file effectively "strides" not two registers but two registers.

[0190]

[Outside 12] Illustration 12 FPSCR system control byte

Table 17 FPSCR System Control Byte Field Definition Register Name Function Bits 23:12 RMODE Rounding Mode Setting 00: RN (Round to nearest, default) 01: RP (Round to positive infinity) 10: RM (rounding toward negative infinity) 11: RZ (rounding toward zero) 21:20 STRIDE Vector register access 00: 1 (default) 01: Reserved 10: Reserved 11: 2 19 Reserved (R) 18:16 LEN vector length. Specifies the length for vector operations. (Not all encodings are available in each implementation.) 000: 1 (default) 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8

5.2.3 Exception Enable Byte The exception enable byte occupies bits 15: 8 and contains the enable for exception trap. The bits are designated as shown in illustration 13. The exception enable bit sets the IEEE for handling floating point exception conditions.
Meets the requirements of the 754 specification. If the bit is set, the exception is enabled. If an exception condition occurs for the current instruction, the FPS signals the user's visible trap to the operating system. If the bit is cleared, no exception is enabled. In the case of exceptional conditions, the FPS does not communicate the user's visible trap to the operating system, but produces mathematically valid results. The default for the exception enable bit is disabled. See the IEEE 754 standard for more information on exception handling.

In some implementations, even when an exception is disabled, it causes a bounce to the support code to handle the exception condition outside of the hardware's function. This is generally not visible to user code.

[0194]

[Outside 13] Illustration 13 FPSCR exception enable

Table 18 FPSCR Exception Enable Byte Field Register Name Function Bits 15:13 Reserved 12 IX Inexact Enable Bit 0: Disabled (Default) 1: Enabled 11 UFE Underflow Enable Bit 0 : Disabled (default) 1: Enabled 10 OFE overflow enable bit 0: Disabled (default) 1: Enabled 9 DZE Division enable bit by zero 0: Disabled (default) 1: Enabled 8 IOE Invalid Operand Enable Bit 0: Disabled (default) 1: Enabled

5.2.4 Exception status byte is FP
Occupies bits 7: 0 of the SCR and contains the exception status flag bit. There are five exception status flag bits, one for each floating point exception. These bits are "sticky". Once set by the detected exception, these bits are set to FPSCR or FSER.
Must be cleared by an FMVX write command to IALCL. The bits are specified as shown in illustration 14. For an enabled exception,
The corresponding exception status bit is not set automatically. It is the task of the support code to set the appropriate exception status bits as needed. Some exceptions can be automatic. That is, when an exception condition is detected, the FPS bounces to a subsequent floating point instruction, regardless of how the exception enable bit is set. This allows more related exception handling required by the IEEE 754 standard to be performed in software rather than hardware. One example is FZ
This is an underflow condition in which a bit is set to 0. In this case, the correct result can be a denormalized number determined by the exponent of the result and the rounding mode. The FPS allows the author to select a response that includes an option to bounce,
A correct result can be created by using the support code, and this value can be written to the destination register. If the underflow exception enable bit is set, the user's trap handler is called after the support code has completed the operation. This code can change the state of the FPS and return, ie, terminate the process.

[0197]

[Outside 14] Illustration 14 FPSCR exception status byte

Table 19 FPSCR Exception Status Byte Field Definition Register Name Function Bits 7: 5 Reserved 4 IXC Incorrect Exception Detection 3 UFC Underflow Exception Detection 2 OFC Overflow Exception Detection 1 DZC Exception Detect by Zero 0 IOC Invalid Operation Exception detection

5.3 Register File Content Register (FPREG) The register file content register is a privileged register.
The debugger can use the information contained therein to suitably present the contents of the registers as interpreted by the currently executing program. 16 for FPREG
Bits, one bit for each double precision register in the register file. When a bit is set, the physical register pair represented by that bit should be displayed as a double precision register. If the bit is clear, the physical register is initialized. That is, a physical register contains one or two single precision data values.

[0200]

[Outside 15] Illustration 15 Encoding of FPREG register

Table 20 FPREG bit field definitions FPREG bit bit clear bit set C0 D0 valid S1 and S0 valid, ie not initialized C1 D1 valid S3 and S2 valid, ie not initialized C2 D2 valid S5 and S4 valid C3 D3 valid S7 and S6 valid, ie not initialized C4 D4 valid S9 and S8 valid, ie not initialized C5 D5 valid S11 and S10 valid, ie uninitialized C6 D6 valid S13 and S12 Is valid, ie not initialized C7 D7 valid S15 and S14 are valid, ie not initialized C8 D8 valid S17 and S16 are valid, ie not initialized C9 D9 valid S19 and S18 are valid, ie not initialized C10 D10 valid S21 and S20 are valid, ie not initialized C11 D11 valid S23 and S22 are valid, ie not initialized C12 D12 valid S25 and S24 are valid, ie not initialized C13 D13 valid S27 and S26 are valid, ie not initialized C14 D14 valid S29 and S28 are valid, ie not initialized C15 D15 valid S31 and S30 are valid, ie not initialized

6. Exception Handling The FPS operates in one of two modes, debug mode and normal mode. If the DM bit is set in the FPSCR, the FPS operates in the debug mode. In this mode, the FPS executes one instruction at a time, and the ARM waits until the execution status of the instruction is known. This makes the register file and memory more accurate for the flow of instructions, but results in much longer execution times.
The FPS accepts new instructions from the ARM, if resources allow, and signals an exception when it detects an exception condition. Exception reporting to the ARM is always correct for floating point instruction streams. However, this does not apply to load or store operations that are executed in parallel with the vector operation following the vector operation. In this case, the contents of the register file for the load operation or the memory for the storage operation may not be accurate.

6.1 Support Code The implementation of the FPS can be chosen to comply with IEEE 754 with a combination of hardware and software support. For unsupported data types and automatic exceptions, the support code is IEEE754
, Returns the result to the destination register when applicable, and returns to the user's code without calling the user's trap handler or otherwise modifying the user's code flow. It appears to the user that only the hardware should have been responsible for processing the floating-point code. Handling these features by bouncing to the support code significantly increases the time required to execute or process the features, but these situations usually occur when user code,
Minimal for embedded applications and well-written numerical applications.

The support code is designed to have two components. That is, a set of routine libraries and exception handlers. The library of routines performs operations beyond the hardware, such as transcendental operations, and supported functions, such as division by unsupported inputs or inputs that can cause exceptions. The set of exception handlers is IEEE
Handle the exception trap to conform to 754. Unsupported data types or data representations (for example,
In order to emulate the appropriate processing (non-normal values), the support code needs to perform the implemented function. If care is taken to restore the user's state at the exit of the routine, the routine may be written to use the FPS for intermediate calculations.

6.2 Exception Reporting and Handling The next floating point instruction issued after an exception condition is detected, reports a normal mode exception to the ARM. ARM
The state of the processor, FPS register file, and memory may not be accurate to the offending instruction at the time the exception was obtained. Sufficient information is available to the support code to perform the correct emulation of the instruction and handle any exceptions caused by the instruction.

In some implementations,
By using the support code, infinity, Na
Some or all operations may be processed with IEEE 754 special data including N, non-normal data, and zero. An implementation that does so will refer to these data as unsupported, bounce to the support code in a way that is generally invisible to user code, and return with the result specified in IEEE 754 in the destination register. Any exceptions caused by the operation follow the IEEE 754 rules for exceptions. This may include trapping in user code if the corresponding exception enable bit is set.

The IEEE 754 standard defines a response to exception conditions for both cases of enabled and disabled exceptions in the FPSCR. VFPv1
The architecture does not specify the boundaries between hardware and software used to correctly follow the IEEE 754 specification.

6.2.1 Unsupported Operations and Formats The FPS does not support operations on, or conversion to or from decimal data. These operations are based on IEEE7
Required by the H.54 standard and must be provided by a support code. Any attempt to utilize decimal data requires a library routine for the desired function. FPS does not have a decimal data type. And FPS cannot be used to trap instructions that use decimal data.

6.2.2 Use of FMOVX When FPS Is Disabled or Exceptional The FMOVX instruction executed in SUPERVISOR or UNDEFINED mode requires that the FPS be in an exception state or (implemented). When the station is disabled (if the station supports the disable option), without causing the ARM to signal an exception,
Read and write PSCR or FP
Reading of SID or FPREG can be performed.

Returning to the embodiment described with reference to FIG. 2, the incrementer 52 generates a register address for addressing the register bank 38. Register bank 3
The register address applied to 8 is stored in register address latch 400 of FIG. During each vector operation, this register address is fed back to 3-bit adder 402, where it is added to the quantity selected by multiplexer 404. Multiplexer 40
4 selects one of the values 0, 1, 2, 4. The multiplexer 404 is switched by the multiplexer controller 406, and the multiplexer controller 406
Responding to the stride value stored in 08 and the data size and register number in the instruction 410 being executed. The initial register value from instruction 410 is loaded into adder 402 via multiplexer 403.

If the register number in the instruction 410 indicates that the register should be treated as a scalar, then the value 0 is selected as the increment regardless of the other parameters. If the data size indicates single precision, the stride value (0 or 1) selects increment 1 or 2. If the data size indicates double precision, the stride value selects increment 2 or 4.

FIGS. 19A to 19D show a vector complex multiplication of length 2 using a stride value of 2 to take into account the interleaving of the real and imaginary parts of the complex number in the memory address space. By using a block load operation, two complex numbers representing the first operand A are stored in registers s12 to s15.
Is loaded. A second block load operation loads two complex numbers for the second operand into registers s20 through s23. The first instruction shown in FIG. 19A uses a stride value of 2 to move between registers that hold the required values (also in the following instructions), thereby providing a second instruction for A1 * B1 and A2 * B2. Calculates the dot product of two imaginary numbers. The second instruction shown in FIG. 19B computes the first two of the four cross products for A1 * B1 and A2 * B2. The third instruction shown in FIG. 19C computes two real dot products for A1 * B1 and A2 * B2, and subtracts from each the respective imaginary dot products previously calculated. The last instruction shown in FIG. 19D computes the respective outer product of the remaining two for A1 * B1 and A2 * B2. The result stored in s29 to s31 is a result in which the real part and the imaginary part of the two complex numbers are arranged adjacent to each other.

Having described certain embodiments of the invention,
It will be apparent that the invention is not limited thereto and that many modifications and additions can be made within the scope of the invention. For example, without departing from the scope of the invention,
The features of the dependent claims can be combined in various ways with the features of the independent claims.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a data processing system.

FIG. 2 shows a floating point unit that supports both scalar registers and vector registers.

FIG. 3 is a flow chart showing how to determine whether a given register is a vector register or a scalar register for single precision operation.

FIG. 4 is a flow chart showing how to determine whether a given register is a vector register or a scalar register for double precision operation.

FIG. 5 illustrates the division of register banks into subsets and wrapping within each subset during single precision operation.

FIG. 6 illustrates the division of register banks into subsets and the wrapping within each subset during double precision operation.

FIG. 7 shows how coprocessor instructions look from the coprocessor, where A shows how the coprocessor instructions look from the main coprocessor, and B shows how the coprocessor instructions appear in single precision ( FIG. 4C shows how a single-precision coprocessor looks like from a single-precision coprocessor, and C shows how a coprocessor instruction looks from a single-precision coprocessor.

FIG. 8 is a diagram showing a main coprocessor that controls single-precision and double-precision coprocessors.

FIG. 9 is a diagram illustrating a main coprocessor that controls a single-precision coprocessor.

FIG. 10 is a diagram showing a circuit in a single-precision and double-precision coprocessor that determines whether an accept signal should be returned to a main coprocessor for a received coprocessor instruction.

FIG. 11 is a diagram showing a circuit in a single-precision coprocessor that determines whether to return an accept signal to a main coprocessor for a received coprocessor instruction.

FIG. 12 is a diagram showing exception processing of an undefined instruction in the main coprocessor.

FIG. 13 is a block diagram illustrating components of a coprocessor according to a preferred embodiment of the present invention.

FIG. 14 is a flowchart illustrating the operation of the register control and instruction dispatch logic according to a preferred embodiment of the present invention.

FIG. 15 illustrates an example of the contents of a floating point register according to a preferred embodiment of the present invention.

FIG. 16 is a diagram showing a register bank in a Cray 1 processor.

FIG. 17 illustrates a register bank in a MultiTitan processor.

FIG. 18 shows the register address incrementing circuit portion of FIG. 2 in more detail.

FIG. 19 illustrates a vector processing operation in the form of a complex multiplication using a stride value of 2, where A is the result of the first instruction and B is the result of the second instruction. C is a diagram showing a result of the third instruction, and D is a diagram showing a result of the fourth instruction.

[Explanation of symbols]

 22 Data Processing System 30 Main Memory 38 Register Bank 48 Register Control-Instruction Sending Unit 50 Vector Control Unit 52 Incrementer 402 3-Bit Adder 406 Multiplexer Controller 408 Control Register 410 Instruction

Claims (12)

[Claims] 1. A data processing device, comprising: a register bank having a plurality of registers for holding data values to be operated, wherein each of the registers has a register address; A register bank; and a memory for performing memory access between a plurality of consecutive address memory locations in the memory and a plurality of consecutive address registers in the register bank in response to at least one block memory access command. An access circuit; and an instruction decoder for performing a plurality of subsequent data processing operations on operands stored in the predetermined sequence of the registers in response to at least one vector processing instruction. And during each execution of the data processing operation, the instruction decoder strikes. In response to the id value, only increments (increments) the amount specified by the data processing operation register addresses the stride value of the register for storing the operands used by the data processing apparatus. 2. The data processing apparatus according to claim 1, wherein the stride value is applied to all registers operating as vector registers when the vector processing instruction is executed. 3. The data processing apparatus according to claim 1, wherein said stride value is set irrespective of said vector instruction processing. 4. The data processing device according to claim 3, wherein said stride value is stored in a control register.
A data processing apparatus, wherein the stride value specifies the amount of the register address increment for all executed vector processing instructions. 5. The data processing apparatus according to claim 1, wherein a current register address input provided to a first adder input is added to the quantity input provided to a second adder input. And a register address adder for incrementing the register address is included in the instruction decoder. 6. The data processing apparatus according to claim 5, wherein said stride value selects an amount to be applied to said second input. 7. The data processing device according to claim 1, wherein said stride value is a coded representation of said quantity. 8. The data processing device according to claim 7, wherein the quantity is a natural number raised to a power of two. 9. The data processing apparatus according to claim 1, wherein the register address is also incremented based on whether the register address is in a subset of the registers in the register bank. Data processing equipment. 10. The data processing apparatus according to claim 1, wherein said subsequent execution is performed in an execution pipeline. 11. The data processing device according to claim 1, wherein a positive number is applied to said register address by said increment. 12. A data processing method, comprising: storing a data value to be manipulated in a register bank having a plurality of registers each having a register address; and at least one block. Responsive to a memory access instruction, performing a memory access between a plurality of contiguous address memory locations in the memory and a plurality of contiguous address registers in the register bank; Responsively performing a plurality of data processing operations on operands stored in a predetermined sequence of said register; and, during each execution of said data processing operations, In response, an opera used in said data processing operation Register address of the register that stores the de is incremented (increment) the amount specified by the stride value, the data processing method.