JP2018097598A - Digital signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal processing device capable of preventing the processing load or the processing time from becoming excessive even when the degree of filter became larger.SOLUTION: A vector computing processor 1 comprises: a zeroth register 20for storing input data; a first register 20for storing data of coefficients; a vector register reading part, a vector register writing part and a use register setting part for writing/reading of data to/from the zeroth and first registers; and a computing part 3 for performing computing processing using the vector operation of the data read out based on the setting. The use register setting part constitutes the zeroth and/or first registers as a ring buffer. The vector register reading part and the writing part write and read the data by sequentially switching the head position to read out from the zeroth and/or first registers constituted as the ring buffer. The computing part 3 performs the computing processing of the data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a digital signal processing apparatus that performs filter processing on various digital signals such as audio signals.

Conventionally, as a filter often used for filtering various digital signals, an IIR (Infinite Impulse Response) filter or FIR (Finite) filter is used.
Impulse Response) filter. These filters are used in various types of digital signal processing, and in particular, FIR filters are often used in audio signal processing and the like because they can be efficiently realized by hardware.

・・・（１）
ただしｘ［ｎ］：入力信号、ｙ［ｎ］：出力信号、ｈ［ｉ］：フィルタ係数、Ｎ：フィルタ次数
このＦＩＲフィルタ処理をディジタル信号処理において用いる場合には、一般に、下記式（２）に示すような積和演算処理を行う。

・・・（２）
ただしｘ［ｎ］：入力信号、ｙ［ｎ］：出力信号、ｈ［ｉ］：フィルタ係数、Ｎ：フィルタ次数
このような積和演算処理をＤＳＰ（Digital Signal Processor）を用いて実行する場合、最新の入力信号からＮ個分過去の入力信号までを保持しておく必要がある。そのため、ＦＩＲフィルタ処理を行う場合、過去の入力信号を記録しておくための、データの個数分のデータ格納領域が設けられたレジスタが用いられる。 In the FIR filter processing for a digital signal, for example, a voice signal, processing shown in the following formula (1) is performed.

... (1)
However, x [n]: input signal, y [n]: output signal, h [i]: filter coefficient, N: filter order When this FIR filter processing is used in digital signal processing, the following equation (2) is generally used. The product-sum calculation process as shown in FIG.

... (2)
However, x [n]: input signal, y [n]: output signal, h [i]: filter coefficient, N: filter order When such product-sum operation processing is executed using a DSP (Digital Signal Processor), It is necessary to hold from the latest input signal to N past input signals. Therefore, when performing FIR filter processing, a register provided with data storage areas for the number of data for recording past input signals is used.

  Here, since the filter characteristic becomes better as the filter order is larger, in the DSP constituting the FIR filter, the filter order N is often higher order such as 512, 1024, and 2048. Therefore, in the DSP filter processing, the same number of data as the filter order N is read, the same number of multiplications as the filter order N, and the addition processing (that is, product-sum operation) of the N multiplication results. As a result, the calculation processing for the filter processing increases, and the processing load of the filter processing in the DSP increases. For this reason, a configuration that can reduce the processing load of the filter processing in the DSP as much as possible is desired.

  On the other hand, conventionally, many vector arithmetic processing devices are used in digital signal processing. In this method, a plurality of vector registers and a vector calculator are used to sequentially read out data stored in the vector registers and perform a vector operation. Thereby, it becomes possible to apply a single instruction sequence to a plurality of data sequences and perform arithmetic processing in parallel.

  As such an FIR filter using parallel arithmetic processing, digital signal processing is performed using a multiplier / adder MAC0 that performs a part of multiplication / addition processing and a multiplier / adder MAC1 that performs the remaining multiplication / addition processing. A sample (data) that is commonly used by the multiplier / adder MAC0 and the multiplier / adder MAC1 is read from the data memory (register), and the sample is processed by the multiplier / adder MAC0 and the multiplier / adder MAC1. Thus, a configuration is known in which the number of times of reading of data recorded in a memory is reduced when performing product-sum operation processing in parallel (see, for example, Patent Document 1).

JP 2012-205298 A

  Here, in general, in a normal configuration for performing parallel processing of product-sum operations such as vector operations on a digital signal, a number for managing the position of each data storage area of the register storing the data (the register Data is read out and processed in the order of numbers (for example, ascending or descending order of numbers) of address information of individual data storage areas and index information assigned to individual storage areas. Therefore, when one parallel process is completed, a process of rewriting the data recorded in each data storage area of the register (for example, the data stored in each data storage area is changed to the data storage area with the number one higher. To store the data again, and delete the data of the oldest signal and newly store the latest data). Also in the said patent document 1, after such a process is performed, it is a premise that the parallel execution of the product-sum calculation process is performed sequentially. For this reason, in the above-mentioned Patent Document 1, there is a problem that processing for rewriting data in a register frequently occurs, and processing load and processing time for the processing are increased. This problem becomes particularly noticeable when the filter order is increased.

  On the other hand, when an input signal used in a digital filter having a plurality of filter orders such as an FIR filter is held, a ring buffer is used so that the data storage area constituting the register is managed in a ring shape. There are also many. If this ring buffer is used, it is not necessary to use a method of rewriting data stored in each data storage area every time a product-sum operation process is performed, so that management of the data storage area becomes easy. . However, in the ring buffer, the order of individual data (for example, the time-series order from the latest signal to the past signal) and the order of numbers for managing the data storage area (ascending order or descending order) match. do not become. Therefore, in the invention described in Patent Document 1, there is a problem that the processing load and the processing time cannot be reduced by using a ring buffer for the register, which becomes particularly excessive when the filter order becomes large.

  The present invention has been made in view of such a problem. In digital signal processing using a digital filter having a plurality of filter orders, even if the filter order is large, the processing load and processing time are increased. It is an object of the present invention to provide a digital signal processing device that can suppress an excessive amount.

  In order to solve this problem, the invention described in claim 1 is a digital signal processing apparatus that performs filtering of various digital signals using vector operations, and includes a plurality of storage areas for storing input data. A first storage means, a second storage means provided with a plurality of storage areas for storing coefficient data to be processed with respect to the input data, and the set first storage means and / or Input / output data control means for writing and reading the data to and from the first storage means and the second storage means based on the position and / or order of writing and reading the data to and from the second storage means And the data read from the first storage means and the data read from the second storage means are subjected to arithmetic processing by vector calculation. Processing means, and the input / output data control means sequentially writes or reads the data with respect to the plurality of data storage areas with respect to the first storage means and / or the second storage means. In this way, the read buffer is configured in order from the first storage unit configured as the ring buffer and / or the second storage unit configured as the ring buffer. The data is written to the data storage area and the data is read from the data storage area, and the arithmetic processing means is read from the data read from the first storage means and the second storage means. An arithmetic process is performed on the data by a vector operation.

  The invention according to claim 2 provides the first storage means configured as the ring buffer and / or the second storage means configured as the ring buffer in addition to the configuration according to claim 1. , Index control means for setting index information as a reference position when writing the data and reading the data, the index control means is the first storage means configured as the ring buffer The index information is set for the data storage area and / or the data storage area of the second storage means configured as the ring buffer, and the input / output data control means is configured to write the data and store the data When reading, the start position of the writing and reading is determined based on the index information. And wherein the writing and the reading of the data Te.

  According to a third aspect of the present invention, in addition to the configuration according to the first aspect, the arithmetic processing means performs a filter processing operation using an FIR filter.

  According to a fourth aspect of the present invention, in addition to the configuration according to any one of the first to third aspects, the input data is an audio signal.

According to the first aspect of the present invention, from the first storage means and / or the second storage means configured as a ring buffer, with respect to the data storage area, the reading start position is changed in order based on the setting. By writing data and reading data and performing arithmetic processing on the read data by vector operation, the data stored in the individual data storage areas in the ring buffer is changed each time processing is performed. Even if the data storage area is not rewritten and the data arrangement order does not coincide with the order of the numbers managing the data storage area, the data can be read out in the data arrangement order and the arithmetic processing can be performed by vector operation. Thereby, in the digital signal processing using the digital filter having a plurality of filter orders, it is possible to prevent the processing load and the processing time from becoming excessive even when the filter order becomes large.

  According to invention of Claim 2, the index information set to the data storage area of the 1st storage means comprised as a ring buffer, and / or the data storage area of the 2nd storage means comprised as a ring buffer Therefore, it is possible to realize the determination of the start position of data writing and reading and the writing and reading of data, so that the data stored in the individual data storage areas in the ring buffer is processed each time processing is performed. Even if it is not rewritten to another data storage area and the order of the data and the order of the numbers managing the data storage area do not match, the data is read out in the order of the data and the arithmetic processing is performed by vector operation. It can be realized easily and reliably.

  According to the invention described in claim 3, in the filter processing using the FIR filter, it is possible to prevent the processing load and the processing time from becoming excessive even when the filter order is high.

  According to the fourth aspect of the present invention, it is possible to suppress excessive processing load and processing time even when the filter order is high in the filter processing of the audio signal.

It is a functional block diagram which shows schematic structure of the vector arithmetic processing apparatus which concerns on this embodiment. It is a functional block diagram which shows schematic structure of the digital signal processing system which concerns on this embodiment. It is a functional block diagram which shows typically the outline of the structure of the vector arithmetic processing apparatus which concerns on this embodiment. It is a functional block diagram which shows typically the detail of a structure of the vector arithmetic processing apparatus which concerns on this embodiment. It is a functional block diagram which shows typically the structure of each register | resistor of the vector register which concerns on this embodiment. It is a functional block diagram which shows typically the structure of the vector command issuing part which concerns on this embodiment. It is a flowchart which shows the process sequence of the vector arithmetic processing apparatus which concerns on this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment. It is a figure which shows typically the storage state of the data in the vector register of the vector arithmetic processing unit concerning this embodiment.

  1 to 13 show an embodiment of the present invention.

[Basic configuration]
FIG. 1 is a functional block diagram showing a schematic configuration of a vector arithmetic processing apparatus as a “digital signal processing apparatus” according to this embodiment.

  A vector arithmetic processing apparatus 1 as a “digital signal processing apparatus” shown in FIG. 1 has a configuration (for example, a CPU) for realizing a function by executing a program, and is used for an apparatus that performs filter processing on various digital signals. It is done. Specifically, for example, the vector arithmetic processing apparatus 1 shown in FIG. 1 is incorporated in a gaming machine (not shown) such as a pachinko machine or a pachislot machine, and a speaker 14 (see FIG. 1) provided in the gaming machine (not shown). 2), the digital audio signal forming the audio output from (2) functions as an FIR filter and performs filter processing.

  As shown in FIG. 1, the vector arithmetic processing device 1 includes a vector register 2 and an arithmetic unit 3 as “arithmetic processing means”. Each configuration provided in the vector arithmetic processing device 1 is basically configured by hardware logic, but part or all of these configurations may be realized by executing a program. .

The vector register 2 records input data (audio signal) to be filtered in the vector arithmetic processing device 1, filter coefficients, and data (filtered audio signal) as a result of product-sum operation in the arithmetic unit 3. Storage element. As shown in FIG. 1, the vector register 2 has N (where N> 1) “0” registers 20 ₁ as “first storage means” and “second storage means” as data storage areas. A first register 20 ₂ ,... M-th register 20 _M (where M = N−1) is provided, and an audio signal before filter processing, coefficient data used for filter processing, and filter processing are performed. Each of the audio signals after the recording is recorded (details will be described later).

  The computing unit 3 includes an adder and a multiplier, and performs filter processing in the FIR filter by performing a product-sum operation on input data (audio signal).

  FIG. 2 is a functional block diagram showing a schematic configuration of the digital signal processing system according to this embodiment. As shown in the figure, the digital signal processing system 10 includes an audio signal processing device 11, a ROM 12, an amplifier 13, and a speaker 14. The audio signal processing device 11 includes a decoder 15, a vector arithmetic processing device 1, and an output unit 16.

  The audio signal processing apparatus 11 includes the vector arithmetic processing apparatus 1 according to this embodiment, and performs audio signal restoration by decoding and filter processing of the audio signal by an FIR filter and outputs the result. Each configuration provided in the audio signal processing device 11 is basically configured by hardware logic, but part or all of these configurations may be realized by executing a program. .

  The ROM 12 is a recording medium on which various data such as compression-encoded audio signals are recorded. The amplifier 13 amplifies the audio signal output from the audio signal processing device 11. The speaker 14 converts the sound signal into sound and outputs it to the outside.

  The decoder 15 restores the audio signal by decoding the encoded audio signal recorded in the ROM 12. The amplitude value of the audio obtained as a result of decoding is supplied to the vector arithmetic processing unit 1 for each sampling period. The output unit 16 has a communication interface function with the amplifier 13 (for example, I2S / SPDIF), and performs processing necessary for transmitting the audio signal filtered by the vector arithmetic processing device 1 to the amplifier 13.

  FIG. 3 is a functional block diagram schematically showing an outline of the configuration of the vector operation processing apparatus 1 according to this embodiment. As shown in the figure, the vector arithmetic processing apparatus 1 of this embodiment includes a ring buffer control unit 17 in addition to the vector register 2 and the arithmetic unit 3.

The ring buffer control unit 17 is necessary to configure part or all of the 0th register 20 ₁ , the first register 20 ₂ ,..., The Mth register 20 _N provided in the vector register 2 as a ring buffer. In other words, a read index and a write index are controlled (details will be described later).

  FIG. 4 is a functional block diagram schematically showing details of the configuration of the vector operation processing apparatus 1 according to this embodiment. As shown in the figure, the vector arithmetic processing unit 1 includes a vector instruction control unit 22 serving as a vector instruction issuing unit 21, a vector register reading unit 23 serving as an “input / output data control unit”, and an “input / output data control unit”. The vector register writing unit 24 is provided.

The vector instruction issuing unit 21 includes an input data control unit 211, an output data control unit 212, and a ring buffer control unit 17 as “input / output data control means” (the functions of these configurations will be described later). Vector instruction issue unit 21, by the function of the ring buffer controller 17, 1 vector register 2 registers example 0th register 20 ₁ is made to function as a ring buffer registers namely 0th register _20, a first register 20 _2, · · controlling the read index and write index data for the M register 20 _N. Specifically, an instruction for performing a vector operation using data recorded in the vector register 2 is issued. The vector instruction issuing unit 21 also includes the function of the ring buffer control unit 17 and controls register reading and writing indexes (details will be described later).

  The vector instruction control unit 22 controls the vector register reading unit 23 and the vector register writing unit 24 on the basis of the instruction output from the vector instruction issuing unit 21, and is necessary for controlling the calculation of data by vector calculation. Processing is performed (details will be described later).

Vector register reading unit 23, the registers in the vector register 2, for example, the 0th register 20 _1, the first register ₂₀ 2,... The M register 20 _N specified data storage area based on the index was in, for example, the 0 the register 20 _1, the 0 data storage region _{20 11} 0th index is assigned, the first data storage area _{20 12} first index is applied, the second data storage area _{20 13} in which the second index is assigned, Data recorded in the third data storage area 20 ₁₄ (see FIGS. 8 to 13) to which the third index is assigned is read by vector calculation and sent to the calculator 3.

Vector register write unit 24, an index of the result calculated each register 0th register 20 1 vector registers 2 by vector _operation, the first register 20 _2, are specified.. The M register 20 _N in adder 3 storage area based on, for example, sends to the 0th data storage area 20 _N1 where the 0th index of the M register 20 _N is applied.

The multiplier 31, the two values (specifically read from the vector register reading unit 23, and the audio signal read out from the 0 register 20 _1, the filter coefficient read out from the first register 20 ₂ ) Is multiplied. The adder 32 performs a process of adding the multiplication result in the multiplier 31 and the product-sum operation result temporarily recorded in the register 33. The register 33 has a function of temporarily recording data resulting from the addition by the adder 32.

FIG. 5 is a functional block diagram schematically showing a configuration of each register 0th register 20 ₁ , first register 20 ₂ ,... Mth register 20 _N of the vector register 2 according to this embodiment. As shown in the figure, the 0 register 20 _1, a plurality of, for example N (N> 1) of the 0 data storage area _{20 11,} the first data storage area ₂₀ 12,... The M data storage area _{20 1M,} An Nth data storage area _201N is provided. Similarly, the 0 data storage area _{20 21} of the first register 20 ₂ is also more example of N (N> 1), the first data storage area ₂₀ 22, ... M-th data storage area _{20 2M,} the N a data storage area _{20 2N,} zeroth data storage area _{20 M1} also the M register 20 _M more example of N (N> 1), the first data storage area ₂₀ M2, · · · the M data storage area _{20 MM} The Nth data storage area _20MN is provided. In each data storage area, for example, the data storage areas 20 ₁₁ , 20 ₁₂ , 20 _1M , and 20 _1N , data such as audio signals and filter coefficients are stored.

  FIG. 6 is a functional block diagram schematically showing the configuration of the vector instruction issuing unit 21 according to this embodiment. As shown in the figure, the vector instruction issuing unit 21 includes an input data control unit 211, an output data control unit 212, and a ring buffer control unit 17 as an “index control unit” shown in FIG. 213, a filter order setting unit 214, and a coefficient setting unit 215. The ring buffer control unit 17 includes a read index control unit 171 as an “index control unit” and a write index control unit 172 as an “index control unit”.

Input data control unit 211, the registers example 0th register 20 _1, the first register ₂₀ 2, a control for inputting ... data in the M register 20 _N (the value or the operation result of the speech signal and the filter coefficient) I do. Output data control section 212, from the M register 20 _N vector registers 2, performs control for outputting the data as a result of product-sum operation of the signal value and the filter coefficients.

The ring buffer controller 17 performs control for the functioning of the respective registers example 0th register 20 ₁ as a ring buffer. Specifically, the 0 index was applied to the 0th data storage area 20 ₁₁ of the storage area (e.g., the 0th register 20 ₁ of each register, the first index was applied to the first data storage area 20 _12, storing the second data second index was applied to the area 20 _13, third index was applied to the third data storage area 20 _14, etc. as a reference position or reference (see FIGS. 8 to 13)), for reading and writing data Take control. Reading the index controller 171, a 0 data storage area _{20 11} of each register eg 0th register 20 ₁ is configured as a ring buffer, the first data storage area ₂₀ 12, the data from the M data storage area _{20 1N} · · · Performs the control necessary for reading. Write index control unit 172, the zeroth data storage area _{20 11} of each register eg 0th register 20 ₁ is configured as a ring buffer, the first data storage area ₂₀ 12, the data in the M data storage area _{20 1N} · · · Performs the control necessary for writing.

Using register setting unit 213, at initialization, each register _{20 1,} 20 2, of the · · · 20 _N, setting the ones that store audio signals and filters counted like. The filter order setting unit 214 sets the filter order N for the filter processing in the computing unit 3 at the time of initial setting. The coefficient setting unit 215 sets coefficients h [0] to h [n−1] used for obtaining FIR filter coefficients at the time of initial setting (see FIGS. 8 to 13).

[Processing procedure]
FIG. 7 is a flowchart showing the processing procedure of the vector arithmetic processing apparatus 1 according to this embodiment. FIGS. 8 to 13 show the storage of data in the vector register 2 of the vector arithmetic processing apparatus 1 according to this embodiment. It is a figure which shows a state typically.

Hereinafter, based on FIG. 7 to FIG. 14, a processing procedure of the vector operation processing device 1 in this embodiment will be described. In the figure, it stores the 0th register 20 ₁ to input data, coefficients in the first register 20 _{and second} vector register 2 will be described with reference to the case of storing the product-sum operation result in the register M. Further, for the sake of simplicity, the description will be made based on the case where the filter order N is 4.

(1) First, as an initial setting, using the register setting unit 213 of the vector instruction issue unit 21 sets the 0th register 20 ₁ as a register for storing the input data, the first register as a register for storing the filter coefficients 20 ₂ And the M-th register _20N is set as a register for storing the product-sum operation result (step S1). Here, using the register setting unit 213 sets the 0th register 20 ₁ stores the input data as a ring buffer. Here, using the first M register 20 _N vector registers 2 as a register for storing the sum operation results, since results of multiply-and-accumulate operations is a single output, the vector register not 2 scalar register (shown May be used.

(2) As an initial setting, the filter order setting unit 214 of the vector instruction issuing unit 21 sets the filter order N (N = 4) in the computing unit 3. Each register of the vector register 2, such as the 0th register 20 ₁ , the first register 20 ₂ ,..., The Mth register 20 _M, is a data storage area for storing data, such as a data storage area 20 ₁₁ , 20 ₁₂ ,. When there are four or more 20 _1M and 20 _1N , four of them are set to be used for data storage. When a register having a smaller number of data storage areas than the filter order, for example, the M-th register _20N is set to be used in this embodiment, the number of data storage areas is set to the filter order (N = 4) It is desirable to perform processing for changing to another register such as the M-1th register (not shown).

(3) As an initial setting, the vector instruction issuing unit 21 instructs the vector instruction control unit 22 to register the 0th register 20 ₁ , the first register set as registers used for storing data in (1) and (2) above. register 20 _2, and the information of the M register 20 _N, 0th register 20 _1, the first register 20 _2, the information of the index to be added to the data storage area used of the M register 20 _N, the vector instruction control unit 22 It is issued to (Step S1). Then, the vector instruction control unit 22 gives an index to the data storage area used by the 0th register 20 ₁ , the first register 20 ₂ , and the Mth register 20 _N to be used (step S1). Specifically, for example, the 0th 0th data storage area _{20 11} of the register 20 ₁ 0th index, the first data storage area _{20 12} of the first index, the second data storage area _{20 13} second the second index, the third data storage area _{20 14} imparts third index, respectively. Similarly, the the first register 20 ₂ of the 0 data storage area _{20 21} 0th index, the first data storage area _{20 22} of the first index, the second data storage area _{20 23} of the second index , the third data storage area _{20 24} imparts third index, respectively. Similarly, the zeroth data storage area _{20 N1} of the M register 20 _N is the 0th index, the first data storage area _{20 N2} the first index, the second data storage area _{20 N3} second An index is _assigned to each of the third data storage areas 20N4 (see FIGS. 8 to 13).

(4) Further, as an initial setting, the coefficient setting unit 215, arithmetic unit coefficients h [0] used for the operation of the FIR filter in 3 ~h [n-1] of the data of the first register 20 _{and second} vector register 2 Store in storage areas 20 ₂₁ , 20 ₂₂ ... 20 _2M , 20 _2N . In this case, the coefficient setting unit 215, the coefficient h [0] to h first register 20 _{and second} data storage area ₂₀ 21 for storing the _{[n-1], 20 22} ··· 20 2M, 20 2N, 0th An N-1th (N = 4 here) index is set from the index (step S1). The coefficients h [0] to h [n−1] are stored in the data storage areas 20 ₂₁ , 20 ₂₂ ... 20 _2M , and 20 _2N in the order of the numbers 0 to N−1.

(5) As shown in FIG. 8, in the initial state, all the input 0th register 20 ₁ of the data storage area ₂₀ 11 before the data _storing, in 20 12 _{· · ·} 20 1M, _{20 1N} is "0" Stored. In addition, “0” is also stored in the data storage areas 20 _N1 , 20 _N2 ... 20 _NM , 20 _NN of the M-th register 20 _N that stores the product-sum operation result.

(6) Here, the vector instruction control unit 22 applies the 0th register to the read index control unit 171 and the write index control unit 172 of the ring buffer control unit 17 based on the following rules (a) and (b). set to cause the retrieval of storage and data of data into 20 ₁ (step S2). Further, the vector instruction control unit 22 sends the first register 20 ₂ and the Mth register 20 _N to the vector register reading unit 23 and the vector register writing unit 24 based on the following rules (c) and (d). The start position of data storage and data retrieval, the storage order, and the retrieval order are set (step S2).
(A) The write index control unit 172 sets the data storage areas 20 ₁₁ , 20 ₁₂ ... 20 _1M , 20 _1N of the 0th register 20 ₁ configured as a ring buffer in descending order of indexes assigned (that is, New data is stored (in the order of index numbers N-1, N-2,..., 1, 0).
(B) The read index control unit 171 sets a data storage area in which data is newly stored as a read start position, and sequentially reads data from the start position by circulating the index in ascending order (step S2). Specifically, for example, if the new input data X1 is stored in the second data storage area _{20 13} in which the second index of the zeroth register 20 ₁ is attached (see FIG. 10), the second data storage area _{20 12} , The third data storage area 20 ₁₃ to which the third index is assigned, the 0th data storage area 20 ₁₁ to which the 0th index is assigned, and the first data storage area 20 ₁₂ to which the first index is assigned. read out.
(C) Since the first register 20 ₂ is not configured as a ring buffer, the reading of data in the order shown in (lolo) is not performed, ascending index (i.e., the 0th index is assigned 0 data storage area 20 ₂₁ , first data storage area 20 ₂₂ assigned with the first index, second data storage area 20 ₂₃ assigned with the second index, and third data storage area 20 _assigned with the third index. ₂₃ in the order of ₂₃ ), and the arithmetic unit 3 performs multiplication and addition processing with the audio signal.
The value of the result (d) all of the multiplication processing and addition processing is performed is stored in the zeroth data storage area 20 _N1 where the 0th index of the M register 20 _N is applied.

(7) If the first input data X0 is input to the vector register writing unit 24, an input data control section 211 of the vector instruction issue unit 21, a fourth data storage 0th register 20 ₁ of the index 3 is assigned to store the input data in the area _{20 14,} and issues an instruction to the vector instruction control unit 22 (step S1).

(8) the vector instruction control unit 22, the 0th register 20 ₁ in the data storage region ₂₀ 11 is set as the vector register 2 for storing the input data in the above _(1), 20 12 _{· · ·} 20 1M, _{20 1N} In addition, the input data is stored based on the order set in (a) of (5) above.

  (9) The vector instruction issuing unit 21 outputs an instruction for performing the following processes (A) to (E) to the vector instruction control unit 22. The vector instruction control unit 22 controls the vector register reading unit 23, the vector register writing unit 24, and the arithmetic unit 3 based on this instruction.

(A) a 0 data storage area 20 and the 0 register 20 ₁ of the third data storage area _{20 14} input data X0 stored in the third index is assigned a 0 index of the first register 20 ₂ is assigned _The coefficient h [0] stored in ₂₁ is read out and multiplied by the arithmetic unit 3 (step S3, (1) in FIG. 9). The calculation result is stored in the register 33 of the calculator 3.

(B) at this stage, since all of the operational data of N (four) is not completed ( "No" in step S4), and shifts one zeroth register 20 _first read position (step S5). Then, since beyond the area in which the read position can store data (third data storage area _{20 23} third index is assigned) ( "Yes" in step S6), and the 0th register 20 _first read position, the 0 back to the 0th data storage region _{20 11} the index is assigned (step S7). Then, the data 0th index is stored in the zeroth data storage region 20 ₁₁ granted (0), the first index of the first register 20 ₂ is stored in the first data storage area 20 ₂₂ granted The coefficient h [1] is read out and multiplied by the arithmetic unit 3 ((2) in FIG. 9). The calculation result and the calculation result stored in the register 33 of the calculator 3 are added, and the calculation result is stored in the register 33 of the calculator 3 again (step S3).

(C) At this stage, since all of the operational data of N (four) is not completed (step S4 "No"), it shifted one zeroth register 20 _first read position (step S5). In this case, since the read position does not exceed the area (the third data storage area _{20 23} third index is assigned) that can store data ( "No" in step S6), and the first index of the zeroth register 20 ₁ There the data stored in the first data storage area 20 ₁₂ granted (0), the coefficient a second index of the first register 20 ₂ is stored in the second data storage area 20 ₂₃ granted h [2] Are multiplied by the arithmetic unit 3 ((3) in FIG. 9). The result of the addition process between the calculation result and the calculation result stored in the register 33 of the calculator 3 is stored again in the register 33 of the calculator 3 (step S3).

(D) at this stage, since all of the operational data of N (four) is not completed ( "No" in step S4), and shifts one zeroth register 20 _first read position (step S5). In this case, since the read position does not exceed the area (the third data storage area _{20 23} third index is assigned) that can store data ( "No" in step S6), and the second index of the zeroth register 20 ₁ read but a stored in the second data storage area 20 ₁₃ granted data, the third data storage area 20 coefficients h [3] which is stored in ₂₄ and the third index of the first register 20 ₂ is assigned Multiply by the arithmetic unit 3 ((4) in FIG. 9). The calculation result and the calculation result stored in the register 33 of the calculator 3 are added, and the calculation result is stored in the register 33 of the calculator 3 again (step S3).

(E) N pieces (4) after performing the product-sum operation on the data of the ( "Yes" in step S4), and the value R0 is the product sum operation result 0th index of the M register 20 _N is applied The data is written in the 0th data storage area 20 _N1 (step S8).

(10) the vector instruction issue unit 21 as the output result of the FIR filter 0th value R0 is a data storage region 20 ₁₁ is operation result stored in the 0th index of the M register 20 _N of the vector register 2 is assigned to output an instruction to the vector instruction control unit 22, the vector instruction control unit 22 instructs accordance outputs the data stored in the zeroth data storage area 20 _N1 where the 0th index of the M register 20 _N is applied .

(11) Next, the second input data X1 is input to the vector register write unit 24, as shown in FIG. 10, the second data storage area 20 in which the second index of the zeroth register 20 ₁ is applied ₁₃ stores data. Then, as shown in FIG. 10, the 0th register 20 ₁ of each data storage area _{20 11, 20 12, ··· 20} 1M (20 13), the data stored in the 20 1N _{(20 14),} first product-sum operation of the coefficient stored in the register 20 ₂ is performed, the value R1 is a result of the calculation is stored in the zeroth data storage area 20 _N1 where the 0th index of the M register 20 _N is applied. Further, the vector instruction issuing unit 21 issues an instruction so as to output the value R1 as the operation result, and the vector instruction control unit 22 performs the vector reading unit 23, the vector writing unit 24, and the arithmetic unit 3 based on the issued instruction. To control.

(12) Thereafter, in the same manner as shown in FIGS. 11 and 12, when the third input data X2,4 th input data X3 is inputted, the write data of the and the 0th register 20 ₁ in the same manner And the calculation are repeated sequentially to obtain the output of the FIR filter. As shown in FIG. 12, all of the data storage area ₂₀ 11 of the zeroth register 20 _1, 20 12, _{· · ·} 20 1M, ₂₀ after the value in _1N is stored, the fifth input data X4 is input when, as shown in FIG. 13, it replaces the data of the data storage area where the data to the earliest is stored (the third data storage area 20 14 in this case is the 0th register 20 ₁₎ to the latest data. Thereafter, the same processing is repeated.

  As described above, in the vector arithmetic processing apparatus 1 of this embodiment, since the vector arithmetic processing apparatus 1 having both the vector arithmetic function and the ring buffer function is used, the product-sum arithmetic processing of the FIR filter is performed by the vector arithmetic processing apparatus. Processing is performed on one side. Therefore, the processing load on the DSP (Digital Signal Processor) side can be reduced.

In this embodiment, the 0th register 20 ₁ which is configured as a ring buffer, based on the setting, for the zeroth data storage region 20 11 _to the third data storage area 20 ₁₄ while changing the head position of the read sequentially by performing arithmetic processing by the vector operation in the calculator 3 data read writes and data reads data in the zeroth register 20 ₁ which is configured as a ring buffer, stores individual data regions or the Each time the data stored in each of the 0 data storage area 20 ₁₁ to the third data storage area 20 ₁₄ is processed, another data storage area, that is, the 0th data storage area 20 ₁₁ to the third data storage area 20 is processed. ₁₄ to the data arrangement order and the data storage area, that is, the 0th data storage area 20 ₁₁ to the third To match the sequence of numbers to manage data storage region _{20 14} (e.g., the data storage area _{20 11,} 20 _12, 20 13, ₂₀ input data X0 in ascending order of _14, X1, X2, X3, X4 · · · Even if it is not rearranged), the data can be read out in the order of the data and the arithmetic processing can be performed by vector operation. Thereby, in the digital signal processing using the digital filter having a plurality of filter orders, it is possible to prevent the processing load and the processing time from becoming excessive even when the filter order becomes large.

In this embodiment, based on the 0th register 20 ₁ of the 0 data storage region 20 11 _to the third data storage area 20 ₁₄ of the set index information i.e. the 0 index to third index that is configured as a ring buffer Te, since and performing writing and reading of determining the data at the top position of the data writing and reading can be realized, in the zeroth register 20 ₁ as a ring buffer, each data storage region or the 0th data storage area 20 _{11 to} the third data stored in the data storage area 20 _14, the arrangement of the process is rewritten to the other data storage areas i.e. the 0 data storage region 20 11 _to the third data storage area 20 ₁₄ whenever carried out data forward a data storage area, that the zeroth data storage region _{20 11} to the third data storage area 20 ₁ To match the order of managing numbers (for example, the data storage area _{20 11,} 20 _12, 20 13, ₂₀ input data X0 in ascending order of _14, X1, X2, X3, rearranges the X4 · · ·) Even if it does not perform, it can implement | achieve simply and reliably that data is read in the arrangement order of data, and an arithmetic process is performed by vector calculation.

  In this embodiment, in the filter processing using the FIR filter in the arithmetic unit 3, it is possible to prevent the processing load and the processing time from becoming excessive even when the filter order is high.

  In this embodiment, it is possible to prevent the processing load and the processing time from becoming excessive even when the filter order becomes high in the filter processing of the audio signal.

In the above embodiment, although the 0th register 20 ₁ for storing the audio signal is configured as a ring buffer, not limited thereto, and a first register 202 for storing a filter attribute, the result of multiply-add operation the first M register 20 _N for storing may be configured as a ring buffer. Two to three of the 0th register 20 ₁ , the first register 20 ₂ , and the Mth register 20 _N may be configured as a ring buffer.

In the above-described embodiment, specifying a write position and read position on the 0th register 20 ₁ configured, optionally the data storage area _{20 11,} 20 _12, 20 13, _{20 14} an index assigned to the reference as a ring buffer configuration and the but capable, not limited thereto, the data storage area _{20 11,} 20 _12, 20 13, _{20 14} any identifiable configuration read position or write position, for example, the data storage area _{20 11, 20} 12, 20 _13, the 20 ₁₄ address information such as the configuration to identify any, if, may be of any type.

  In the above embodiment, the vector arithmetic processing apparatus 1 handles an audio signal as a processing target. However, the present invention is not limited to this, and any digital signal other than the audio signal, for example, an image signal or the like is a processing target. You may do.

  In the above embodiment, the vector arithmetic processing apparatus 1 functions as an FIR filter. However, the present invention is not limited to this, and any filter other than the FIR filter, for example, an IIR filter may perform the filter process. Good.

  In the above embodiment, the vector arithmetic processing apparatus 1 is used for a gaming machine (not shown), but may be used for any application other than a gaming machine.

  The above embodiment is an exemplification of the present invention, and it is needless to say that the present invention is not limited to the above embodiment.

1 ... Vector arithmetic processing device (digital signal processing device)
3 ... Calculator (arithmetic processing means)
20 ₁ ... 0th register (first storage means)
20 ₂ ... First register (second storage means)
20 ₁₁ , 20 ₁₂ , 20 ₁₃ , 20 ₁₄ , 20 ₂₁ , 20 ₂₂ , 20 ₂₃ , 20 ₂₄ , 20 _{N 1} , 20 _{N 2} , 20 _{N 3} , 20 _{N 4} ,... Data storage area 171. (Index control means)
172 ... Write index control section (index control means)
211 ... Input data control unit (input / output data control means)
212 ... Output data control unit (input / output data control means)
213... Used register setting unit (input / output data control means)
23. Vector register reading section (input / output data control means)
24... Vector register writing unit (input / output data control means)
X0, X1, X2, X3, X4 ... Input data h [0] to h [n-1] ... Coefficient

Claims (4)

A digital signal processing apparatus that performs filtering of various digital signals using vector operations,
A first storage means comprising a plurality of data storage areas for storing input data;
Second storage means comprising a plurality of data storage areas for storing coefficient data to be processed with respect to the input data;
Based on the set position and / or order of the data writing and reading with respect to the first storage means and / or the second storage means, the first storage means and the second storage means Input / output data control means for writing and reading data;
Computation processing means for performing computation processing by vector computation on the data read from the first storage means and the data read from the second storage means,
The input / output data control unit controls the first storage unit and / or the second storage unit to sequentially write or read the data to or from the plurality of data storage areas. The data storage area is configured as a ring buffer and the first storage means configured as the ring buffer and / or the second storage means configured as the ring buffer is changed in order from the read start position. Writing the data to and reading the data from
The arithmetic processing means performs a digital operation on the data read from the first storage means and the data read from the second storage means by vector calculation. Processing equipment. An index as a reference position when writing the data and reading the data with respect to the first storage means configured as the ring buffer and / or the second storage means configured as the ring buffer Comprising index control means for setting information;
The index control means includes the index for the data storage area of the first storage means configured as the ring buffer and / or the data storage area of the second storage means configured as the ring buffer. Set the information,
The input / output data control means determines the start position of the writing and the reading based on the index information when writing the data and reading the data, and performs the writing and reading of the data. The digital signal processing apparatus according to claim 1.   The digital signal processing apparatus according to claim 1, wherein the arithmetic processing unit performs a filter processing operation using an FIR filter.   4. The digital signal processing apparatus according to claim 1, wherein the input data is an audio signal.

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