JP2008085923A - Digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cause a digital filter to make computation with an accuracy of computation adapted to conditions of an execution of filtering-processing and avoid needless electrical power consumption. <P>SOLUTION: Filter coefficients in a coefficient storing section 200 are rewritable via an interface 300 under control of a coefficient rewriting control section 401. Data path section 100 executes computation for applying filtering-processing using the filter coefficients in the coefficient storing section 200 to an input audio sample x(n). A filtering-processing control section 402 is means for controlling computation of the data path section 100, and makes selection of whether the single precision arithmetic or double precision arithmetic is to be executed in dependence on the filter coefficient stored in the coefficient storing section 200. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a digital filter suitable for audio equipment and the like.

  Digital filters can be integrated circuits, and can be downsized, priced, and highly reliable, and filter characteristics can be easily adjusted by software processing. Has advantages. This digital filter is realized by, for example, a DSP (Digital Signal Processor) programmed to execute desired filter processing. Recently, a digital filter having a configuration in which a user can freely rewrite filter coefficients used for filter processing has been provided.

  FIG. 10 is a block diagram showing a functional configuration of this type of digital filter. This digital filter is composed of a DSP programmed to function as this three-band equalizer. Here, the 3-band equalizer is formed by cascading equalizers EQ0, EQ1, and EQ2 each configured by an IIR (Infinite Impulse Response) filter, and has a desired frequency characteristic for an input audio sample x (n). Is output as an output audio sample y (n). Such an IIR filter for an equalizer is disclosed in Patent Document 1, for example. The digital filter shown in FIG. 10 performs the illustrated delay processing 901 to 912, multiplication processing 921 to 936, and addition processing 941 to 943 in each sampling period in order to serve as a three-band equalizer. To do.

In each sampling period, the multiplication processes 921 to 935 multiply the output signal values dEQ00 and the like of the delay processes 901 to 911 by the illustrated filter coefficient cEQ00 and the like, respectively. In each sampling cycle, the output value of the multiplication processes 921 to 925 is added in the addition process 941, the output values of the multiplication processes 926 to 930 are added in the addition process 942, and the multiplication process is performed in the addition process 943. Each output value of 931-935 is added. As a result, signal values dEQ10, dEQ20, and dEQ30 shown in the following equations (1) to (3) are calculated as output values of the addition processes 941 to 943, and this calculation result is obtained when switching to the next sampling period. The signal value is updated at the same time.
dEQ10
= CEQ00 * dEQ00 + cEQ01 * dEQ01 + cEQ02 * dEQ02
+ CEQ03 × dEQ10 + cEQ04 × dEQ11 (1)
dEQ20
= CEQ10 x dEQ10 + cEQ11 x dEQ11 + cEQ12 x dEQ12
+ CEQ13 × dEQ20 + cEQ14 × dEQ21 (2)
dEQ30
= CEQ20 x dEQ20 + cEQ21 x dEQ21 + cEQ22 x dEQ22
+ CEQ23 × dEQ30 + cEQ24 × dEQ31 (3)

FIG. 11 schematically shows a filter characteristic of one of the equalizers EQx (x = 0 to 2) shown in FIG. As shown in FIG. 11, the filter characteristic of one equalizer EQx is specified by the peak frequency f0 at which the gain of the signal to be passed is maximized, the gain G at the peak frequency f0, and the queue Q indicating the sharpness of frequency selection. . When the target peak frequency f0, gain G, and queue Q of the equalizer EQx in the x-th band (x = 0 to 2) are given, the filter coefficients cEQx0, cEQx1, cEQx2, cEQx3, cEQx4 used for the equalizer EQx Is calculated by the following equation.
cEQx0 = (1 + α × A) / β (4)
cEQx1 = −2 × (cosω) / β (5)
cEQx2 = (1−α × A) / β (6)
cEQx3 = 2 × (cosω) / β (7)
cEQx4 =-(1-α / A) / β (8)

However, A, ω, α, and β are as follows. In the following, Fs is a sampling frequency.
A = 10 ^ (G / 40) (9)
ω = (2 × π × f0) / Fs (10)
α = (sin ω) / (2Q) (11)
β = 1 + (α / A) (12)

  For each of the equalizers EQx (x = 0 to 2), the user sets the filter coefficients cEQx0, cEQx1, cEQx2, cEQx3, and cEQx4 based on a desired peak frequency f0, gain G, and queue Q, for example. It can be calculated and written to the coefficient storage unit of the digital filter. When this coefficient writing is performed, the digital filter functions as a three-band equalizer that performs the calculations of the above formulas (1) to (3) using the filter coefficients written in the coefficient storage unit.

  Now, the multiplication processes included in the above formulas (1) to (3), that is, the multiplication processes 921 to 936 in FIG. 10, are executed by using a multiplier in the DSP under time division control. Further, the addition processes included in the above formulas (1) to (3), that is, the addition processes 941 to 943 in FIG. 10, are executed by using adders in the DSP under time division control. Here, since multipliers and adders in the DSP handle data of a finite bit width, an error is inevitably generated in the calculation. If this calculation error is large, it may not be possible to obtain a three-band equalizer that satisfies the required specifications (for example, peak frequency f0, gain G, and queue Q). In particular, a digital filter constituted by an IIR filter such as a three-band equalizer shown in FIG. 10 has an advantage that the amount of calculation is smaller than that of an FIR (Finite Impulse Response) filter, while the calculation error is small. If it is large, an oscillation phenomenon called a limit cycle may be caused.

  However, the calculation accuracy, which is the difference between whether or not a failure such as a lack of requirement specifications or a limit cycle occurs, is not constant and depends on what filter processing is executed. For example, in the case of an IIR filter as shown in FIG. 10, when the peak frequency f0 that is the center of the passband is high, no problem occurs even if the calculation accuracy is not so high, but when the peak frequency f0 is low. If the calculation accuracy is not increased, problems tend to occur. Therefore, when the DSP performs filter processing under various conditions (for example, the peak frequency f0), the calculation accuracy required to prevent the occurrence of malfunctions is the highest among the filter processing executed under these conditions. It is necessary to obtain a high calculation accuracy in the worst case, that is, to ensure the calculation accuracy.

  Conventionally, there are two methods for designing a digital filter in consideration of such a worst case. The first method is a design method that matches the original calculation accuracy of the DSP arithmetic unit, more specifically, the bit width of the multiplier or adder to what is required in the worst case.

The second method does not optimize the DSP hardware configuration in accordance with the worst case as in the first method. In the worst case, the double-precision operation is executed by the computing unit in the worst case, which is necessary in the worst case. This is a technique for ensuring the calculation accuracy. For example, in the three-band equalizer shown in FIG. 10, assuming the worst case, if the original calculation accuracy of the DSP multiplier or adder does not satisfy the required calculation accuracy, the second method uses the following formula for the DSP: The double precision calculation shown in (13) to (15) is executed to obtain the required calculation precision.
dEQ10
= CEQ00 x dEQ00L + cEQ01 x dEQ01L + cEQ02 x dEQ02L
+ CEQ03 x dEQ10L + cEQ04 x dEQ11L
+ CEQ00 × dEQ00U + cEQ01 × dEQ01U + cEQ02 × dEQ02U
+ CEQ03 × dEQ10U + cEQ04 × dEQ11U (13)
dEQ20
= CEQ10 x dEQ10L + cEQ11 x dEQ11L + cEQ12 x dEQ12L
+ CEQ13 x dEQ20L + cEQ14 x dEQ21L
+ CEQ10 × dEQ10U + cEQ11 × dEQ11U + cEQ12 × dEQ12U
+ CEQ13 × dEQ20U + cEQ14 × dEQ21U (14)
dEQ30
= CEQ20 x dEQ20L + cEQ21 x dEQ21L + cEQ22 x dEQ22L
+ CEQ23 x dEQ30L + cEQ24 x dEQ31L
+ CEQ20 × dEQ20U + cEQ21 × dEQ21U + cEQ22 × dEQ22U
+ CEQ23 × dEQ30U + cEQ24 × dEQ31U (15)

In the above equations (13) to (15), dEQxyL (x = 0 to 2, y = 0 to 4) is a lower bit of the signal value dEQxy (x = 0 to 2, y = 0 to 4), dEQxyU (x = 0-2, y = 0-4) are the upper bits of the signal value dEQxy (x = 0-2, y = 0-4).
JP 2003-110405 A

  By the way, the above-described first method has a problem that the hardware for calculation becomes large because the calculation accuracy of the multiplier or the like is determined in accordance with the worst case. Further, there is a problem that power consumption increases as the hardware for computation becomes larger. In addition, since the second method described above does not change the hardware scale for the calculation, the hardware scale can be reduced as compared with the first method, but the calculation in accordance with the worst case is possible. In order to obtain accuracy, the number of computations is increased and double precision computation is performed, which causes a problem that power consumption increases. In both the first and second methods, the calculation accuracy of the digital filter is fixed to the calculation accuracy that can withstand use in the worst case. However, in the case of a digital filter in which the user can freely rewrite the filter coefficient, the digital filter may be used even under conditions that are not the worst case (for example, the peak frequency f0 is increased). Even in such a case, the digital filter designed by the first method or the second method operates with the calculation accuracy determined in consideration of the worst case, that is, the calculation accuracy higher than the originally required calculation accuracy. Therefore, there is a problem in that power is wasted due to calculation with excessive calculation accuracy.

  The present invention has been made in view of the circumstances as described above, and provides a digital filter that can perform computations with computation accuracy commensurate with the execution conditions of filter processing and that reduces wasteful power consumption. It is an object.

The present invention relates to a coefficient storage means for storing a filter coefficient to be multiplied by a signal to be processed for filtering or a filter coefficient to be multiplied to a signal generated in the processing process of the filter processing, and Coefficient rewriting control means for performing rewriting, arithmetic means for performing an operation for applying a filter process using the filter coefficient stored in the coefficient storage means to the signal to be processed, and means for controlling the calculation by the arithmetic means And filtering processing control means for performing switching control of calculation accuracy of calculation by the calculation means by changing a use mode of the calculation means based on a parameter indicating an execution condition of the filter processing. Provide a digital filter.
According to this invention, since the calculation accuracy of the calculation by the calculation means is switched based on the execution condition of the filter process, when performing the filter process under various execution conditions, the appropriate calculation accuracy that matches the execution condition Thus, computation for filtering is performed, and unnecessary power consumption is avoided.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram showing the configuration of a digital filter according to the first embodiment of the present invention. This digital filter is a DSP programmed to perform the filtering process as the 3-band equalizer of FIG. 10 on the input audio sample x (n) and output the audio sample y (n) obtained as a result. A pass unit 100, a coefficient storage unit 200, an interface 300, and a control unit 400 are included.

  The coefficient storage unit 200 is a means for storing a filter coefficient cEQxy (x = 0 to 2, y = 0 to 4) used for the filter processing as the three-band equalizer shown in FIG. 10, and is a rewritable nonvolatile memory such as an EEPROM. It is composed of a memory.

  The data path unit 100 is a device that performs an operation for filter processing as the three-band equalizer shown in FIG. 10, and includes an arithmetic unit 110 including a multiplier 111, an adder 112, and a register 113, a work RAM 120, and a multiplier. And selectors 131 and 132 for selecting input information to be given to 111.

  Here, the work RAM 120 is a storage device used for the delay processes 901 to 912 and the like shown in FIG. 10, and is data of 2N bits (N is a plurality) indicating the signal value dEQxy of each node of the 3-band equalizer shown in FIG. Remember. The multiplier 111 is a device that performs the multiplication processes 921 to 936 and the like shown in FIG. 10, and multiplies two pieces of N-bit input data to output 2N-bit data. The selector 131 selects a filter coefficient cEQxy (x = 0 to 2, y = 0 to 4) in the coefficient storage unit 200 that is instructed by the control unit 400 and supplies the selected one to the multiplier 111. The selector 132 selects the signal value dEQxy read from the work RAM 120 or the input audio sample x (n) according to an instruction from the control unit 400 and supplies the selected signal value dEQxy to the multiplier 111. Here, when the selector 132 supplies the signal value dEQxy read from the work RAM 120 to the multiplier 111, the selector 132 outputs the upper N bits or the lower N bits of the 2N-bit signal value dEQxy according to an instruction from the control unit 400. This is selected and supplied to the multiplier 111. The 2N-bit data output from the multiplier 111 is sign-extended in the process of being supplied to the adder 112, and becomes 2N + M-bit data in which an integer part M bits are added after the sign bit. The adder 112 and the register 113 accumulate the 2N + M-bit data, and calculate the signal values dEQ10, dEQ20, and dEQ30 of the above equations (1) to (3) or the above equations (13) to (15). Functions as an arithmetic unit. The above processing of each unit in the data path unit 100 is performed in synchronization with a clock φ having a predetermined frequency supplied from the control unit 400.

  The interface 300 is a device that exchanges signals with devices external to the digital filter. The digital filter obtains an input audio sample x (n) from the outside by using this interface 300, and outputs an output audio sample y (n) obtained by the filter processing as a 3-band equalizer to the outside. In addition, when the filter coefficient in the coefficient storage unit 200 is rewritten, the interface 300 is connected to an external device such as a personal computer and plays a role of receiving a rewrite filter coefficient and a filter coefficient rewrite command from the external device.

  The control unit 400 is means for controlling the entire digital filter. In a preferred embodiment, the control unit 400 includes a CPU, a ROM that stores a program executed by the CPU, and a working RAM. The control unit 400 includes a coefficient rewrite control unit 401 and a filter processing control unit 402. These entities are programs executed by the CPU of the control unit 400.

  When an external device such as a personal computer is connected to the interface 300 when the coefficient rewrite control unit 401 receives a filter coefficient and a filter coefficient rewrite command from the external device via the interface 300, the coefficient rewrite control unit 401 uses the received filter coefficient to generate a coefficient. This is means for rewriting the filter coefficient in the storage unit 200.

  The filter processing control unit 402 is a unit that controls filter processing as a three-band equalizer performed by the data path unit 100. The feature of this embodiment is in the mode of control of filter processing performed by the filter processing control unit 402. Under the conventional technique, the calculation accuracy of the digital filter calculation process is determined in accordance with the worst-case execution condition among various execution conditions of the filter process, and the digital filter executes the filter process under any execution condition. Even in this case, the calculation for the filter processing was performed with the determined calculation accuracy. On the other hand, the filter processing control unit 402 according to the present embodiment has the worst-case or non-worst-case execution conditions for the equalizer EQx for each of the equalizers EQx (x = 0 to 2) constituting the three-band equalizer. In accordance with the determination result, the calculation accuracy of the filter processing as the equalizer EQx is determined, and the data path unit 100 is controlled so that the filter processing is performed with such calculation accuracy. That is, when the execution condition is a non-worst case, the arithmetic unit 110 of the data path unit 100 performs a single precision operation, and when the execution condition is the worst case, the arithmetic unit 110 of the data path unit 100 Double precision calculation is performed. Further details are as follows.

  First, each equalizer EQx (x = 0 to 2) constituting the 3-band equalizer shown in FIG. 10 is filtered without causing a malfunction (a requirement specification is not satisfied, a limit cycle is generated, etc.) as the peak frequency f0 is lower. The calculation accuracy required for processing is increased. That is, for each equalizer EQx, whether the execution condition is the non-worst case or the worst case is determined by the peak frequency f0. If the peak frequency f0 is equal to or greater than a certain threshold value, no problem occurs even in single precision calculation (non-worst case). When the peak frequency f0 is lower than the threshold value, a problem is likely to occur unless the double precision calculation is performed (worst case). And in this embodiment, in the range of the peak frequency f0 which is the range of the peak frequency f0 which does not produce a malfunction even if the filtering process by the single precision computation is performed, and the peak frequency f0 where the malfunction occurs if the double precision computation is not performed. The boundary with a certain double precision calculation zone is in the vicinity of 500 Hz.

  In the present embodiment, the peak frequency f0 useful for the determination of the non-worst case / worst case is not directly given to the digital filter, but the filter coefficient cEQxy (x = 0 to 2, calculated using this peak frequency f0). y = 0 to 4) is given to the digital filter. Some of the filter coefficients cEQxy (x = 0 to 2, y = 0 to 4) greatly depend on the peak frequency f0. FIG. 2 shows how the filter coefficient cEQxy (y = 0 to 4) changes when the peak center frequency f0 is changed in the IIR filter that performs processing of the x-th band of the 3-band equalizer. In this figure, the single precision calculation zone and the double precision calculation zone are shown together with the filter coefficient cEQxy (y = 0 to 4).

  As shown in FIG. 2, the filter coefficients cEQx1 and cEQx3 greatly depend on the peak frequency f0, and the filter coefficient cEQx1 becomes closer to −2.0 as the peak frequency f0 becomes lower, and the filter coefficient cEQx3 has a lower peak frequency f0. Indeed, it is close to 2.0. Therefore, if an appropriate threshold value is provided, for example, if the filter coefficient cEQ1 falls below the threshold value, a double precision calculation is performed, and if the filter coefficient cEQ1 is equal to or greater than the threshold value, a single precision calculation is performed. It can be seen that an appropriate calculation accuracy can be selected. Therefore, in the present embodiment, the filter processing control unit 402 compares the filter coefficient cEQx1 with the threshold value −1.99, and if cEQx1 <−1.99, double precision calculation, and cEQx1 ≧ −1.99, single precision. The calculation is selected as the calculation accuracy for the filtering process.

  FIG. 3 shows the validity of the threshold value -1.99 used in this case, and when the filter coefficient cEQx1 is calculated for various combinations of the queue Q and the gain G in the range where the peak frequency f0 is 1000 Hz or less. The number of times that the filter coefficient cEQx1 falls below -1.99. As shown in FIG. 3, in the region where the peak frequency f0 is higher than 650 Hz, the filter coefficient cEQx1 never falls below −1.99 regardless of the combination of the cue Q and the gain G. The filter coefficient cEQx1 starts to fall below -1.99 when the peak f0 becomes 650 Hz or less. Therefore, if the double precision calculation is performed when the filter coefficient cEQx1 falls below -1.99 as described above, it is guaranteed that the double precision calculation is always performed when the peak frequency f0 is 500 Hz or less. .

In addition to the functions described above, the filter processing control unit 402 is a clock that is supplied to the data path unit 100 during a period until the next sampling cycle starts when all filter processing to be executed within one sampling cycle is completed. It has a function to stop φ and avoid unnecessary power consumption.
The above is the details of the configuration of the digital filter according to the present embodiment.

  Next, the operation of this embodiment will be described. FIG. 4 is a state transition diagram showing the operation of the filter processing control unit 402 in the present embodiment. In this embodiment, the filter processing control unit 402 causes the data path unit 100 to perform filter processing as an equalizer EQx (x = 0 to 2) in each sampling period, and outputs one audio sample y (n). Let

  The DSP operation idle state DSPIDLE is a state in which all processes to be executed in one sampling period are completed and the next sampling period starts. The filter processing control unit 402 stops the supply of the clock φ to the data path unit 100 in the DSP calculation idle state DSPIDLE. In the DSP calculation idle state DSPIDLE, when the FS flag indicating the start of the sampling period is asserted, the filter processing control unit 402 refers to the filter coefficient cEQ01 in the coefficient storage unit 200, and cEQ01 ≧ −1.99. In this case, the state is transited to the single-precision arithmetic state EQ0, and when cEQ01 <−1.99, the state is transited to the double-precision arithmetic state BIEQ0. Then, the supply of the clock φ to the data path unit 100 is started.

  In the single-precision calculation state EQ0, the filter processing control unit 402 causes the data path unit 100 to execute the single-precision calculation of the above equation (1), and the output signal value dEQ10 of the equalizer EQ0 obtained as a result is the first in the work RAM 120. Are stored in the calculation result storage area. In the double precision operation state BIEQ0, the data path unit 100 is caused to execute the double precision operation of the above equation (13), and the output signal value dEQ10 of the equalizer EQ0 obtained as a result is stored in the first calculation result storage area in the work RAM 120. To store.

  When the single-precision operation state EQ0 or the double-precision operation state BIEQ0 ends, the filter processing control unit 402 refers to the filter coefficient cEQ11 in the coefficient storage unit 200, and when cEQ11 ≧ −1.99, the state is single-precision. Transition to operation state EQ1. Then, the output signal value dEQ20 of the equalizer EQ1 is calculated by the data path unit 100 by the single precision calculation of the above equation (2), and the output signal value dEQ20 is stored in the second calculation result storage area in the work RAM 120. On the other hand, when cEQ11 <−1.99, the state is shifted to the double precision operation state BIEQ1. Then, the output signal value dEQ20 of the equalizer EQ1 is calculated by the double precision calculation of the above equation (14), and the output signal value dEQ20 is stored in the second calculation result storage area in the work RAM 120.

  When the single-precision calculation state EQ1 or the double-precision calculation state BIEQ1 ends, the filter processing control unit 402 refers to the filter coefficient cEQ21 in the coefficient storage unit 200, and if cEQ21 ≧ −1.99, the state is single-precision. Transition to operation state EQ2. Then, the output signal value dEQ30 of the equalizer EQ2 is calculated by the data path unit 100 by the single precision calculation of the above equation (3), and the output signal value dEQ30 is stored in the third calculation result storage area in the work RAM 120. On the other hand, if cEQ21 <-1.99, the state is shifted to the double-precision operation state BIEQ2. Then, the signal value dEQ30 of the equalizer EQ2 is calculated by the double precision calculation of the above equation (15), and the output signal value dEQ30 is stored in the third calculation result storage area in the work RAM 120.

  When the single-precision arithmetic state EQ2 or the double-precision arithmetic state BIEQ2 ends, the filter processing control unit 402 changes the state to the fade-out / fade-in arithmetic state FADE. Then, the data path unit 100 executes the multiplication process 936 shown in FIG. 10 to output the audio sample y (n) to the outside of the digital filter. Further, in order to execute the delay processes 901 to 912 of FIG. 10, for example, the signal value dEQ01 is moved to an area for storing the signal value dEQ02 in the work RAM 120, and the signal value dEQ00 is stored to store the signal value dEQ01. Move to the area, and change the storage area of each signal value dEQxy, and so on. Further, the signal values dEQ10, dEQ20, and dEQ30 stored in the first to third calculation result storage areas in the work RAM 120 are stored in the areas provided for the respective signal values. Then, the input audio sample x (n) is selected by the selector 132 and stored in the area for the signal value dEQ00 in the work RAM 120. In the next sampling period, the signal value dEQxy of each storage area in which the content is updated in this way is used for the calculations of the above formulas (1) to (3) or the above formulas (13) to (15). When the fade-out / fade-in operation state FADE is completed, the filter processing control unit 402 changes the state to the DSP operation idle state DSPIDLE.

  In the present embodiment, the filter coefficient in the coefficient storage unit 200 is updated through the interface 300 even during the period in which the digital filter is executing the filter process, whereby the equalizer EQx (x = 0 to 2). ), Switching between single-precision arithmetic / double-precision arithmetic may occur. In this case, the filter processing control unit 402 causes the data path unit 100 to execute a fade-out process in the fade-out / fade-in calculation state FADE. This fade-out process is a process of gradually decreasing the multiplication coefficient FADE by which the output signal value dEQ30 of the equalizer EQ2 is multiplied in the multiplication process 936 from 1 to approach 0 by using a predetermined number of sampling periods.

  When the fade-out processing is completed and the multiplication coefficient FADE becomes 0, the filter processing control unit 402 changes the state to the work RAM initialization state MEMCLR when the state transits to the DSP operation idle state DSPIDLE in the immediately following sampling period. Transition. In this work RAM initialization state MEMCLR, the filter control unit 402 initializes the signal value dEQxy of each node of the 3-band equalizer shown in FIG. 10 stored in the work RAM 120 of the data path unit 100. When this initialization is completed, the filter processing control unit 402 causes the data path unit 100 to execute the fade-in process when the state becomes the fade-out / fade-in calculation state FADE in the immediately following sampling cycle. This fade-in process is a process of gradually increasing the multiplication coefficient FADE multiplied by the output signal value dEQ30 of the equalizer EQ2 in the multiplication process 936 from 0 to approach 1 by using a predetermined number of sampling periods.

  When switching between single-precision arithmetic / double-precision arithmetic occurs in this way, the signal value in the work RAM 120 is initialized after the fade-out process is performed, and the filter process as the three-band equalizer is restarted after the fade-in process. Therefore, it is possible to prevent the output audio sample y (n) from generating noise due to the switching of the calculation accuracy.

  5 and 6 are time charts showing a specific operation example of the present embodiment. In the example illustrated in FIG. 5, the execution conditions of the equalizer EQx (x = 0 to 2) are all the worst case, and the filter coefficients cEQx1 (x = 0 to 2) are all less than −1.99, so that one sampling is performed. During the period, double precision operation states BIEQ0, BIEQ1, BIEQ2, fade-out / fade-in operation state FADE, and DSP operation idle state DSPIDLE are generated. On the other hand, in the example shown in FIG. 6, the execution conditions of the equalizer EQx (x = 0 to 2) are all non-worst cases, and the filter coefficients cEQx1 (x = 0 to 2) are all −1.99 or more. Therefore, during one sampling period, single-precision calculation states EQ0, EQ1, EQ2, a fade-out / fade-in calculation state FADE, and a DSP calculation idle state DSPIDLE are generated. Here, as also shown in the above equations (1) to (3) and the above equations (13) to (15), the number of multiplication processes performed in the single precision operation state EQx (x = 0 to 2). Is ½ of the number of multiplications performed in the double precision operation state BIEQx (x = 0 to 2). Therefore, the duration of the single-precision computation state EQx (x = 0 to 2) is about ½ of the duration of the double-precision computation state BIEQx (x = 0 to 2). Therefore, as shown in the figure, when the execution condition of the equalizer EQx (x = 0 to 2) is a non-worst case (FIG. 6), the data path unit 100 is compared to the worst case (FIG. 5). The period during which the clock φ is supplied is shortened and power consumption is reduced.

  Next, with reference to FIG. 7, a mode of multiplication and addition processing of the filter coefficient cEQ and the signal value dEQ performed under the control of the filter processing control unit 402 will be described. 7, cEQ is a filter coefficient cEQxy (x = 0 to 2, y = 0 to 4) used in the multiplication processes 921 to 936 of the 3-band equalizer shown in FIG. 10, and dEQ is used in the multiplication processes 921 to 936. The signal value dEQxy (x = 0 to 2, y = 0 to 4) is represented.

  The filter processing control unit 402 causes the data path unit 100 to execute only the “upper calculation” process shown in FIG. 7 in the single precision operation state EQx (x = 0 to 2). For example, in the case of causing the data path unit 100 to calculate the signal value dEQ10 of the above equation (1) in the single precision operation state EQ0, the filter processing control unit 402 writes the initial value 0 in the register 113. Next, the filter processing control unit 402 causes the multiplier 111 to supply the filter coefficient cEX00 in the coefficient storage unit 200 and the upper N bits of the signal value dEQ00 in the work RAM 120 to the multiplier 111 via the selectors 131 and 132, respectively. To do. Thereby, the multiplier 111 outputs 2N-bit data indicating the multiplication result cEQ00 × dEQ00. The filter processing control unit 402 sign-extends the 2N-bit data to 2N + M-bit data, and causes the adder 112 and the register 113 to perform accumulation.

Next, the filter processing control unit 402 causes the multiplier 111 to supply the filter coefficient cEX01 in the coefficient storage unit 200 and the upper N bits of the signal value dEQ01 in the work RAM 120 to the multiplier 111 via the selectors 131 and 132, respectively. And the adder 112 and the register 113 are caused to accumulate the multiplication result cEQ01 × dEQ01. The filter processing control unit 402 causes the data path unit 100 to perform each of the multiplication processes cEQ02 × dEQ02, cEQ03 × dEQ10, and cEQ04 × dEQ11 in Equation (1) and the accumulation in the same procedure. As a result, 2N + M-bit data indicating the signal value dEQ10 of the above equation (1) is obtained in the register 113. The filter processing control unit 402 stores data consisting of the upper N bits of the 2N + M bit data and the lower N bits which are all 0s in the first operation result storage area in the work RAM 120 as the signal value dEQ10. Although the aspect of the multiplication and addition process in the single precision arithmetic state EQ0 has been described above, the arithmetic processes of the above formulas (2) and (3) are executed in the same manner also in the single precision arithmetic states EQ1 and EQ2.
The above is the aspect of the calculation of the filter processing executed in the non-worst case.

  On the other hand, in the double precision operation state BIEQx (x = 0 to 2), the filter processing control unit 402 divides the signal value dEQ into upper N bits and lower N bits (both including a sign bit), and the same multiplier 111. Next, the multiplication process of the coefficient cEQ and the lower bit of the signal value dEQ (“lower calculation” in FIG. 7) and the multiplication process of the coefficient cEQ and the higher bit of the signal value dEQ (“upper calculation” in FIG. 7) are sequentially performed. And the multiplication process is performed with an operation accuracy that is double the operation accuracy corresponding to the bit width N of the multiplier 111. The operation of the double precision operation state BIEQ0 will be described as an example as follows.

First, the filter processing control unit 402 writes an initial value 0 in the register 113. Next, the filter processing control unit 402 causes the multiplier 111 to supply the N-bit filter coefficient cEX00 in the coefficient storage unit 200 via the selector 131. Further, the filter processing control unit 402 causes the multiplier 111 to supply the lower N bits of the 2N bit signal value dEQ00 in the work RAM 120 via the selector 132. Then, the multiplier 111 is caused to perform multiplication processing of the filter coefficient cEX00 and the lower N bits of the signal value dEQ00. Thereby, the multiplier 111 outputs 2N-bit data indicating the multiplication result. Next, the filter processing control unit 402 performs sign extension of the multiplication result to generate a 2N + M-bit signal value, and provides the 2N + M-bit signal value to the accumulator including the adder 112 and the register 113. Let the accumulation occur. As a result, 2N + M bits of data indicating the multiplication result of the filter coefficient cEX00 and the lower N bits of the signal value dEQ00 are stored in the register 113. Before executing “upper calculation”, the data in the register 113 is shifted to the lower bit side by N−1 bits to obtain the original 1/2 ^N−1 times data.

Next, the filter processing control unit 402 causes the data path unit 100 to execute “upper calculation” as follows. First, the filter processing control unit 402 causes the multiplier 111 to supply the N-bit filter coefficient cEX00 in the coefficient storage unit 200 via the selector 131. Further, the filter processing control unit 402 causes the multiplier 111 to supply the upper N bits of the 2N bit signal value dEQ00 in the work RAM 120 via the selector 132. Then, the multiplier 111 is caused to multiply the filter coefficient cEX00 by the upper N bits of the signal value dEQ00. Thereby, the multiplier 111 outputs 2N-bit data indicating the multiplication result. Next, the filter processing control unit 402 performs sign extension of the multiplication result to generate a 2N + M-bit signal value, and provides the 2N + M-bit signal value to the accumulator including the adder 112 and the register 113. Let the accumulation occur. As a result, data obtained by adding the multiplication result of the filter coefficient cEX00 and the lower N bits of the signal value dEQ00 and the multiplication result of the filter coefficient cEX00 and the upper N bits of the signal value dEQ00 in the register 113, that is, double precision A multiplication result of the filter coefficient cEX00 and the signal value dEQ00 by calculation is obtained. In the same manner, the multiplication processes shown in the above equation (13) and their accumulation processes are performed. Then, the output signal value dEQ10 of the equalizer EQ0 obtained in the register 113 is stored in the first calculation result storage area in the work RAM 120.
Although the aspect of the multiplication and addition process in the double precision arithmetic state BIEQ0 has been described above, the arithmetic processes of the above formulas (14) and (15) are executed in the same manner in the double precision arithmetic states BIEQ1 and BIEQ2.
The above is the aspect of the filter processing operation executed in the worst case.

  As described above, according to the present embodiment, based on the filter coefficient, it is determined whether the execution condition of the digital filter is a worst case that requires high calculation accuracy or a non-worst case that does not, and a common calculation is performed. Using the device 110, the filtering process is executed by a double precision calculation in the worst case and by a single precision calculation with low power consumption in the non-worst case. Therefore, both the worst case filtering process and the non-worst case filtering process can be executed without increasing the hardware scale and generating unnecessary power consumption. Further, in the present embodiment, when the filter processing as the three-band equalizer includes each filter processing as a smaller equalizer EQx (x = 0 to 2), each of the small-scale filter processing is individually performed. Since the execution condition is determined to be the worst case or non-worst case, and the calculation accuracy is selected, it is possible to perform as much filter processing as possible by single-precision calculation, and it has the advantage that fine power saving is possible. is there.

<Second Embodiment>
FIG. 8 is a diagram showing a mode of multiplication and addition processing of the filter coefficient cEQ and the signal value dEQ in the digital filter according to the second embodiment of the present invention. In the first embodiment, when the filter coefficient cEQ is N bits, the signal value dEQ is 2N bits, and the filter process is performed by double precision calculation, the signal value dEQ is divided into upper N bits and lower N bits, and the coefficient cEQ The multiplication process of the latter and the coefficient cEQ and the former are sequentially executed, and the multiplication results are accumulated. On the other hand, in the present embodiment, the filter coefficient cEQ is 2N bits, the signal value dEQ is N bits, and the number of bits of the filter coefficient cEQ used for multiplication with the signal value dEQ is switched, so that single precision calculation / double precision is achieved. Switch computations.

  When the filter process is performed by single precision calculation, only the “upper calculation” shown in FIG. 8 is executed. That is, the multiplication of the upper N bits of the filter coefficient cEQ and the signal value dEQ is performed by the multiplier 111, the multiplication result is sign-extended, and the result is accumulated by the accumulator including the adder 112 and the register 113.

  When the above processing is executed for each combination of the filter coefficient cEQxy and the signal value dEQxy in Equation (1), 2N + M-bit data indicating the signal value dEQ10 is obtained in the register 113. The filter processing control unit 402 stores the upper N bits of this data in the first calculation result storage area in the work RAM 120 as the signal value dEQ10. The operation of calculating the signal values dEQ20 and dEQ30 shown in the above equations (2) and (3) is basically the same.

On the other hand, when the filter processing is performed by double precision calculation, “lower calculation” and “upper calculation” shown in FIG. 8 are sequentially executed. First, the multiplication of the lower N bits of the filter coefficient cEQ and the signal value dEQ is performed by the multiplier 111, the multiplication result is sign-extended, and the result is accumulated by an accumulator including an adder 112 and a register 113. Prior to “upper calculation”, the data in the register 113 is shifted to the lower bit side by N−1 bits to obtain the original 1/2 ^N−1 data. Next, the multiplication of the upper N bits of the filter coefficient cEQ and the signal value dEQ is performed by the multiplier 111, the multiplication result is sign-extended, and the result is accumulated by the accumulator including the adder 112 and the register 113.

  When the above processing is executed for each combination of the filter coefficient cEQxy and the signal value dEQxy in Equation (1), 2N + M-bit data indicating the signal value dEQ10 is obtained in the register 113. The filter processing control unit 402 stores the upper N bits of this data in the first calculation result storage area in the work RAM 120 as the signal value dEQ10. The operation of calculating the signal values dEQ20 and dEQ30 shown in the above equations (2) and (3) is basically the same.

  Also in the present embodiment, since switching between single-precision arithmetic / double-precision arithmetic is performed depending on whether the execution condition of the filter processing is a non-worst case or a worst case, the non-worst case is achieved without increasing the hardware scale. Filter processing can be performed in cases and worst cases, and wasteful power consumption can be avoided in non-worst cases.

<Third Embodiment>
FIG. 9 is a state transition diagram showing the operation of the filter processing control unit 402 (see FIG. 1) in the digital filter according to the third embodiment of the present invention. In the first embodiment, for each of the equalizers EQx (x = 0 to 2), it is determined whether the execution condition of the filter processing is a non-worst case or the worst case, and the calculation accuracy is selected for each equalizer. On the other hand, in the present embodiment, the calculation accuracy is collectively switched for all the processes of the equalizer EQx (x = 0 to x).

  More specifically, the filter processing control unit 402 refers to the filter coefficient cEQx1 (x = 0 to 2) in the coefficient storage unit 200 at the start of the sampling period. When all of the filter coefficients cEQx1 (x = 0 to 2) are equal to or greater than -1.99, the state is subsequently shifted to single-precision calculation states EQ0, EQ1, and EQ2 and the equalizer EQx is obtained by single-precision calculation. The filter processing (x = 0 to 2) is executed. On the other hand, if at least one of the filter coefficients cEQx1 (x = 0 to 2) is less than −1.99, the state is subsequently changed to the double-precision operation states BIEQ0, BIEQ1, and BIEQ2, and the equalizer is obtained by the double-precision operation. The filter process of EQx (x = 0 to 2) is executed.

  Also in the present embodiment, the non-worst case and the worst case filter processing can be executed without increasing the hardware scale, and wasteful power consumption can be avoided in the non-worst case. Further, unlike the first embodiment, the present embodiment does not switch individual calculation accuracy for each of the equalizers EQx (x = 0 to x), and thus cannot perform fine power saving. However, there is an advantage that the control is simple compared with the first embodiment.

<Other embodiments>
As mentioned above, although each embodiment of this invention was described, this invention can have other embodiment besides this. For example:

(1) In the above-described embodiment, the execution condition of the filter processing is divided into two stages, the non-worst case and the worst case, and the single precision operation or the double precision operation is selected depending on which execution condition belongs to. However, the execution conditions of the filter processing may be divided into three or more stages, and the calculation accuracy may be increased as the execution conditions become stricter, such as double precision calculation, triple precision calculation, and so on.

(2) In the above embodiment, the filter coefficient is used as a parameter indicating the execution condition of the filter processing. However, when the digital filter can obtain the peak frequency f0, gain G, queue Q, etc. of the filter processing from the outside. Based on these parameters, the execution condition of the filter process (non-worst case / worst case) may be determined, and the calculation accuracy may be selected.

(3) The digital filter is provided with an automatic mode and a manual mode that can be set by an external operation, and in the manual mode, for example, an equalizer EQx (x = 0 to 2) according to a command input via the interface 300 In the automatic mode, the calculation accuracy is switched based on a parameter (filter coefficient in the first embodiment) indicating the execution condition of the filter processing as in the first embodiment. Control may be performed.

It is a block diagram which shows the structure of the digital filter which is 1st Embodiment of this invention. It is a figure which shows the relationship between the peak frequency of the equalizer handled by the embodiment, and a filter coefficient. It is a figure which shows the validity of the threshold value of the filter coefficient for determining whether the execution condition of a filter process is a non-worst case or a worst case in the same embodiment. It is a state transition diagram showing the operation of the filter processing control unit in the same embodiment. It is a time chart which shows the operation example of the embodiment. It is a time chart which shows the other operation example of the embodiment. It is a figure which shows the aspect of the multiplication addition process of the filter coefficient and signal value in the embodiment. It is a figure which shows the aspect of the multiplication addition process of the filter coefficient and signal value which are performed in the digital filter by 2nd Embodiment of this invention. It is a state transition diagram which shows operation | movement of the filter process control part of the digital filter by 3rd Embodiment of this invention. It is a block diagram which shows the function structure of the digital filter which operate | moves as a 3-bid equalizer. It is the figure which showed typically the filter characteristic of one equalizer in the same 3 band equalizer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Data path part, 200 ... Coefficient memory | storage part, 300 ... Interface, 400 ... Control part, 401 ... Coefficient rewrite control part, 402 ... Filter process control part, 110 ... Calculator, 111 ... Multiplier 112... Adder 113. Register 131, 132.

Claims (6)

Coefficient storage means for storing a filter coefficient to be multiplied by a signal to be processed for filter processing or a filter coefficient to be multiplied to a signal generated in the process of the filter processing;
Coefficient rewrite control means for rewriting the filter coefficient stored in the coefficient storage means;
A calculation means for performing a calculation for applying a filter process using the filter coefficient stored in the coefficient storage means to the signal to be processed;
A filter for controlling the calculation by the calculation means, and for controlling the calculation accuracy of the calculation by the calculation means by changing a usage mode of the calculation means based on a parameter indicating an execution condition of the filter processing. And a processing control means.   2. The digital according to claim 1, wherein the control unit performs switching control of the calculation accuracy using a filter coefficient stored in the coefficient storage unit as a parameter indicating an execution condition of the filter process. filter.   The filter processing control unit causes the calculation unit to perform double precision calculation when the execution condition of the filter processing indicated by the parameter is the worst case that requires the highest calculation accuracy, and performs the filter processing indicated by the parameter. 3. The digital filter according to claim 1, wherein when the execution condition is a non-worst case, the arithmetic unit performs single-precision arithmetic.   The filter processing is composed of a plurality of smaller filter processes, and the filter processing control unit is individually configured so as to ensure the calculation accuracy required for each small filter processing unit. The digital filter according to any one of claims 1 to 3, wherein control for switching calculation accuracy is performed.   The filter processing includes a plurality of smaller filter processes, and the filter processing control means ensures the highest calculation accuracy among the calculation accuracy required by the plurality of small filter processes. 4. The digital filter according to claim 1, wherein calculation accuracy switching control is collectively performed for the plurality of small-scale filter processes. 5.   There are a manual mode and an automatic mode that can be set by an external operation. In the manual mode, the calculation accuracy is switched according to an external operation. In the automatic mode, the execution condition of the filter process is set. 6. The digital filter according to claim 1, wherein switching control of accuracy of the arithmetic processing is performed based on a parameter indicated.

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