JP3523104B2 - Fixed-point multiplier / adder - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed point type multiplier / adder formed in a semiconductor integrated circuit, and more particularly to a data feedback loop to a multiplication circuit, for example, a digital signal processor (DS) for digital audio equipment.
P) is used.

[0002]

2. Description of the Related Art Generally, in a fixed-point type multiplier / adder incorporated in a DSP, as a representation format of data having a decimal point, (1) the decimal point position is set to the lower side of the least significant bit of the data and is expressed as an integer. The handling method and (1) a method of setting the decimal point position to the upper side of the most significant bit of data and handling it as a pure decimal number (a real number without an integer part) is known. Currently, the latter method is used. Is overwhelmingly adopted.

FIG. 5 shows an example of a conventional fixed point type power adder.

In FIG. 5, IN is input data, Y is coefficient input data (multiplicand data), 51 is a selector for selectively outputting the input data IN and feedback input data described later, and 52 is a selective output of the selector 51. , 53 is a multiplication circuit for multiplying the multiplier data X read from the data storage device 52 by the multiplicand data Y, and 54 is a multiplication output of the multiplication circuit 53 as one addition input. An adder circuit 55 is a register for temporarily holding the addition output of the addition circuit 54 and using it as the other addition input of the addition circuit 54. A reference numeral 56 is one input terminal of the selector 51 for using the addition output of the addition circuit 54. This is a shifter that allows the signal to be passed through as it is when it is fed back to, and shifts a predetermined number of bits when the added output is finally output as a calculation result.

The structure and operation of this fixed-point type multiplier / adder are well known, and although a detailed description thereof is omitted here, a minute signal which changes only the lower several bits of the input data IN is input. If the coefficient of the coefficient input data Y is small, or if the product-sum operation with feedback with a large operation error is applied, a digit loss occurs during the operation and the operation result including the error is output. To be done.

Therefore, when the calculation is repeated using this calculation result, since the calculation is performed between the numerical values including the error, the calculation result including many errors is finally output, and the calculation accuracy is increased. Is reduced.

That is, in the DSP having the fixed-point type multiplier / adder shown in FIG. 5, the bit length of the data that can be handled internally is limited, and the operation result of the lower bit of the input data IN is truncated in the middle. There will be a calculation error, so
The calculation precision is determined by the bit length of the data that can be handled internally.

The hardware configuration of the multiplication circuit 53 in FIG. 5 can basically be configured by one AND gate per bit. The hardware configuration of the adder circuit 54 in FIG. 5 can be configured by one full adder per bit.

On the other hand, in the floating point type multiply adder,
Even when handling the same bit length as the fixed-point type power adder, the mantissa can always be treated as a pure decimal,
If the mantissa part and the exponent part are provided with a sufficient number of bits, the rounding error due to the calculation can be reduced, and the calculation accuracy is significantly improved. However, the floating-point type multiply-adder has a complicated and large-scale hardware and becomes more complicated in processing.

That is, as shown in FIG. 6 (a), the hardware configuration of the multiplication circuit in the floating-point type multiply-adder is as follows.
An adder circuit 61 for exponent part calculation, a multiplication circuit 62 for mantissa part calculation, and a normalization circuit 63 for normalizing the addition result are required.

As shown in FIG. 6B, the hardware configuration of the adder circuit in the floating-point type power adder is as follows.
A comparator 65 for comparing the magnitudes of the exponents, a digit matching circuit 66 for the operands, an adder 67, and a normalization circuit 68 for normalizing the addition result are required.

On the other hand, FIG. 7 shows a conventional IIR (Infinite Impulse r) to which the fixed-point type multiply-adder shown in FIG. 5 is applied.
An example of an esponse (infinite impulse response) type LPF (low pass filter) is shown.

In FIG. 7, the input signal IN has a coefficient a0.
Is input to the first coefficient circuit 711 and is stored in the first register 721. This first register 72
The output of 1 is input to the second coefficient circuit 712 having the coefficient a1 and stored in the second register 722. The output of the second register 722 is input to the third coefficient circuit 713 having the coefficient a2. These first coefficient circuits 711,
The outputs of the second coefficient circuit 712 and the third coefficient circuit 713 are input to the first addition circuit 731 and added.

The output of the first adder circuit 731 is input to the second adder circuit 732. This second adder circuit 73
The output of 2 is stored in the third register 723.
The output of the register 723 is input to the fourth coefficient circuit 714 having the coefficient b1 and stored in the fourth register 724. The output of the fourth register 724 is input to the fifth coefficient circuit 715 having the coefficient b2. The outputs of the fourth coefficient circuit 714 and the fifth coefficient circuit 715 are fed back and input to the second adder circuit 732 to output the first coefficient.
Is added together with the output of the adder circuit 731. And
The output of the second adding circuit 732 is taken out as the output signal OUT.

In the IIR type LPF, an input signal shifted by one sample period is input to a first adder circuit 731, cumulative addition is performed to obtain a moving average, and the output signal of the first adder circuit 731 is fed back. The signal is added to the second adder circuit 732.
The order of the filter is reduced by inputting the signal to the input terminal and cumulative addition is performed, so that the characteristics in the region of the cutoff frequency fc are sharpened. In this case, in order to lower the cutoff frequency fc, the coefficients a1, a2, b1 and b2 are set small.

By the way, the operation precision of the DSP for the current digital audio equipment can usually be sufficiently dealt with by using a fixed-point type multiply-adder as shown in FIG. Device shown in FIG.
When applied to an IR type LPF, the calculation accuracy may become insufficient in some calculations (the calculation part that repeats the product-sum calculation in which feedback is applied).

On the other hand, DSP for digital audio equipment
If you use a floating-point type multiply-adder for, the hardware configuration becomes redundant, even if the calculation accuracy is sufficient.
The cost of digital audio equipment increases.

Here, the cutoff frequency fc is set to 50 Hz, for example.
Regarding the impulse response characteristic of the second-order IIR type LPF set to, the calculation result when a 24-bit fixed point type power adder is used is shown by the solid line in FIG. 8. The calculation result when the adder is used is shown by the dotted line in FIG.

From the characteristics shown in FIG. 8, it is apparent that in the IIR type LPF, the arithmetic precision when using the fixed point type power adder is inferior to the arithmetic precision when using the floating point type power adder. Is.

[0020]

As described above, the conventional fixed-point type multiply-adder has a simple hardware configuration, but since the calculation precision is determined by the bit length of the data that can be handled internally, a minute signal is input. However, there is a problem that the calculation accuracy is lowered when the coefficient of the coefficient input data is small, or when the product-sum calculation in which feedback with a large calculation error is applied is performed.

The present invention has been made to solve the above problems, and fixed-point type multiplication / addition which can improve the arithmetic precision to the level of a floating-point type multiplication / adder without increasing the hardware configuration. The purpose is to provide a container.

[0022]

A first fixed-point type multiply-adder according to the present invention includes an input selection selector for selecting and outputting either input data or feedback input data, and the input selection selector. A multiplication circuit that multiplies the multiplier data that is the selection output of the selector and the multiplicand data that is the coefficient input data, an addition circuit that has the multiplication output of the multiplication circuit as one addition input, and an addition output of the addition circuit that is temporarily A data holding circuit for holding the same as the other addition input of the addition circuit, a left bit shift circuit for selectively bit-shifting the addition output of the addition circuit to the upper side, and output data of the left bit shift circuit. A data storage device for returning written data and read data to one input terminal of the selector , wherein the left bit shift circuit is the addition circuit.
Add the desired head margin to the number of bits of the addition output of
Characterized in that it have a number of bits.

[0023]

A second fixed point type power adder of the present invention is
The first fixed-point type power adder comprises a control circuit for automatically controlling the left bit shift amount of the left bit shift circuit based on the head margin of the left bit shift circuit and the value of the multiplicand data. Is characterized by.

A third fixed point type power adder of the present invention is
In the first or second fixed-point type power adder, the left bit shift amount data is written together with the output data of the left bit shift circuit in the data storage device, and the data is output when the operation result is finally output. The addition output of the addition circuit is controlled to bit shift to the lower side based on the left bit shift amount data read from the storage device.

A fourth fixed point type power adder of the present invention is
In a third fixed point type power adder, a selector for inputting the output of the adder circuit and selecting the left bit shift circuit as one of the output destinations, and a selector for selecting the output destination And a right bit shift circuit which shifts the output of the selector for selecting the output destination to the lower side based on the left bit shift amount data read from the data storage device. Is characterized by.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a fixed-point type multiply-adder according to a first embodiment of the present invention.

The fixed-point type multiplier-adder shown in FIG. 1 has an input selection selector 11 for selecting and outputting either the input data IN or the feedback input data F, and a selection output of the input selection selector 11. A multiplication circuit 12 that multiplies certain multiplier data X and multiplicand data Y that is coefficient input data.
And an addition circuit 13 in which the multiplication output of the multiplication circuit 12 is one addition input, and a data holding that temporarily holds the addition output data Z of the addition circuit 13 and uses it as the other addition input of the addition circuit 13. A circuit (register) 14, a left bit shift circuit 15 for selectively bit-shifting to the upper side when the addition output Z of the addition circuit 13 is input, and output data of the left bit shift circuit 15 are stored, And a data storage device 16 for returning read data to one input terminal of the input selection selector 11.

The hardware structure of the multiplication circuit 12 can be basically composed of one AND gate per bit. The hardware configuration of the adder circuit 13 can be configured by one full adder per bit.

Further, a control circuit 17 for controlling the bit shift amount of the left bit shift circuit 15 is provided. This control circuit 17 stores a control program for the bit shift amount in, for example, a ROM table or an encoder with a priority function. Stored in.

The control circuit 17 controls the left bit shift circuit 15 to perform bit shift in the case of high precision fixed point type operation, and in the case of normal fixed point type operation, the left bit shift circuit. Pass the data through without 15 bit shifting.

The data storage device 16 is, for example, a DRA.
A register such as M is used to write the output data of the left bit shift circuit 15 and the data representing the left bit shift amount. At this time, in the case of a normal fixed-point type operation, the bit shift amount in the left bit shift circuit 15 is zero.

Further, in this example, the selector 18 for selecting the output destination to which the addition output Z of the adder circuit 13 is input, and the data supplied from the selector 18 for selecting the output destination are bit-shifted to the lower side. A bit shift circuit 19 is provided.

In this case, the selector 1 for selecting the output destination
8 selects the left bit shift circuit 15 as the output destination of the addition output Z until the operation finally ends, and the right bit as the output destination of the addition output Z after the operation finally ends. The shift circuit 19 is selected.

The left bit shift circuit 15 adds the desired number of bits of the addition output Z of the adder circuit 13 with a desired sufficient head margin (determined according to the application of the fixed point type power adder). In response to this, the right bit shift circuit 19 also has a bit number obtained by adding a desired sufficient head margin to the bit number of the addition output Z of the addition circuit 13.

Further, the adder circuit 13 and the data holding circuit 14 are provided with a sufficient head margin so as to be able to cope with the overflow due to the bit shift of the left bit shift circuit 15 in the case of high precision fixed point type operation. ing.

Next, the operation of the fixed-point type multiply-adder having the above configuration will be described.

When performing a normal fixed-point type operation,
The multiplication operation by the multiplication circuit 12, the cumulative addition operation by the addition circuit 13 and the data holding circuit 14, the left bit shift circuit 15, the data storage device 16, the input selection selector 11
The product-sum operation is performed by the operation of the data feedback loop including the.

In this case, data is passed through the left bit shift circuit 15, and the output data (actual data) of the left bit shift circuit 15 is written in the data storage device 16. After the operation is completed, the result (addition output Z) after the product-sum operation is limited by the right bit shift circuit 19 to the bit length of the output bus and is output as the final operation result. During this series of operations, data is always represented in fixed point.

On the other hand, when performing high precision fixed-point arithmetic, the left bit shift circuit 15 is operated during the operation of the feedback loop, as compared with the case of the normal fixed-point arithmetic.
, The left bit shift operation is performed to the extent that the most significant bit does not overflow (to the extent that it does not peak), and the adder circuit
3 and the data holding circuit 14 are different in that processing corresponding to overflow is performed.

This left bit shift operation is equivalent to multiplying the data several times (for example, shifting 1 bit changes the data by 2).
Equivalent to doubling). Then, the data storage device 16
Is written with the output data of the left bit shift circuit 15 and the data representing the left bit shift amount, and can be regarded as storing the same data as the mantissa part and exponent part of the floating point type operation. By such an operation, a pseudo floating point type operation is performed.

After the operation is completed, the result (addition output Z) after the product-sum operation is the bit shift amount data stored in the data storage device 16 and the adder circuit 13.
Right bit shift circuit 19 based on the overflow in
After right bit shifting (corresponding to division) is performed to return to the original digit, the bit length of the output bus is limited and the final operation result is output.

That is, according to the fixed point type multiply-adder according to the first embodiment, the left bit shift circuit 15 is provided in the product-sum operation feedback loop including the data storage device 16.
It is characterized in that the digit of the data to be fed back by the addition output Z is shifted to the upper side before the operation, and the digit of the addition output Z is shifted to the lower side after the operation and returned to the original position to be taken out.

As a result, it is possible to control the operation result of the lower bit of the input data IN so that it is not truncated in the middle, so that the scale of the hardware configuration is not significantly increased, and a floating point type multiply-adder is used. The calculation accuracy of is obtained.

Therefore, according to the DSP for the digital audio equipment which incorporates the fixed point type multiplier / adder,
Even if there is a limit to the bit length of the data that can be handled internally,
Calculation accuracy is greatly improved.

<Modification of First Embodiment> The selector 18 for selecting the output destination in the first embodiment is omitted,
The addition output Z may be supplied to both the left bit shift circuit 15 and the right bit shift circuit 19, and the output of the right bit shift circuit 19 may be captured at the output destination when the final operation result is output.

<Example of Application of First Embodiment> FIG. 2 shows an example of an IIR type LPF to which the fixed point type multiplier / adder of FIG. 1 is applied.

In FIG. 2, the input signal IN has a coefficient a0.
Is input to the first coefficient circuit 211 and is stored in the first register 221. This first register 22
The output of 1 is input to the second coefficient circuit 212 having the coefficient a1 and stored in the second register 222. The output of the second register 222 is input to the third coefficient circuit 213 having the coefficient a2. These first coefficient circuits 211,
The outputs of the second coefficient circuit 212 and the third coefficient circuit 213 are input to the first addition circuit 231 and added.

The output of the first adder circuit 231 is input to the second adder circuit 232 via the left bit shift circuit 24. The output of the second adder circuit 232 (output signal O
UT) is stored in the third register 223, and the output of the third register 223 is the fourth coefficient circuit 2 having the coefficient b1.
The data is input to 14 and stored in the fourth register 224. The output of the fourth register 224 is input to the fifth coefficient circuit 215 having the coefficient b2. The outputs of the fourth coefficient circuit 214 and the fifth coefficient circuit 215 are fed back and input to the second adder circuit 232 and added together with the output of the first adder circuit 231. The output of the second adder circuit 232 is the right bit shift circuit 25.
Is output as an output signal OUT.

Further, each of the registers 221 to 224,
A bit shift control circuit 2 for controlling the bit shift amounts of the left bit shift circuit 24 and the right bit shift circuit 25.
6 is provided.

According to the IR type LPF of FIG. 2, since the fixed-point type multiply-adder of FIG. 1 is used in the operation part for repeating the multiply-accumulate operation with feedback, in order to lower the cutoff frequency fc. Even when the coefficients a1, a2, b1 and b2 are set to be small (when a calculation error is likely to occur), the bit shift amount is controlled to be large, whereby sufficient calculation accuracy can be obtained.

<Second Embodiment> In the first embodiment, the most significant bit is set as the left bit shift amount (data lifting amount) of the left bit shift circuit 15 controlled by the program of the control circuit 17. Was fixed so that it would not overflow.

However, since the left bit shift amount in the left bit shift circuit 15 affects the calculation accuracy, the calculation precision becomes higher if the left bit shift amount is increased as long as the head margin of the left bit shift circuit 15 allows.

Here, the secondary IIR type L shown in FIG.
In the PF, the cutoff frequency fc is set to 100 Hz, for example, and the result of calculation of the impulse response characteristics when the bit shift amount n is changed from 1 to 8 is shown in FIG.
To (h).

From the characteristics shown in FIGS. 3 (a) to 3 (h), it can be seen that if the head margin of the left bit shift circuit 15 is sufficient, the filter characteristic can be greatly improved by increasing the bit shift amount n. .

Considering this point, a second embodiment for realizing a fixed-point type multiply-adder suitable for a case where higher calculation accuracy is required depending on the application will be described below.

FIG. 4 shows a fixed point type power adder according to a second embodiment of the present invention. Compared with the fixed-point type power adder described above with reference to FIG. 1, the fixed-point type power adder shown in FIG. 1 is the same as that in FIG. 1 except that a bit shift amount determination device 40 for automatically determining a large value) and controlling the bit shift amount is added. .

That is, the bit shift amount determination device 40
Determines the largest left bit shift amount as long as the head margin allows, in consideration of the head margin of the left bit shift circuit 15 based on the calculation result and the value of the multiplicand input data Y, and the bit of the feedback data is determined according to the determination result. It has the function of controlling the shift amount.

According to such a configuration, the influence of the calculation error accumulated in the middle of the calculation is minimized, and the high-precision calculation equivalent to that of the floating-point type multiply-adder is always performed.

That is, according to the fixed-point type multiply-adder according to the second embodiment, the same effect as that of the fixed-point type multiply-adder according to the first embodiment can be obtained, and the arithmetic operation can be performed. Since the bit shift amount determining device 40 for automatically determining the optimal bit shift amount of the feedback data according to the above is provided, by controlling the bit shift amount of the feedback data according to the determination result, the multiplicand data Y Regardless of the value, it is possible to realize a highly accurate operation equivalent to a floating point type power adder.

Therefore, if the fixed-point type multiplier-adder shown in FIG. 4 is applied to the quadratic IIR type LPF shown in FIG. 2, the optimum value of the bit shift amount of the feedback data (maximum as much as possible) is calculated according to the operation. Since the value) can be controlled automatically, the filter characteristics can be significantly improved.

In each of the above embodiments, the right bit shift of the right bit shift circuit 19 is controlled based on the bit shift amount data held in the data storage device 16 when the operation result is finally output. However, not limited to this, the control circuit 17 in FIG. 1 or the bit shift amount determination device 40 in FIG. 4 may control the right bit shift of the right bit shift circuit 19.

[0064]

As described above, according to the present invention, it is possible to provide a fixed-point type multiply-adder capable of improving the calculation accuracy without increasing the hardware configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fixed point type power adder according to a first embodiment of the present invention.

FIG. 2 is an IIR to which the fixed-point type power adder of FIG. 1 is applied.
The block diagram which shows an example of a type LPF.

3 is a characteristic diagram showing a result of calculation of impulse response characteristics when the bit shift amount n is changed from 1 to 8 in the secondary IIR type LPF shown in FIG.

FIG. 4 is a block diagram showing a fixed point type power adder according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional fixed-point type power adder.

FIG. 6 is a block diagram showing an example of a multiplication circuit and an addition circuit of a conventional floating-point type power adder.

7 is a block diagram showing an example of a conventional IIR type LPF to which the fixed-point type power adder of FIG. 5 is applied.

FIG. 8 shows a cutoff frequency fc of a secondary IIR type LPF of 5
Impulse response characteristics when set to 0 Hz 24
FIG. 6 is a characteristic diagram showing the result of the operation using the bit fixed point type power adder and the result of the operation using the floating point type power adder.

[Explanation of symbols]

IN ... input data, F ... Feedback input data, X ... Multiplier input data, Y: coefficient input (multiplicand input) data, Z ... Addition output data, 11 ... Selector for input selection, 12 ... Multiplier circuit, 13 ... Adder circuit, 14 ... Data holding circuit, 15 ... Left bit shift circuit, 16 ... Data storage device, 17 ... control circuit, 18 ... Selector for selecting output destination, 19 ... Right bit shift circuit.

─────────────────────────────────────────────────── --Continued from the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 7/02 G06F 7/52 310

Claims (4)

(57) [Claims] 1. A selector for input selection which selects and outputs either input data or feedback input data, and multiplication of multiplier data which is a selected output of the selector for input selection and multiplicand data which is coefficient input data. And a data holding circuit for temporarily holding the addition output of the addition circuit and using it as the other addition input of the addition circuit. A left bit shift circuit for selectively bit-shifting the added output of the adder circuit to the upper side, and a data storage in which output data of the left bit shift circuit is written and read data is fed back to one input end of the selector. And a left bit shift circuit comprising:
Is the desired head for the number of bits of the addition output of the adding circuit.
Fixed-point multiplication and addition circuit, characterized in that have a number of bits obtained by adding a margin. 2. The fixed-point type multiplier / adder according to claim 1, wherein the head margin of the left bit shift circuit and the multiplicand
Based on the value of the data, the left bit of the left bit shift circuit is
A fixed-point type power adder comprising a control circuit for automatically controlling the shift amount . 3. The fixed-point type multiply-adder according to claim 1, wherein the left bit shift circuit is provided with the output data of the left bit shift circuit.
Write the shift amount data to the data storage device,
When finally outputting the calculation result, the data storage device
Based on the left bit shift amount data read from
Bit-shift the addition output of the addition circuit to the lower side.
A fixed-point type multiply-adder characterized by the following control . 4. The fixed-point type power adder according to claim 3 , wherein the addition output of the addition circuit is input, and one of the output destinations is input.
For selecting an output destination for selecting the left bit shift circuit
The other of the selector and the output destination of the selector for selecting the output destination,
The left bit shift amount data read from the data storage device.
The output of the selector for selecting the output destination based on the
The right bit shift circuit that shifts the bits to
A fixed-point type multiply-adder characterized in that