JP3137131B2 - Floating point multiplier and multiplication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a passive-point multiplier and a multiplication method, and more particularly, to an addition of exponents of a multiplier and a multiplicand expressed in a binary floating-point and a subtraction of a bias value. The present invention relates to a floating-point multiplier and a multiplication method for performing a carry process on a calculation result based on a calculation result regarding a mantissa.

[0002] A floating point multiplier and a multiplication method according to the present invention correspond to, for example, two or more accuracies in the IEEE 754-1985 standard. In the IEEE standard, three types of numerical expressions of precision, single precision, double precision, and extended double precision, are defined, and each exponent has a width of 8, 11, or 15 bits.

In the expression based on the IEEE standard, the exponent uses a number X = x + B obtained by adding a constant B as a bias to an actual value x for calculation. Specifically, it is defined as shown in Table 1.

[0004]

[Table 1] In the case of an exponent operation in the operation, the exponent z of the product and the exponents X and Y of the multiplier / multiplicand have the following relationship. (Operations in [] may be performed based on the result of mantissa operation) Actually, an operation such as an expression is performed in the multiplier.

[0005]

2. Description of the Related Art Conventionally, there has been an arithmetic unit relating to an exponent part of a floating-point multiplier as shown in FIG. As this operation apparatus shown in the drawing, single, double, an arithmetic unit capable of performing the calculation of the exponent in the double-extended three precision and single precision for exponent arithmetic unit 53 ₁ , those having a double-precision for exponent arithmetic unit 53 _2, and double extended precision for exponent arithmetic unit 53 _3, and selecting means 50 for these, to select one of three types of arithmetic unit by an instruction . Each of the arithmetic units 53 ₁ , 53 ₂ , and 53 ₃ has exponent arithmetic means 51 ₁ , 51 for performing addition of exponents of multipliers and multiplicands represented by binary floating-point numbers and subtracting bias values. _2, 51 ₃ and, for calculation results on the exponent part by the exponent part calculation unit, post-processing unit 5 for processing the carry on the basis of the calculation results for the mantissa
21 ₁ , 52 ₂ , and 52 ₃ respectively.

[0006] The exponent calculation means of each calculation device has a calculation capability such as a digit width corresponding to each precision. That is, in the case of single precision, the digit width of 8 bits, in the case of double precision, the digit width of 11 bits, and in the case of extended double precision,
With a digit width of 15 bits and corresponding to each precision,
Different bias values are used.

[0007]

By the way, as described above, in the conventional floating point multiplier,
In the case of a multiplier capable of multiplying a plurality of precisions, a separate arithmetic unit for exponent operation is provided for each precision. This is not only because the required digit width differs for each precision, but also because the bias value B varies depending on the precision as shown in Table 1. Therefore, in the conventional example, in a floating-point multiplier capable of multiplying a plurality of precisions, a separate arithmetic unit is required for each precision in order to realize the operation of the expression, and the number of parts is reduced. There is a problem that it leads to an increase in production cost, an increase in production time, and an increase in size of the apparatus.

Therefore, the present invention enables floating-point multiplication in accordance with a plurality of precisions, which leads to an increase in the number of parts, an increase in production cost, an increase in production time, and an increase in the size of the apparatus. The purpose of the present invention is to provide a floating-point multiplier and a multiplication method that cannot be connected.

[0009]

In order to solve the above technical problem, a first invention is to add an exponent part of a multiplier and a multiplicand represented by a binary floating point as shown in FIG. , And an exponent part operation means 10 for adding the complement of the bias value, a mantissa part multiplication circuit for multiplying the mantissa parts of the multiplier and the multiplicand, and a mantissa part multiplication operation result of the exponent part by the exponent part operation means 10. And a post-processing means for performing carry-out processing based on the result of the operation concerning the mantissa by the circuit. The exponent part calculating means and the post-processing means correspond to high precision among at least two kinds of precision. When performing low-precision calculations while performing calculations and processing using the specified digit width and bias value, the digits from the upper digits to the digits corresponding to the low-precision digits in the digit widths corresponding to the high precision are used. Is represented with low precision Pre-processing means 30a and 30b for supplying the exponent part to the exponent part calculation means 10 as the exponent part of the multiplier or the multiplicand by merging the exponent parts assigned to 1 and the remaining digits. .

The addition of the exponents of the multiplier and the multiplicand represented by the binary floating-point number and the addition of the complement of the bias value are performed (S2), and the multiplication of the mantissa of the multiplier and the multiplicand is performed. performs processing carry on the basis of the calculation results for parts (S3), the addition of the exponent portions of the multiplier and multiplicand, processing complement addition and carry the bias value, the at least two types of precision, high When performing low-precision calculations while performing calculations with the digit width and bias value corresponding to the precision, before performing addition of the exponent parts of the multiplier and the multiplicand and addition of the complement of the bias value (S2), In the digit widths corresponding to, the exponent part represented with low precision is assigned to the digits from the high-order digit to the digit width corresponding to low precision, and 1 is assigned to each of the remaining digits and merged. Exponent of multiplier or multiplicand (S1) is intended.

[0011]

When multiplication with at least two types of precision is possible, if multiplication with low precision is instructed, the exponent part and the mantissa part of the floating-point multiplier and multiplicand to be multiplied are given. And the exponents of the multiplier and the multiplicand are input to the pre-processing means 30a and 30b, respectively. Here, when the multiplicand and the multiplier are expressed by a binary floating point, they become Q _X · 2 ^X and Q _Y · 2 ^Y , respectively, and Q _X and Q _Y are called mantissa parts of the multiplicand and the multiplier, and the widths X and Y of 2 Are referred to as the multiplicand and the exponent of the multiplier. When the multiplication is performed between the multiplicand and the multiplier, the product is (Q _X · Q _Y ) · 2 ^{X + Y} ,
The present invention relates to the calculation of the exponent.

In step S1, the pre-processing means 30
“a” and “30b” are assigned the exponent part represented by the original low precision to the low-precision digit width from the high-order digit in the digit width corresponding to the high precision among the at least two types of precision, and Is assigned to 1 and then merged. The merged data is
This is a mode corresponding to a high-precision calculation among two types of precision.

For the sake of simplicity, it is assumed that two types of precision can be selected. Among them, a long digit width corresponding to high precision is L bits, and a short digit width corresponding to low precision is S (<L). The processing of the pre-processing units 30a and 30b will be described as bits (L and S are natural numbers). That is, the two exponents X = (X ₀ ... X _S-1 ) of the input multiplicand and multiplier.
For Y = (Y ₀ ... Y _S-1 ), the pre-processing means 30a,
30b outputs the following L-bit numbers X 'and Y'. _{X '= (X 0 ··· X} S-1 1 ... 1) Y' = (Y 0 ··· Y S-1 1 ... 1)

In step S2, the exponent part operation means 1
With the addition of 0, the exponent parts X ′ and Y ′ are added, and then the bias value B is subtracted. That is, Z ′ = X ′ +
Y′-B is obtained. Here, the exponent part calculating means 10
Has a calculation capability corresponding to high precision, and the bias value B is set to a value 2 ^L−1 −1 corresponding to high precision. By the way, the bias value B = 2 ^L−1 −1 = (011... 11)
Is subtracted from the two's complement of B−B = (100... 0
This is the same as adding 1). Therefore, the following operation is performed. Here, when the relation of Z ′ with the upper S bits Z = (Z ₀ ... Z _S−1 ) is obtained, Z ′ = X ′ + Y′−B, that is, the left side = Z · 2 ^LS + 1 · 2 ^{LS -1} + ... + 1 - 2 ⁰ right ^{= X · 2 LS +1 · 2} LS-1 + ... + 1 · 2 0 + Y · 2 LS +1 · 2 LS-1 + ... + 1 · 2 0 +2 L-1 +1

[0015] by dividing both sides by 2 ^LS, when set equal, Z + 1/2 + ... + 1/2 LS = X + Y + 2 · (1/2 + ... + 1/2 LS) +1/2 LS +2 S-1 is obtained, When further deformed, Z = X + Y + 2 ^S−1 + 1 = X + Y− (2 ^S−1 −1). This equation corresponds to the processing to be performed in the case of low precision (addition and subtraction of the low precision bias value).

In step S3, when there is an instruction from the mantissa by the post-processing means 20, the incremented number A 'is obtained as follows. Here, a short digit A = from the upper digit of A ′ to the S bit
(A _O・ ・ ・ A _S-1 ) The exponent part calculation means 10 and the post-processing means 20 have the same formula as that of the low precision case, and have high precision capability.
Can be used to perform a low-precision exponent operation. Incidentally, when the calculation of the exponent part is performed with high accuracy, the pre-processing means 30 is no different from the conventional case.
a and 30b merely output the input exponent part as it is.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A floating point multiplier and a multiplying method according to an embodiment of the present invention will be described. FIG. 3 is an overall view of the floating-point multiplier according to the present embodiment. As shown in the figure, the present multiplier performs addition of exponent parts of a multiplier and a multiplicand represented by a floating point number in a binary system, and a bias value B.
An exponent part operation circuit 1 that is an adder for performing subtraction of the exponent part, and a post-processing circuit 2 that performs a carry process on the operation result of the exponent part by the exponent part operation circuit 1 based on the operation result of the mantissa part. The exponent part operation circuit 1 and the post-processing circuit 2 perform operations and processes with a digit width and a bias value corresponding to high accuracy among at least two types of accuracy. Further, in the present embodiment, when performing low-precision arithmetic, the exponent part represented by the original low precision is used in the high-precision digit width from the upper digit to the low-precision digit width. Pre-processing circuits 3a and 3b to be supplied to the exponent part operation circuit 1 are provided as an exponent part of a multiplier or a multiplicand by merging the numbers to which "1" is assigned to each of the remaining digits.

Further, as shown in the figure, the post-processing circuit 2 holds registers 21 and 22 for holding the operation result of the exponent part operation circuit 1 and adjusting timing, and the exponent part operation circuit 1 It has a carry circuit 23 for carrying a calculation result on the exponent part, and a multiplexer 24 for selecting whether to carry or not to carry based on the result of the mantissa operation.

In addition, in the present embodiment, as shown in the figure, aligning circuits 4a and 4b for switching between an exponent part and a mantissa part according to the precision mode, and a register for temporarily holding the multiplier and multiplicand of the mantissa part. 5a, 5b, a mantissa multiplying circuit 6 for multiplying the mantissa, a register 7 for holding the product of the mantissa, a normalizing circuit 8 for rounding and normalizing the multiplication result of the mantissa, a multiplier or multiplicand Check units 9 and 91 for checking the operands of the above, a register 92 for holding a status signal indicating the state of the check result,
A generation unit 93 for generating a special operation result such as）, NAN, etc. (non-numeric value), a multiplexer 94, a register 95 for holding a product as a final result of multiplication, and an EXCP
(Exception signal, four types of exception notification are defined in the case of the IEEE standard).

In this embodiment, for the sake of simplicity, I
Selection of single precision (low precision) / double precision (high precision) of EEE standard
A description will be given of a floating-point multiplier which can be selected. Where
The digit width (bit width) in the case of degrees is 8 bits, and the bias value
B is 2 ⁷It is -1. The digit width for double precision is 1
With one bit, the bias value B is 2 ^Ten-1 but
The exponent part arithmetic circuit 1 and the like have a digit width (11 bits) in the case of double precision.
And the bias value B are 2^Ten-1 is provided.
FIG. 4 illustrates the operation of the exponent part in the multiplier according to the present embodiment.
These parts are extracted and shown.

As shown in FIG.
Signals a and 3b are provided with 11 bits which is a digit width corresponding to double precision based on the IEEE standard, and 8 bits which is a digit width corresponding to single precision from the most significant digit are signals for directly outputting input data. , And the signal lines for the remaining digit width of 3 bits are OR elements 31a, 32a, 33a... Provided in the respective pre-processing circuits 3a, 3b. 31b, 32
b, 33b, and a signal line (+ SEL) for instructing switching between the single precision mode and the double precision mode is provided to the other terminal of the OR element. SNG) are connected, and the output signal lines for each 3 bits of each OR element 31a and the like are combined with the 8-bit signal lines for single precision, and each is input to the exponent part operation circuit 1. . Here, switching between the single precision mode and the double precision mode is performed by + SEL
This is done by switching the SNG between "1" and "0" respectively.

Next, the operation relating to the operation of the exponent part in the floating-point multiplier according to the present embodiment will be described.
When performing multiplication in the single precision mode, the alignment circuit 4
The multiplicand and the multiplier are divided into a mantissa part and an exponent part according to a and 4b.
8 bits left-justified from the most significant digit of the 1-bit long digit width
The bits are input to the pre-processing circuits 3a and 3b. X = (X ₀ ... X ₇ ) and Y = (Y ₀ ... Y ₇ ) represent two 8-bit exponents of the input multiplicand and multiplier. When there is an instruction for multiplication in the single precision mode, the OR elements 31a, 32a, 3
+ SEL connected to one terminal of 3a, 31b, 32b, 33b The SNG signal line goes to "1" state.

Therefore, the pre-processing circuits 3a and 3b
Of the 11-bit digit width, 8
The exponent data sent from the aligning circuits 4a and 4b is stored in the bits, and the OR elements 31a, 32a, 33a, 31b, 32b and 32b are written in the remaining three bits.
An 11-bit number X ', as shown below, in which the data to which "111" data output from 3b is allocated is merged.
Y ′ is output (L = 11, S = 8 in the case described above). X ′ = (X ₀ ... X ₇ 111) Y ′ = (Y ₀ ... Y ₇ 111) The X ′ and Y ′ are input to the exponent part operation circuit 1. In the arithmetic circuit 1, data Z '= X' + Y '-(2 ¹⁰ -1) is obtained by adding the two input data and subtracting the bias value B = 2 ¹⁰ -1 in the case of double precision. .

At this time, the double-precision bias value B = (01)
111111111) is subtracted from the 2's complement of B-
This is the same as adding B = (1000000001). Therefore, the following operation is performed in the operation circuit 1. Here, the upper 8 bits Z = (Z ₀ ... Z ₇ ) of Z ′ are Z = X + Y− (2 ⁷ −1). That is, as described above, 2 ⁷ −
1 corresponds to the single-precision bias value B, and the expression yields the same result as the expression to be calculated in the single-precision case.

In the post-processing circuit 2, if there is a carry instruction based on the result of the mantissa operation, the operation result (Z _C Z ₀ ... Z ₇ 111) obtained by the exponent operation circuit 1 is added to the result. 1 will be added. As a result, A 'is obtained as follows. Here, the upper 8 bits of A 'A = (A _O ... A ₇ )
Is Becomes This corresponds to the expression for the case of single precision.

On the other hand, when the operation of the exponent part is performed in double precision, the same operation as in the conventional example is performed, and the pre-processing circuits 3a and 3b add the 11-bit exponent part to the alignment circuits 4a and 4a. 4b, the signal line of one terminal of the OR element + SEL “0” is set in SNG, and the input data is directly input to the exponent part operation circuit 1 and normal processing is performed, which is no different from the conventional one.

In the above description, two types of cases, single precision and double precision, have been described. However, the present invention is not limited to this case.
The highest accuracy may be applied as the high accuracy described above, and the accuracy other than the highest accuracy may be applied as the low accuracy. Further, although the case of the positive logic is shown in the circuit of FIG. 4, the circuit may be configured by the negative logic. In that case, a NOR element may be used instead of the OR element.

[0028]

As described above, according to the present invention, when calculating the exponent part of the multiplier and the multiplicand, when performing low-precision calculation of at least two precisions,
Of the digit widths required for high precision, exponents represented with low precision are assigned to digits from the upper digit to the digit width required for low precision, and "1" is assigned to each of the remaining digits. The assigned ones are merged and operated as the exponent part of the multiplier or the multiplicand. Therefore, it is possible to perform floating-point multiplication of the plurality of precision in a common circuit, increase in the number of components, increase in the manufacturing operation costs, and does not cause an increase in the size of the apparatus. Further, according to the present invention, in the case of a low-precision operation, "1" is assigned to each of the remaining lower digits of the required digit width, so that after the process based on the carry from the mantissa, The operation of the exponent part is not required, and the number of operation steps can be reduced and the operation speed can be improved. Further, in the present invention, the arithmetic operation between the mantissa parts of the multiplier and the multiplicand is performed in parallel with the addition of the exponent parts and the addition of the complement of the bias value, so that the processing time of the multiplication is reduced. Can be

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the first invention.

FIG. 2 is a flowchart of the principle of the second invention.

FIG. 3 is an overall block diagram of a multiplier according to the embodiment;

FIG. 4 is a block diagram of a device related to an operation of an exponent part of the multiplier according to the embodiment;

FIG. 5 is a block diagram according to a conventional example.

[Explanation of symbols]

 10 (1) Exponent part operation means (exponent part operation circuit) 20 (2) Post-processing means (post-processing circuit) 30a, 30b Pre-processing means (pre-processing circuit)

Claims (2)

(57) [Claims] 1. A sum of the multiplier and multiplicand exponent portions of the expressed in floating-point binary, and the exponent calculation means for adding the complement of the bias value, the exponent portions by the exponent part arithmetic means Addition and before
A mantissa multiplying circuit for multiplying the mantissas of the multiplier and the multiplicand in parallel with the addition of the complement of the bias value; And a post-processing means for performing a carry process based on the result. The exponent part calculating means and the post-processing means have a digit width corresponding to high precision among at least two kinds of precision, and have high precision.
When performing the calculation of , the calculation and processing with the digit width and bias value corresponding to high precision are performed, and when performing the calculation of low precision, the higher digit of the digit width corresponding to high precision is calculated. Digits up to the low-precision digit width are assigned low-precision exponents, and each remaining digit is 1
Merges those assigned as exponent of the multiplier or the multiplicand, floating-point multiplier, characterized in that a pre-processing means for supplying to said exponent calculation means. 2. A floating-adder of the multiplier and the exponent portions of the multiplicand represented by several points binary, and in parallel with the addition of the complement of the bias value, multiplies between the mantissa of the multiplier and multiplicand, the Carry-out processing is performed based on the result of mantissa operation. Addition of exponents of multipliers and multiplicands, addition of complements of bias values, and carry-over processing correspond to high precision among at least two types of precision. With a high precision performance.
When performing the arithmetic, the digit width and the bias value corresponding to the high precision are used, and when performing the low precision arithmetic, the addition of the exponent parts of the multiplier and the multiplicand and the addition of the complement of the bias value are performed. before,
Of the digit widths corresponding to high precision, the exponent part represented with low precision is assigned to the digits from the upper digit to the digit width corresponding to low precision, and 1 is assigned to each of the remaining digits. floating number <br/> point multiplication method characterized by the exponent of the multiplier or the multiplicand by.