JP2002108606A - Sticky bit generating circuit and multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further enhance multiplication speed by shortening time to be taken in a rounding processing by speeding up a processing of generation of sticky bit. SOLUTION: The sticky bit is directly generated from the sum of partial products of a carry save format before calculating a multiplication result. Specifically, since inversion G, exclusive logical OR P and logical AND G of logical OR by every bit corresponding to sum components and carry components of the partial products of the carry save format are calculated, the virtual sum in consideration of the adjacent high-order bits and carry propagation of the respective bits is calculated and the sticky bit is generated by taking the entire logical OR, the sticky bit is generated at high speed without the propagation of carry.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit, and more particularly to a sticky bit generation circuit for generating a sticky bit which is an auxiliary bit for reducing a calculation error and using the sticky bit generation circuit. Related to a multiplier.

[0002]

2. Description of the Related Art Hitherto, various configurations of a high-speed multiplier for use in a computer have been proposed. In such a high-speed multiplier, basically, a partial product corresponding to each bit of the multiplier is obtained, and a product is obtained by adding a plurality of partial products shifted left by one bit. In order to increase the speed, a method to reduce the number of partial products and reduce the addition work by finding partial products corresponding to multiple bits of the multiplier, such as Booth's algorithm, etc. There are known a method of adding in parallel "Walath's method", a method of adding partial products using a carry-save adder, and the like. Many high-speed multipliers use these techniques, and the sum of the partial products is obtained by a carry component, a carry save form of the sum component, and the carry propagation addition is performed only once at the end. The above is an integer multiplication method, but it is also used when generating a mantissa at a floating point.

FIG. 4 shows a configuration example of a typical conventional floating point multiplier. The 52-bit operand S and the 52-bit operand T are input to the multiplier 201, where they are multiplied to obtain a 105-bit sum component SS of the partial product and a 105-bit carry component CC. The sum component SS and the carry component CC of these partial products are added by the adder 202 to obtain a final multiplication result. The sticky bit generation circuit 203 generates a sticky bit by taking the logical sum of the shift bits of the obtained multiplication result,
It is passed to the rounding circuit 204.

A rounding circuit 204 determines whether or not the result of the multiplication is to be rounded based on the sticky bit. When the rounding is performed, an addition value 1 is supplied to an adder 205. The output value of the adder 205 is input to a selection circuit (multiplexer) 206,
Here, the result of the final multiplication is selected depending on whether or not the one shifted by one bit and the one not shifted overflow.

When multiplying in a floating point multiplier configuration, the product often must round the result to a defined number of bits in a particular format. For example, the standard for double-precision binary numbers is 53 bits [1 bit for the integer part, 52 bits after the decimal point].

[0006] The product of two 53-bit binary numbers is 106 bits long. However, the double precision result uses only the upper 54 bits of the product. Here, the most significant bit indicates overflow. The lower 53 bits are used only for determining whether a carry is generated from the lower bits, whether or not rounding is necessary, and further, a rounding value is determined, and the value itself is discarded.

[0007]

By the way, in order to round the above-mentioned product, first, the mantissa must be normalized. In a multiplier that multiplies two normalized operands S and T, this may cause a one-bit shift of the mantissa to the right. Until the mantissa is normalized, the bit position at which rounding is performed is not determined. As a result, the worst case, the carry from the lowest order is propagated to the highest order, the normalization is performed by the highest order result, and the rounding position and the position of the bit necessary for determining whether or not the rounding process is performed are determined. You usually have to wait for

Accordingly, the carry from the lower bit is included in the critical path. In such a multiplier, the adder 202 normally adds the carry component and the sum component of the product [1], and performs [2] normalization and [3] sticky bit generation in the circuit 203. Using this result, [4] rounding is determined by the circuit 204 and [5]
Typically, the result is generated by a procedure in which the rounding increment is performed by the adder 205.

However, in such a configuration, it is necessary to perform the final addition by the adder 202 before the generation of the sticky bit, and this addition takes time and
The logical sum of all the shift bits must be taken for the sticky bit generation, and it takes time to generate the sticky bit, and a series of rounding processes takes time.
Therefore, the speed of the multiplier is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to increase the speed of sticky bit generation to reduce the time required for rounding, thereby increasing the multiplication speed. And a floating-point multiplier using the sticky bit generation circuit.

[0011]

In order to achieve the above object, a feature of the present invention is to provide a multiplying means for multiplying two normalized operands, and a sum component of partial products obtained from the multiplying means. PKG generating means for generating an inverted KB (stop of carry propagation), an exclusive OR P (propagate of carry), and a logical product G (generate of carry) from the lower bit of the carry component and the lower bit of the carry component, A sticky bit generation means for generating a sticky bit from the inverted KB obtained by the PKG generation means, the exclusive OR P, and the logical product G is provided.

The sticky bit generating means according to the second aspect of the present invention is configured to calculate an exclusive OR P, a logical product G, and an inverted KB of a corresponding bit of the sum component and the carry component and an upper bit adjacent thereto. After a signal indicating that the bit does not become 1 is obtained, a sticky bit is generated by calculating the total logical sum of the signal indicating that each bit does not become 1.

According to a third aspect of the present invention, the PKG generating means calculates each of the exclusive OR P, the logical product G, and the inverted KB by operating on a bit slice, and the sticky bit generating means generates a plurality of blocks of sticky bits. It is characterized in that it is obtained by dividing into two.

According to a fourth aspect of the present invention, there is provided a multiplying means for multiplying two normalized operands, and inverting a logical sum from a lower bit of a sum component of the partial products and a lower bit of a carry component obtained from the multiplying means. KB (stop carry propagation),
PKG generating means for generating exclusive OR P (carry propagation) and logical product G (generating carry), and a sticky bit based on the inverted KB, exclusive OR P, and logical product G obtained by the PKG generating means , A first adding means for adding an upper bit of the sum component of the partial products obtained from the multiplying means and an upper bit of the carry component, and a sticky bit generated by the sticky bit generating means. Determining means for determining whether or not to perform rounding on the multiplication result;
The inverted KB obtained by the G generation means, the exclusive OR P,
Carry generating means for generating a carry from the logical product G;
While adding the carry generated by the carry generation means to the multiplication result obtained from the first addition means,
A second adding means for adding 1 when the rounding processing is determined to be performed by the determining means.
A feature of the invention of claim 5 is that the addition processing by the first addition means and the processing of the PKG generation means and the sticky bit generation means are performed in parallel.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the multiplier of the present invention. The multiplication circuit 1
Multiplication circuit 1 for inputting and multiplying normalized operands S and T
And the upper bits of the sum component SS and carry component CC output from the multiplication circuit 1 to add two operands S
(52: 0) multiplied by operand T (52: 0), adder circuit 2 for calculating the result of multiplication, inverted KB of logical sum (stop of carry propagation), exclusive OR P (propagation of carry), logical product G ( A PKG generation circuit 3 for generating a carry, a sticky bit generation circuit 4 for generating a sticky bit 100, a carry generation circuit 5 for generating a carry,
A rounding circuit 6 for determining whether or not to round the multiplication result;
It has an adder circuit 7 for rounding or adding a carry to the multiplication result, and a selection circuit (multiplexer) 8 for selecting whether the result of the multiplication result is shifted by one bit or not and overflows.

FIG. 2 is a circuit diagram showing a configuration example of the PKG generation circuit 3. The PKG generation circuit 3 includes an exclusive OR circuit, an OR circuit, and an AND circuit.

The exclusive OR circuit receives the operation result SS of the multiplication circuit 1 and each bit of CC as input and generates a signal P indicating propagation of carry in the corresponding bit. The signal PB in the figure is the inverse of P.

The OR circuit similarly calculates the operation result SS,
, And CC, and generates a signal K indicating the disappearance of the carry in the corresponding bit. The signal KB in the figure indicates the inversion of K.

The AND circuit similarly calculates the operation result SS,
, And CC, and generates a signal G indicating generation of a carry in the corresponding bit.

FIG. 3 shows a sticky bit generation circuit 4
FIG. 3 is a circuit diagram showing a configuration example of FIG.

The sticky bit generation circuit 4 comprises an exclusive OR circuit of the constituent members 103, 105, 107 and 109 and a logical OR circuit of the constituent members 104, 106, 108 and 110. This circuit receives the output of the PKG generation circuit, the inverted KB signal, and the P signal as inputs and generates a sticky signal. Note that the operation is a bit slice.

In this embodiment, the lower order S of the double precision multiplication result
Although S <50: 0> and CC <50: 0> are divided into four fields for each bit in the order in which the operation result is obtained, the operation result does not change even if the operation is performed at once. By performing division as in the present embodiment, calculation can be performed from the portion where the multiplication result is obtained, so that the generation of sticky bits can be performed at a higher speed than performed at once.

Next, the operation of this embodiment will be described. The multiplication circuit 1 multiplies the normalized operands S and T,
It outputs a sum component SS of partial products and a carry component CC. Assuming that the sum of partial products is generated in a carry-save form and is double-precision, the sum component SS (105:
0) and carry component CC (105: 0). The upper bits of the sum component SS and the carry component CC are input to the addition circuit 2, and the lower bits are input to the PKG generation circuit 3.

The PKG generating circuit 3 receives as input the sum component SS (50: 0) and the carry component CC (50: 0) of the partial products in the carry save format, and inverts the KB of the logical sum for each corresponding bit. An exclusive OR P and a logical product G are obtained by a bit slice. The inverted KB of the logical sum, the exclusive logical sum P, and the logical product G are passed to the sticky bit generation circuit 4, and the sticky bit generation circuit 4 outputs the inverted logical sum K.
B, an exclusive OR P, and a logical product G, to generate a sticky bit 100, and the resulting sticky bit 1
00 is output to the rounding circuit 6.

The sticky bit generation circuit 4 generates sticky bits in stages based on the carry information of each input bit. Sticky bit generation circuit 4
Is provided with a plurality of XOR logic gates and a plurality of OR gates.
To determine whether or not 1 is set in each bit, and OR the signals indicating whether or not 1 is set in each bit to generate a sticky bit 100. Since the sticky bit generation circuit 4 does not perform the addition in the process of generating the carry as described above, the carry is not propagated and the sticky bit can be obtained at high speed.

Here, in the present embodiment, the sticky bit is obtained by dividing it into four blocks. This is because the multiplying arrays are added by the Wallace method. The partial sum of the partial products is determined in order from the lower part. In this example, since a double-precision multiplication array is configured, four bits of SS (3: 0, CC (3: 0)) and SS (1
1: 4), 8 bits of CC (11: 4), SS (25:
15), 14 bits of CC (25:15), remaining SS
(105: 26), CC (105: 26) is determined step by step.

In the present system, the sticky bit may be obtained by calculating the logical sum of the operation result performed in the bit slice, and the calculation may be started from any bit. In general, the process of calculating the logical sum of multi-bits needs to be performed stepwise in a tree structure, and is essentially a time-consuming process. In order to further speed up the generation of the sticky bit, in this example, the generation of the sticky bit is performed stepwise from the determined partial product.

The rounding circuit 6 determines whether or not to perform rounding based on the input sticky bits, and outputs an addition value “1” to the adding circuit 7 when performing rounding. The addition circuit 7 adds "1" to the multiplication result of the addition circuit 2 only when performing rounding and performs rounding. In other cases, the addition circuit 7 outputs the multiplication result as it is to the selection circuit 8. In addition, carry generation circuit 5
Receives the sum component SS (50: 0) of partial products and the carry component CC (50: 0) of the carry save format, finds the lower carry C51 of the partial product, and adds the found carry to the adder circuit 7. Send to Thereby, the addition circuit 7
In, the carry is added to the multiplication result input from the addition circuit 2 to obtain a correct multiplication result.

The selection circuit 8 selects whether or not the result of the multiplication is shifted by 1 bit and whether or not it overflows, and outputs the final multiplication result.

According to the present embodiment, the P, K, and G signals are generated from the sum component SS and the carry component CC of the partial products of the multiplication circuit 1, and the sticky bit 100 is formed by bit slice from the P, K, and G signals. By performing the calculation, there is no carry propagation, and the sticky bit 100 is generated at high speed by performing the process of obtaining the sticky bit 100 in parallel with the addition process of the sum component SS and the carry component CC of the partial products by the adding circuit 2. can do. As a result, the time for obtaining the multiplication result can be shortened, and the multiplication speed of the circuit can be improved.

The present invention is not limited to the above-described embodiment, and may be embodied in various other forms in terms of specific structure, function, operation, and effect without departing from the gist of the invention. .

[0032]

As described above in detail, according to the present invention, in the sticky bit generation circuit in the floating point arithmetic unit, the sum component of the partial product of the carry save format before the multiplication result is obtained and Invert G of exclusive OR of corresponding bit of carry component, exclusive OR P,
The multiplication speed is further improved by obtaining the logical product G and obtaining the sticky bits from the obtained P, K, and G signals, thereby speeding up the process of generating the sticky bits and shortening the time required for the rounding process. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multiplier according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a PKG generation circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration example of a sticky bit generation circuit shown in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a conventional floating-point multiplier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplication circuit 2, 7 Addition circuit 3 PKG generation circuit 4 Sticky bit generation circuit 5 Carry generation circuit 6 Rounding circuit 8 Selection circuit

Claims (5)

[Claims] 1. Multiplying means for multiplying two normalized operands, and inverting a logical sum from the lower bit of the sum component and the lower bit of the carry component of the partial product obtained from the multiplying unit (stop of carry propagation) PKG generating means for generating exclusive OR P (carry propagation) and logical product G (generating carry); and sticky from inverted KB, exclusive OR P, and logical product G obtained by the PKG generating means. A sticky bit generation circuit, comprising: sticky bit generation means for generating bits. 2. The sticky bit generation means determines whether the bit of the exclusive component P, the logical product G, and the inverted KB of the corresponding bit of the sum component and the carry component and its adjacent upper bit is 1 2. The sticky bit generation circuit according to claim 1, wherein a sticky bit is generated by obtaining a signal indicating that each bit does not become 1 after obtaining a signal indicating that each bit does not become 1. 3. The PKG generating means calculates each of the exclusive OR P, the logical product G, and the inverted KB by operating on a bit slice, and the sticky bit generating means divides the sticky bit into a plurality of blocks. 3. The sticky bit generation circuit according to claim 1, wherein the value is obtained. 4. Multiplying means for multiplying two normalized operands, and inverting the logical sum from the lower bit of the sum component and the lower bit of the carry component of the partial product obtained from the multiplying means KB (stop of carry propagation) PKG generating means for generating exclusive OR P (carry propagation) and logical product G (generating carry); and sticky from inverted KB, exclusive OR P, and logical product G obtained by the PKG generating means. Sticky bit generation means for generating bits; first addition means for adding the high order bit of the sum component of the partial products obtained from the multiplication means and the high order bit of the carry component; and sticky generated by the sticky bit generation means. Determining means for determining whether or not to perform a rounding process on the multiplication result based on the bits; ORs P, a carry generating means for generating a carry from the logical product G, as well as adding the carry generated from said carry generating means is multiplied results obtained from said first addition means,
A second adding means for adding 1 when it is determined that the rounding processing is to be performed by the determining means. 5. The multiplier according to claim 4, wherein the addition processing by said first addition means and the processing of said PKG generation means and sticky bit generation means are performed in parallel.