JP2010011493A - Digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce memory capacity for storing tap coefficients in a digital filter, including a plurality of multipliers for multiplying the tap coefficients, respectively, and an adder for adding multiplied outputs. <P>SOLUTION: This digital filter includes: a plurality of tap compatible multipliers; an adder for adding the multiplied outputs of the multipliers; and memories storing a plurality of kinds of tap compatible tap coefficients corresponding to filter properties, and makes a filter waveform into a symmetrical wave to a center tap, wherein the memories are a plurality of taps corresponding memories collectively storing tap coefficients corresponding to the plurality of kinds of filter properties, respectively, to be compatible with taps, and store the tap coefficients in such a pattern that a pattern stored with tap coefficients which shifts the filter waveform in the positive direction or the negative direction to a center tap, is turned up to the upper and the lower or the right and left sides about a center tap position and a tap coefficient position of 0 shift of the filter waveform. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital filter whose filter characteristics can be switched.

  The digital filter includes a plurality of cascaded multipliers and an adder that adds the multiplication outputs. The multiplier has a configuration in which tap coefficients corresponding to filter characteristics are input and multiplied by input data. For example, in the case of a 5-tap configuration, as shown in a simplified manner in FIG. 6, five multipliers 11 are connected in cascade, and input data Din is sequentially passed through the previous multiplier 11 to the next multiplier 11. Are input after being delayed, and the multiplication output of each multiplier 11 is added by the adder 12, and the input data Din is output as filtered output data Dout. Taps (Tap1 to Tap5) input to the multiplier 11 Corresponding tap coefficients are set in the register 13. Further, for example, the filter coefficients corresponding to the patterns 1 to 4 are held in the memory 14 so that the filter characteristics can be switched, and the filter coefficients read from the memory 14 are set in the register 13 when the filter characteristics are switched.

  The filter coefficient storage memory 14 holds filter coefficients corresponding to filter characteristic patterns 1 to 4 as shown in FIG. 7, for example, and has a maximum number of tap coefficients, for example, a 16-bit configuration. In the memory configuration, tap coefficients corresponding to patterns 1 to 4 are held at addresses 0x00 to 0x13, respectively. In this case, the tap coefficients of the center taps of taps (Tap) 1 to 5 are configured in 16 bits, tap coefficients of taps 2 and 4 are configured in 6 bits, taps 1 and 5 are configured in 3 bits, and each tap coefficient is stored. The memory to be used has a storage capacity of 16 bits × 20 words. In the following description, the filter coefficient indicates a coefficient corresponding to the filter characteristic patterns 1 to 4, and the tap coefficient indicates a coefficient set in a register corresponding to the multiplier 11.

  FIG. 8A shows a flowchart of a conventional example when switching filter characteristics, and FIG. 8B shows a sequence chart. It is necessary to update the filter coefficients when switching the filter characteristics by simultaneously setting the respective tap coefficients for all the taps. Therefore, in FIG. ), The filter coefficients are sequentially read by read access to the memory 14 (12), and the read filter coefficients are temporarily buffered (13). In FIG. 6, a buffer for this buffering is not shown. Then, it is determined whether or not buffering for all taps is completed (14), that is, it is determined whether or not reading of tap coefficients for updating is completed for all taps. The filter coefficient update is instructed (15), the buffered tap coefficient corresponding to the multiplier 11 is set in the register 13, and the filter coefficient update process is terminated (16).

  In FIG. 8B, the read access to the memory 14 is started by the control input for updating the filter coefficient, and the addresses of the tap (Tap) 1 to tap (Tap) 5 are sequentially input to the memory 14, and the filter The coefficients are read sequentially, and the filter coefficients are held in the buffer. By instructing the filter to update the filter coefficient upon completion of buffering of the filter coefficients of all the taps 1 to 5, the filter starts the filter process using the new filter coefficient.

  Also, multiple storage areas that can be read by common address input can be selected by external signals, filter coefficients with different filter characteristics are stored in each storage area, and the filter coefficients read from the selected storage area are summed A digital filter is known in which a desired filter characteristic can be selected by inputting to a signal processing circuit including an arithmetic circuit (see, for example, Patent Document 1).

  In addition, in the FIR type digital filter that performs sampling rate conversion, a coefficient memory holding a plurality of tap coefficients is provided for each tap corresponding to a plurality of multipliers, and the coefficient memory is sequentially shifted by one tap for each tap. A digital filter that reads a tap coefficient and inputs it to a multiplier is known (see, for example, Patent Document 2).

JP-A-60-244111 JP-A-4-68708

  In the conventional example in which the filter characteristics can be switched, for example, a filter coefficient storage memory as shown in FIG. 7 is used, and a memory having a maximum bit number such as a center tap is used. Therefore, there is a problem that a useless area exists for a tap coefficient with a small number of bits. In addition, there is a problem that it takes time to sequentially read tap coefficients by the number of taps. Further, when switching the filter characteristics, it is necessary to make the tap coefficients effective at the same timing, so that there is a problem that a buffer for buffering the tap coefficients read sequentially until all taps are read out is required. .

  The conventional example shown in Patent Document 1 in which a plurality of storage areas are accessed by a common read address and different filter coefficients are selected and input to a product-sum operation circuit by inputting an external signal for selecting the storage area. However, since it is necessary to use a memory having the maximum bit width regardless of the bit configuration of the filter coefficient, there is a problem that a useless storage area is included as described above. In the conventional example shown in Patent Document 2 in which a coefficient memory is provided for each tap, buffering of tap coefficients is not necessary. However, when the tap coefficient has a different bit configuration, a wasteful storage area is used. There is a problem that will include. Therefore, it has been difficult to reduce the required area when an integrated circuit including a multiplier and an adder for performing a filter operation is included.

  An object of the present invention is to solve the problems of the conventional example described above, and to eliminate the need for a buffering configuration for setting tap coefficients and to reduce the storage capacity of a memory for storing filter coefficients. .

  The digital filter of the present invention includes a plurality of tap-compatible multipliers, an adder that adds the multiplication outputs of the multipliers, and a memory that stores a plurality of tap-corresponding tap coefficients corresponding to filter characteristics. A digital filter having a filter waveform symmetrical with respect to a center tap, wherein the memory is a plurality of tap correspondence memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in a tap correspondence manner. A pattern storing tap coefficients for shifting the filter waveform in the + direction or-direction with respect to the center tap is folded up and down or left and right around the center tap position and the tap coefficient position of 0 shift of the filter waveform. The tap coefficient is stored in a predetermined pattern.

  Further, the memory is a plurality of tap corresponding memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in correspondence with the taps, and the filter waveform is shifted in the + direction or the − direction with respect to the center tap. The tap coefficient is stored in a pattern in which the tap coefficient is stored as a pattern folded back to the left and right around the center tap position and the tap coefficient position of the 0 shift of the filter waveform. Is inverted with respect to the array of tap coefficients which is not omitted, and is set in the register corresponding to the multiplier.

  Further, the memory is a plurality of tap corresponding memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in correspondence with the taps, and the filter waveform is shifted in the + direction or the − direction with respect to the center tap. The tap coefficient is stored in a pattern in which the tap coefficient is stored in a pattern that is folded up and down around the tap coefficient position of the 0 shift of the filter waveform at the center tap position. Is inverted with respect to the array of tap coefficients which is not omitted, and is set in the register corresponding to the multiplier.

  The tap corresponding memory has a storage area according to the bit configuration of the tap coefficient corresponding to the tap, so there is no need to provide an extra storage area, and the filter waveform is the target waveform for the center tap, and By storing the tap coefficient for the pattern folded at the center tap position, the circuit scale can be reduced. The tap-compatible memory can simultaneously read out the tap coefficient corresponding to the filter characteristic by the same address and set it in the register corresponding to the multiplier, and it is not necessary to provide a buffer for buffering. It is possible to speed up the switching.

It is explanatory drawing of the filter coefficient storage memory of Example 1 of this invention. It is the flowchart and sequence chart of Example 1 of this invention. It is characteristic explanatory drawing of the digital delay filter of Example 2 of this invention. It is explanatory drawing of a tap corresponding | compatible memory. It is explanatory drawing of a tap corresponding | compatible memory. It is explanatory drawing of the digital filter shown simplified. It is explanatory drawing of the filter coefficient storage memory of a prior art example. It is the flowchart and sequence chart of filter coefficient update of a prior art example.

  The digital filter of the present invention includes a plurality of tap-capable multipliers, an adder that adds the multiplication outputs of the multipliers, and a memory that stores a plurality of tap-corresponding tap coefficients corresponding to filter characteristics, A digital filter having a filter waveform symmetric with respect to a center tap, wherein the memory is a plurality of tap corresponding memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in a tap-compatible manner, and the center. A pattern in which tap coefficients for shifting the filter waveform in the + direction or the − direction with respect to the tap are stored in a pattern that is folded up and down or left and right around the center tap position and the tap coefficient position of 0 shift of the filter waveform. It has a configuration in which tap coefficients are stored.

  FIG. 1 is an explanatory diagram of a tap correspondence memory according to the first embodiment of the present invention. M1 to M5 denote tap correspondence memories provided for the taps Tap1 to Tap5 of the digital filter. The adder is not shown. The digital filter has a 5-tap configuration, the tap coefficient of its center tap (Tap3) has a 16-bit configuration, the tap coefficients of adjacent Tap2 and Tap4 have a 6-bit configuration, and the tap coefficients of Tap1 and Tap5 at the first stage and the final stage have 3 tap coefficients. Each tap-corresponding memory M1 to M5 has a bit configuration and is divided into tap-corresponding memories M1 to M5 each having a storage area of the same bit width. Each tap-corresponding memory M1 to M5 stores tap coefficients corresponding to patterns 1 to 4, respectively. Addresses for M1 to M5 are assumed to be common 0x00 to 0x03. The tap correspondence memories M1 to M5 can be applied to, for example, the digital filter memory 14 having the configuration shown in FIG. 6, and in this case, the tap correspondence memories M1 to M5 are simultaneously read by the pattern correspondence addresses. The tap coefficients are set simultaneously in the registers corresponding to the multipliers without buffering.

  Also, the addresses 0x00 to 0x03 are associated with the patterns 1 to 4, for example, when the filter characteristics of the pattern 1 are required, the tap correspondence memories M1 to M5 are accessed by the address 0x00, and the patterns for the Tap1 to Tap5 at the same time. One tap coefficient can be read simultaneously and set in a register corresponding to a multiplier not shown. That is, when switching filter characteristics, tap coefficients can be set simultaneously without buffering. This eliminates the need for a buffering buffer when updating tap coefficients in the conventional example, and allows all tap coefficients to be updated simultaneously, thereby speeding up switching of filter characteristics.

  In the case of a 5-tap digital filter configuration, the Tap1 and Tap5 compatible multipliers are configured to multiply the input data by the 3-bit configuration tap coefficients read from the tap corresponding memories M1 and M5, and the Tap2 and Tap4 compatible multiplications. The multiplier multiplies the input data by a tap coefficient having a 6-bit configuration read from the tap correspondence memory M2 or M4, and the Tap3 compatible multiplier has a 16-bit configuration read from the tap correspondence memory M3. It can be set as the structure which multiplies a tap coefficient. Therefore, the number of multiplication bits of the other tap-compatible multipliers is smaller than that of the Tap3-compatible multiplier with the maximum number of bits, so that the size can be reduced.

  The total storage area of the tap correspondence memories M1 to M5 is 3 (bits) × 4 (words) × 2 + 8 (bits) × 4 (words) × 2 + 16 (bits) × 4 (words) in the above-described bit configuration. = 136 (bits). On the other hand, the storage area of the memory of the conventional example shown in FIG. 7 is 16 (bits) × 20 (words) = 320 (bits) corresponding to the maximum number of bits. Therefore, according to the first embodiment of the present invention. For example, the storage capacity can be reduced to about 40% compared to the conventional example. Thus, the reduction in the memory capacity of the memory for storing the tap coefficients enables the reduction of the area occupied by the memory and the reduction of the scale of the multiplier constituting the digital filter. Therefore, when the digital filter is integrated. It will be advantageous. Since the number of taps of the digital filter is usually 5 taps or more, the memory configuration corresponding to the number of taps and the memory configuration corresponding to the bit configuration of the coefficient of each tap are used. It is.

  FIG. 2 shows a flowchart (A) and a sequence chart (B) of Embodiment 1 of the present invention. In the flowchart shown in FIG. Coefficient reading, that is, read access is simultaneously performed to the tap correspondence memories M1 to M5 by one address corresponding to the patterns 1 to 4 (2). As a result, the simultaneously read tap coefficients are simultaneously set in the registers corresponding to the multipliers, and the filter coefficient updating process is completed (3).

  In FIG. 2B, when a read address corresponding to the pattern is input from the control unit, tap coefficients corresponding to Tap1 to Tap5 are simultaneously read from the tap corresponding memories M1 to M5 and stored in a register corresponding to the multiplier of the digital filter. Since the setting is made, it becomes possible to immediately start the filtering process based on the new filter coefficient.

  FIG. 3 is an explanatory diagram of the characteristics of the digital filter according to the second embodiment of the present invention, and shows a case where the output waveform can be shifted back and forth by selection of the tap coefficient and has a 17-tap configuration. However, the multiplier, the adder, and the tap coefficient holding register are not shown. FIG. 3A shows a filter waveform of an impulse response, and shows a case where the waveform has a symmetrical waveform around the center tap position. Also, if the tap coefficient group in the case of the filter characteristics of the illustrated filter waveform is +0/16, switching to the tap coefficient of +1/16 results in the characteristics of the filter waveform shifted to the left side. When switched to the tap coefficient, the filter waveform characteristic shifted to the right side is obtained. This digital filter is called a digital delay filter.

  3B shows an arrangement of tap coefficients at the symmetrical positions of the center tap, and FIG. 3C shows a case where tap coefficients of tap0 to tap16 are +0/16 (0 delay). The arrangement in the case of +7/16, -8/16 is shown in the center. That is, the memory configuration storing the tap coefficients in the 17-tap digital filter has the pattern shown in (C). When the bit configuration of the tap coefficient of tap 8 of the center tap is maximized, the bit configuration of the left-right symmetric tap coefficient is a configuration corresponding to the filter waveform. As described with reference to FIG. 1, the memory storing the tap coefficients has a memory capacity tap corresponding memory configuration in accordance with the bit configuration of each tap coefficient corresponding to the tap, and simultaneously reads the tap coefficients for all the taps. The filter characteristics can be switched by setting a register corresponding to a multiplier in which is omitted. In this case, the tap correspondence memory storing the tap coefficient in this case has a storage capacity with a bit width corresponding to the tap coefficient of the maximum bit configuration. According to the embodiment of the present invention, each tap coefficient Therefore, the overall storage capacity can be greatly reduced. Further, by one tap coefficient reading process, the filter coefficient can be switched by simultaneously setting the tap coefficient in the register corresponding to the multiplier.

  FIG. 3B shows a state in which the tap coefficient arrangement patterns of tap7 and tap9 on both sides of the center tap tap8 in FIG. The curve schematically shows the value of the tap coefficient. The tap coefficient of +7/16 is large, the tap coefficient of -8/16 is small, and the tap coefficients of +7/16 and -8/16 at both ends are excluded. And symmetric tap coefficients. In FIG. 3C, with respect to the tap coefficient position of +0/16 of the center tap tap8, for example, +5/16 of tap3 and −5/16 of tap13 are indicated by dotted arrows. It is a point-symmetrical relationship. The same point-symmetric relationship is obtained for other tap coefficients. Therefore, the storage capacity of the memory for storing the tap coefficients can be further halved as an array pattern obtained by turning back the array pattern of tap coefficients from this point symmetry relationship.

  FIG. 4 is an explanatory diagram of the tap-corresponding memory, and shows a case where the storage capacity of the memory storing the tap coefficients is halved by using an array pattern of point-symmetric tap coefficients centered on the center tap tap8. With respect to the tap coefficient storage pattern shown in FIG. 3C, the tap correspondence memories M0 to M8 in the region indicated by the solid line excluding the dotted line portion can be used. The tap correspondence memory M8 corresponding to the center tap is configured to store tap coefficients of +0/16 to −8/16, which is half of the other tap correspondence memories M0 to M7. When the delay characteristic of +3/16 is obtained, the tap coefficient of +3/16 of tap0 to tap7 is set as the tap coefficient of taps tap0 to tap7 of the filter, and for the taps tap8 to tap16 of the filter, + 3 / 16 and a -3/16 tap coefficient symmetrical to the position are set in a relationship of folding around tap8. That is, a tap coefficient of +3/16 of tap0 to tap8 is set for a register of a multiplier corresponding to tap0 to tap8, and an array of tap coefficients of tap0 to tap7 is set to a register of a multiplier corresponding to tap9 to tap16 The tap coefficients of tap7 to tap0 in which the order is reversed are set in the order of arrangement of tap coefficients.

  5A and 5B are explanatory diagrams in the case of filter characteristics different from those in FIG. 4, FIG. 5A shows the configuration of the tap-compatible memory, and FIG. 5B shows the tap coefficient in the register corresponding to the multiplier. The main part of the structure which sets is shown. The memory configuration is the same as that shown in FIG. 4. Tap coefficients M0 to M7 in the tap corresponding memories M0 to M8 store tap coefficients of +7/16 to −8/16, and correspond to taps. The memory M8 stores tap coefficients of +0/16 to −8/16, and is configured with a storage capacity that is substantially half that of the entire tap correspondence memories M0 to M16. When the tap coefficient of −7/16 is set, the tap coefficient of −7/16 of the tap corresponding memory M0 to M8 is set to tap0 to tap8, and the tap coefficient of +7/16 of the tap corresponding memory M0 to M7 is set. In the reversed order, tap9 to tap16 are set.

  FIG. 5B shows the main part of the configuration in which the coefficients of taps tap0 to tsp16 are set in the registers corresponding to the tap correspondence memories M0 to M8 and the multiplier (not shown). First, the enable signal EN_L is set. In addition, the same address corresponding to −7/16 is added to the tap corresponding memories M0 to M8 in addition to the registers corresponding to tap0 to tap8, and the tap coefficient of −7/16 read simultaneously from the tap corresponding memories M0 to M8 is changed to tap0. -Tap8 corresponding register is simultaneously set, then enable signal EN_R is added to tap9-tap16 corresponding register, and the same address corresponding to +7/16 is added to tap corresponding memory M0-M7, and tap corresponding memory M0-M7 The order of the +7/16 tap coefficients read out simultaneously is reversed and stored in the registers corresponding to tap9 to tap16. It is set to.

  In this case, the total storage capacity of the tap corresponding memory for storing the tap coefficient can be substantially halved, but the tap coefficient reading process needs to be performed twice. In this case, when the time required from the first read setting process to the second read setting process cannot be ignored, the tap coefficient read in the first time is buffered. Even in this case, the buffer capacity is Compared to the conventional example, it is half. If a dual-port memory is used, the tap coefficient reading process can be performed only once, so that there is no need for buffering.

  The tap correspondence memory for storing the tap coefficients described above shows a case where the right side of the center tap is omitted, but conversely, a tap correspondence memory having the left side omitted may be employed. It is also possible to reduce the memory capacity by omitting either the top or bottom centered on the storage location of the 0 delay +0/16 tap coefficient. In this case, the tap coefficient is set as shown in FIGS. Similarly, the tap coefficients on the omitted tap corresponding memory side are set in the multiplier corresponding register by inverting the arrangement order of the tap coefficients read from the non-omitted side. For example, when the lower side is omitted around the 0 delay +0/16 of the configuration of the tap correspondence memory shown in FIG. 3C, for any tap coefficient setting of +0/16 to +7/16, Since the tap correspondence memory has a configuration of M0 to M16, tap coefficients simultaneously read from the tap correspondence memories M0 to M16 at the same address can be set simultaneously in the multiplier correspondence registers. Further, any tap coefficient setting of −1/16 to −8/16 on the omitted side can be simultaneously set in a register corresponding to the multiplier by inverting the arrangement order of the read tap coefficients.

M1-M5 Tap-capable memory Tap1-Tap5 Digital filter tap

Claims (3)

A plurality of tap-compatible multipliers; an adder that adds the multiplication outputs of the multipliers; and a memory that stores a plurality of tap-corresponding tap coefficients corresponding to filter characteristics, and the filter waveform is a center tap. In a digital filter with a symmetrical waveform,
The memory is a plurality of tap correspondence memories that collectively store tap coefficients corresponding to a plurality of types of filter characteristics in correspondence with taps, and taps that shift the filter waveform in the + direction or the − direction with respect to the center tap. A digital filter having a configuration in which the tap coefficient is stored in a pattern in which the pattern storing the coefficient is folded up and down or left and right around the center tap position and the tap coefficient position of 0 shift of the filter waveform. .   A tap for shifting the filter waveform in the + direction or the-direction with respect to the center tap, wherein the memory is a plurality of tap correspondence memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in correspondence with the tap. The tap coefficient is stored in a pattern in which the tap coefficient is stored in a pattern folded back to the left and right around the center tap position and the 0-shift tap coefficient position of the filter waveform. 2. The digital filter according to claim 1, wherein: is inverted with respect to an array of tap coefficients that are not omitted and set in a register corresponding to the multiplier.   A tap for shifting the filter waveform in the + direction or the-direction with respect to the center tap, wherein the memory is a plurality of tap correspondence memories each storing tap coefficients corresponding to a plurality of types of filter characteristics in correspondence with the tap. The tap coefficient is stored in a pattern in which the tap coefficient is stored in a pattern that is folded up and down around the center tap position and the 0-shift tap coefficient position of the filter waveform. 2. The digital filter according to claim 1, wherein: is inverted with respect to an array of tap coefficients that are not omitted and set in a register corresponding to the multiplier.

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