JPH03211910A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce the increase of a scale of a hardware in order to increase the number of taps of an FIR type filter by constituting the digital filter so that a convolutional operation to be executed is divided into blocks. CONSTITUTION:The digital filter is realized by circuits 1000, 1001 for executing a convolutional operation of the filter by divided convolutional operations, an accumulator 1002 for synthesizing its outputs and a memory 1030. In such a way, in an FIR type digital filter having a large number of taps, the increase of a scale of a hardware can be reduced, and also, by the address control of a filter coefficient ROM and an accumulation memory, the number of taps can be changed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FIR type digital filter, and particularly to a digital filter suitable for a case with a large number of taps.

[Conventional technology]

Conventional N-tap finite impulse response (FiniteI)
The npulse Re5ponse (hereinafter referred to as FIR) type digital filter is described by the following first equation.

In N-2, X represents the filter input, y represents the filter output, and h represents the impulse response of the filter. As a means for realizing the calculation of the first equation, there is, for example, a method described in Japanese Patent Application Laid-Open No. 62-284510 titled "Digital filter processor that can be connected in cascade using moving coefficients". The configuration disclosed herein is shown in FIG.

FIG. 5 is a block diagram showing a first example of a conventional digital filter. This digital filter processor 5000
is a register 501 that stores filter input data Xゎ.
N registers 5011-5 that store 0 and coefficients
N multipliers 50 that multiply 01N, X, -4 and hl
21 to 502N, N accumulators 5031 to 503N that accumulate the multiplier outputs, and a multiplexer 5040 that selects the accumulator outputs. With this configuration, input data x
,-,l! One of the filter coefficients supplied to N multipliers 5021-502N at the same time is a coefficient hN-t~ha stored in a ROM, etc., which is cyclically read out, and this is taken into a register 5011. .

N registers 5011 to 501N shift this coefficient, and the output thereof is sent to N multipliers 5021.
~502N, respectively. Accumulators 5031 to 503N are connected to each multiplier output, and here the filter coefficients are connected. The multiplier outputs of -hN-[ are accumulated. Due to the shift operation of the above filter coefficients.

The accumulators 5031 to 503N complete the calculation of the first equation one after another. The calculation results of the first equation generated in sequence are selected by the multiplexer 5040 and output as the filter output y4. With this configuration, the number of taps is 2N.
The configuration for obtaining the FIR type filter is shown in FIGS. 6 and 7.

FIG. 6 is a block diagram of the filter shown in FIG. 5 when the number of taps is increased. This digital filter is a cascade connection of digital filter processors (hereinafter referred to as DFP) shown in FIG. The filter input data X, -1 is supplied to the first DFP 6010 and the second DFP 6011, and the filter coefficients X, -1 are stored in the coefficient ROM 602, read out according to the address supplied from the sequencer 603, and inputted to the first DFP 6010. , second DF
The filter coefficients to P6011 are supplied to the first DFP.
This is performed from the final stage of the shift register of filter coefficient h9 at 6010. In FIG. 5, the filter output y. is N
In KI FIG. 6, the accumulators in the first DFP 6010 and the accumulators in the second DFP 6011 sequentially obtain the accumulators in FIG. For this purpose, the first D
The FP6010 and the second DFP6011 each have a signal for selecting an internal multiplexer and a signal for each DFP6010.
, 6011f7) output is provided. Output of first DFP6010 and second DFP60
The output of 11 is wired-off, and the enable signal enables the first DFP6010 and the second DFP6o1
By selecting the output of 1, the output y of a digital filter with 2N taps is obtained.

FIG. 7 is another configuration diagram of the filter shown in FIG. 5 when the number of taps is increased. This digital filter obtains a filter with the number of taps of 2N using one DFP shown in FIG. Filter input data xn-, data X++-
myxwa-, -5 is the first in.

First out memory (hereinafter referred to as FIFO) 701
and is supplied to the DFP 705 by the multiplexer 702. For one filter coefficient, the DFP input is χ, -1
The filter coefficient ROM 703 reads DF so that when the DFP input becomes
Supplied to P705. Signals from the sequencer 704 are supplied to each section.

The relationship between the above input data x, , x, -□1 and the coefficient h l1lh a+N can be explained by the following second equation.

mm.

I11.O The first term on the right side of the second equation is the DF for the input data X, -
The second term in the multiplication result at P705 is the input data Xゎ□-1
It can be seen that by accumulating both multiplication results in the same accumulator, the 2N tap digital filter output y is obtained. However, the shift register for storing the filter coefficients inside the DFP 705 in FIG. 7 requires twice as many shift registers as in the case of FIG. 5, as shown in FIG. 8, in order to shift the coefficient hllfhm-N. FIG. 8 is a register configuration diagram inside the DFP of FIG. 7. A coefficient register 801, a multiplier 802, and an accumulator 803 are shown.

In addition, as another means for realizing the N-tap FIR type digital filter described by the first equation, for example, Pe1ed
Abraham, Liu Bede, John
Viley & 5ons, Inc. Published 1976 0 “Digital Signal Preces
There is one described in Chapter 5 of "Sing". The configuration described here is shown in FIG.

FIG. 9 is a block diagram showing a second example of a conventional digital filter. The configuration of this digital filter is bit
This is called 5erial mechanization, and its operating principle can be explained by the following third equation.

In the third equation, the input data X has a B-bit structure and is expressed as a two's complement number, and x, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 11, 10, 10, 1f t, ,,, ,,, ,,, ,,, ,,, ,,,,, h,,,,, and eg, and, and eg, and,, eg,,,, According to the third equation, by accumulating the filter response to the th bit of input data X with a weight of 2, the filter output y
, it changes what you can get. As a method for obtaining the filter response of the bit string of the input data X, there is a method, for example, of using that bit string as an address and referring to a ROM that has previously stored the results of a convolution operation.

Now, if the ROM output is represented by F, the third equation can be rewritten into the following fourth equation.

p' Cx0e x'”'+')
(s)n n-1”n-!i÷1 Here, the parentheses of F represent the ROM address. No.

Therefore, as shown in Figure 9, the input data
The signal is input to a serial converter 901, and its output is connected to a shift register 902 having an N-stage B-bit configuration in order from the LSB. While the parallel/serial converters 901 take in one sample, the shift register 902 performs a B-bit shift operation, and from this shift register 902, the bit values x1 to "n-" of N sets of input data are input.
N+□ is taken out and the address of the convolution operation ROM 903 becomes loud. This ROM 903 stores the value of F described in Equation 5, that is, the filter response to the Nth bit string of the input data, and after being fetched into the ROM output output register 905, it is sent to the adder/subtractor 905.
is input. Note that the adder/subtracter 904 subtracts the value of the register 905 when k is zero, that is, when MSH is
is controlled to be added when is another value.

Adder/subtractor outputs are in register 906 and register 90
7 and the output of register 906 is connected to register 905.
It is connected to an adder/subtracter 904 so as to shift the signal to the LSB side by 1 bit, thereby realizing accumulation by weighting 2-k. The register 907 operates to compare the KI results when the filter response to the MSB bit string of the input data is supplied from the register 905 to the adder/subtractor 904. Through the above operation, the filter output y is obtained from the output of the register 907. A configuration for realizing a 2N tap FIR type filter using this configuration is shown in FIG.

FIG. 10 is a configuration diagram of the filter shown in FIG. 9 when the number of taps is increased. The operation of this filter can be explained by the following equation 6.

F(X,, *”'pX, -N41) -F(xn-N"
""'+-2N+1) (6) In the sixth equation, the ROM address is X, ~xn-N+□ and k and x"x (k=o-B-1)n-Nn-
2N+1, which is represented by multiplexer 1 in Figure 10.
This is realized by selecting the output of the register 102 using 08. In this case, parallel/serial conversion @1
01 accesses the convolution operation ROMIO3 only 2B times while taking in one sample. ROMIO3 has the responses for the first and second half blocks of the filter's impulse response written therein, and multiplexer 1
Block selection is performed in synchronization with the operation of 08. Registers 105, 106 and adder/subtractor 104 are the ninth
The ROM outputs for 2B bit strings are accumulated in the same manner as shown in the figure, and the register 107 operates to take out the results.

[Problem to be solved by the invention]

The above-mentioned conventional technology has a problem in that the scale of the hardware increases when the number of taps of the filter is increased. For example, in the FIR type filter configuration with 2N taps using DFPs shown in Figure 5, the example in Figure 6 requires two DFPs, and the example in Figure 7 requires N shift registers as shown in Figure 8. need to be added. Also, the bit shown in Figure 9
In the 2N tap FIR type filter configuration by serialmechanj,zation, it was necessary to add a shift register for storing N samples and an N-stage multiplexer as shown in FIG.

An object of the present invention is to provide a digital filter that reduces the increase in hardware size when increasing the number of taps of an FIR type filter.

[Means to solve the problem]

In order to achieve the above object, the digital filter according to the present invention implements the convolution operation of the filter using a circuit that performs divided convolution operations, an accumulator that combines the outputs, and a memory. .

[Effect]

By dividing the convolution operation to be executed into blocks, the digital filter described above divides the hardware required for the operation into a circuit that executes the divided convolution operation, an accumulator and memory that synthesizes the operation results. can be reduced. This will be explained using the following formula 7.

In order to execute Equation 7, the first conventional example shown in FIG. 5 requires 128 registers to store the filter coefficient h□.
Further, the second conventional example shown in FIG. 9 requires 128 registers for storing filter inputs. Therefore, considering the case where the block division method of the present invention is divided into, for example, 16 tap convolution operations, the following Equation 8 is the calculation expression after block division.

In the 8th formula, Y49. , represents the i-th convolution operation to obtain the filter output y. The hardware required for Equation 8 is a circuit for performing a 16-tap convolution operation, an accumulator for synthesizing its output, and a memory.

If the filter is a low-pass filter, the output sample rate can generally be lower than the input sample rate. Here, the hardware scale will be evaluated for the case where output is obtained for 16 input samples. In this case, for the output y0, it is only necessary to execute equation 8 when n is a multiple of 16. That is, y19 of the 8th equation. 8 blocks are calculated in the interval of 16 input samples. The calculation results for each block are stored in a register until eight blocks have been accumulated, and after the accumulation is completed, they are taken out as a filter output. Therefore, the hardware required in this case is a convolution operation circuit for the 16 input samples, an accumulator, and 8 registers for storing the accumulated results of the convolution operation. Accordingly, it is possible to reduce the amount of hardware required.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention. This digital filter is an N-tap FIR type digital filter based on a convolution operation of N input sample values and N filter coefficients, and M number of N taps (M is an integer greater than or equal to 1 and less than or equal to N). This is achieved by dividing the filter into blocks and accumulating the convolution results of each block using taps (K is an integer greater than or equal to 1 and less than or equal to M) and M filter coefficients.

The shift register 1000 includes, for example, registers 1010 to 101 each having a B-bit parallel input/output terminal, and the B-bit input sample value X input to the register 1010. N are sequentially delayed and this register 1010
The output terminals of the registers 1011 to 101 connected thereto output B-bit parallel tap power signals sequentially delayed by, for example, one clock cycle. These registers 1010~
First, the first block is selected from the coefficient ROM 1030 which stores the digital signal of B bits each outputted from the ROM 101K and the filter coefficients of the divided M blocks. The filter coefficients h1□~)lxX are multiplied by the multipliers 1020 to 102K in the convolution calculator 1001, and the outputs of the 8 multipliers are added together by the adder 1031.
The result of the convolution operation on the first block of the input sample sequence stored in 010 to 10IK is obtained. In this way, by sequentially selecting the filter coefficients hzx to hzK of the second block to the filter coefficients hwx to hMx of the M-th block from the coefficient ROM 1030, the input sample strings stored in the registers 1010 to 101K are Convolution calculation results for the first block to the Mth block are sequentially output from the convolution calculator 1001. Furthermore, + filter coefficients can be supplemented with KmagK1 zeros. However, 1. , is the number of input sample registers and is the maximum value of KI.

In this way, when the convolution operation result of the first block is output from the convolution operation unit 1001, it is inputted to the first input of the adder 1032 in the accumulator 1002, and
The initial value S1 selected by the selector 1033 is input to the second input of 32 and added, and the result of this addition is stored in the accumulation memory 1034. Then, when the convolution operation result of the second block is output from the convolution operator 1001, it is input to the first input of the adder 1032, and the second input of the adder 1032 is input to the accumulator memory 1.
The convolution result of the first block using the sample sequence +1 sample before read from 034 and the initial value S
The result of addition with 1 is input by the selector 1033, and these are added and stored in the accumulation memory 1034. That is, when the convolution result of the n-th block (n is an integer greater than or equal to 2 and less than or equal to M) is input to the accumulator 1002,
It is added to the cumulative result of the convolution operation results up to the (n-1)th block based on the past input sample string stored in the cumulative memory 1034 and stored in the cumulative memo IJ 1034. When the convolution result of the Mth block is finally input to the accumulator 1002, the accumulation memory 103
4 to the M-1th block read out, and the result is stored in register (R2) 1035. Therefore, each time the input sample values are input to the shift register 1000, the above processing is performed, and the register (R,
The result output from is the result of convolution operation with N input sample values XIN, and therefore F with N taps
Results similar to filter processing of IR digital filter y
, is obtained.

FIG. 2 is an explanatory diagram of the calculation example shown in FIG. 1. In this calculation example, the number of taps N=32. An example is shown in which the number of divided blocks M=4 and the number of taps in each block=8. S1 is the initial value, A-A is the address of the accumulation memory 1034, H11-H14 is the filter coefficient string of the convolution operation block of the convolution operation unit 1001, (1), ~7-2.2. ~
3□ indicates an input sample string. The end is an operator indicating a convolution operation, (A□) to (A, ) are the contents of the cumulative memory 1034 at addresses A1 to A4, and the arrow indicates the result of the operation on the left side to the memory 1034 or register (Rx) at the address on the right side. 1
035. As shown in the figure, the cumulative results of the calculation results of the four blocks are stored and output at the output of the register (Rz) 1035.

According to the above configuration, the output filtering operation result is an output for each input sample, which is equal to or less than the sampling rate of the input sample. / K sampling rate, but by performing similar processing for each input sample and increasing the number of cumulative memories 1034,
An output is obtained for each input sample. Also, L pieces (L is 1
The same processing is performed for each of the input samples (an integer smaller than or equal to N), and by increasing or decreasing the cumulative memory 1034, an output for each of L input samples can be obtained. When increasing the number of taps by N, the number of blocks to be divided into one block M is increased to, for example, M', the number of filter coefficients to be stored in the coefficient ROM 1030 is set to M', and the block selection in the above process is performed in the first step. This can be handled by increasing the number of accumulation memories 1034 from the M'th block to the M'th block. In other words, the increase in hardware is the coefficient ROM1030.
In addition, the number or capacity of the accumulation memory 1034 and the control circuit are small compared to the increase in the number of shift registers (SR) 102 as in the example shown in FIG. 10 of the second example of the prior art.

FIG. 3 is an explanatory diagram of the filter coefficients in FIG. 1. 1st
An example of the impulse response of the digital filter explained in the figure is shown in FIG. 3, and the above-mentioned filter coefficients are sampled at the sampling frequency ts of the input sample as shown in FIG. This filter coefficient is,
Let k be a filter coefficient sequence Ho. Now, if we sample a point shifted by t5/2 from the above sampling point, we get
Filter coefficient sequence by filter coefficient h'mk) (11 is obtained. When a convolution operation is performed using this filter coefficient sequence H, the result is obtained by interpolating the middle of the convolution operation result obtained by filter coefficient sequence H1. Therefore, in the above filter configuration, the filter coefficient sequences H10, H1
, is stored in the coefficient ROM 1.030, and the convolution operation is performed in the convolution operator 1001 using the filter coefficient sequence H101 for the same input sample sequence, and the sampling rate of the input sample is 1/ls by obtaining the result.
Results can be obtained at twice the sampling rate. Furthermore, when sampling point G is taken during the sampling period t8, the filter coefficient sequence I becomes G+1, and by performing the above filter processing using this filter coefficient sequence H, the sampling rate is G+1 times the sampling rate of the input sample. It can be converted to .

FIG. 4 is a block diagram showing another embodiment of the digital filter according to the present invention. Shift register 1000, 1-convolution operator 1ool, and coefficient ROM in the configuration shown in FIG.
1030, a parallel/serial converter 401 similar to that shown in FIG. 10 of the second example of the prior art, a shift register 408, a selector 203, and a convolution operation RO.
M403, registers 405 and 406, adder/subtractor 404, and register 2070 can be replaced with the configuration shown in the fourth @. Even with this configuration, the number of shift registers 402 can be smaller than that of shift register 102 in FIG. 10. In FIG. 4, shift register 40
2 performs operations from the first block to the M-th block, so each shift register 402 performs M-
It circulates once and is sequentially input to the next stage when the Mth block is calculated. Accumulator 1002 is similar to FIG.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the increase in the scale of hardware in an FIR type digital filter having a large number of taps. Further, the number of taps can be easily changed by controlling the addresses of the filter coefficient ROM and accumulation memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter according to the present invention, FIG. 2 is an explanatory diagram of the calculation example of FIG. 1, and FIG. 3 is an explanatory diagram of the filter coefficients of FIG. 1. FIG. 4 is a block diagram showing another embodiment of the digital filter according to the present invention, FIG. 5 is a block diagram showing the first example of the conventional digital filter, and FIG. 6 is a block diagram showing a case where the number of taps in FIG. 5 is increased. Fig. 7 is another block diagram of the filter when the number of taps in Fig. 5 is increased, Fig. 8 is a block diagram of the filter in Fig. 7.
FIG. 9 is a block diagram showing a second example of a conventional digital filter, and FIG. 10 is a block diagram of the filter shown in FIG. 9 when the number of taps is increased. 1000...Shift register, 1001...Convolution operator, 1.002...Accumulator, 1010-101K...Register, 1020-102-...Multiplier. 1030... Coefficient ROM, 1031, 1032... Adder, 1033... Selector, 1034... Accumulation memory. 1035...Register, 401...Parallel/serial converter, 402...
Shift register, 4o3...Selector, 4030...
・Convolution operation ROM, 404...Adder/subtractor, 405.406,407...Register, B 4th concave 4θ8 section 7th flash x 7I ゞf/1 small゛χ-rinn Tsumuwakuni No. 8'V Chioto

Claims (1)

[Claims] 1. An N-tap FIR type digital filter, which has N taps.
Divide the tap convolution operation into M blocks (M is an integer greater than or equal to 1 and less than or equal to N), and each of the M blocks has K
Assuming that a convolution operation is performed using __I taps (K_I is an integer greater than or equal to 1 and less than or equal to M), there are Kmax (Kmax is the maximum value of K_I) first registers that store filter input samples; means for performing divided convolution operations on the input samples stored in the registers; L adders for accumulating the results of the convolution operations;
is an integer greater than or equal to 1 and less than or equal to N. 2. The digital filter according to claim 1, wherein the second register is constituted by a RAM. 3. The digital filter according to claim 1, wherein the K_I filter coefficients are supplemented with Kmax-K_I zeros.