JP2733403B2 - Digital filter for decimation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for decimation, and more particularly to a digital filter for performing decimation and changing a frequency characteristic.

[0002]

2. Description of the Related Art Along with recent advances in digital signal processing technology, the importance of A / D conversion technology, which is an interface between analog signals and digital signals, is increasing. Especially recently, the required sampling frequency
A-Σ type A / D conversion technique with a sampling frequency much higher than fs, for example, 64 fs, is often used (1987, Technical Report of the Institute of Electronics, Information and Communication Engineers ICD87-52). Since the digital signal obtained by this A / D conversion has a sampling frequency of 64 fs, the sampling frequency fs originally required is
In order to obtain, a 64: 1 decimation must be performed. As a method of this decimation, first, 16: 1 decimation is performed using a comb filter, and then 4: 1 decimation is performed using an FIR filter, whereby efficient decimation can be performed with a relatively small circuit configuration. (1987, IEICE Technical Report ICD87-52). However, if a comb filter is used in the first stage decimation, the frequency characteristics of this filter are not flat,
That correction is required. Normally, this correction is performed by a subsequent FIR filter. Such a digital filter for decimation is shown in FIG. 8 and will be described (for example, Radio Technology Magazine, July 1989, pp. 50-5).
3).

A digital filter, a Lch input and an Rch input, of a sampling frequency of 3072 kHz supplied from two A / D converters (not shown) are used as comb filters 10.
0,104. These comb filters 100,
According to 104, 8: 1 decimation is performed, and a digital signal having a sampling frequency of 384 kHz is obtained. The digital signal obtained here is a signal whose high frequency range is slightly attenuated due to the frequency characteristics of the comb filter. Next, this signal is applied to the first-stage FIR filters 101, 1
05 is given. In the FIR filters 101 and 105,
After filtering the input digital signal based on the filter coefficient given from the ROM 103,
4: 1 decimation is performed, and a digital signal having a sampling frequency of 96 kHz is obtained. Next, this signal is applied to the second-stage FIR filters 102 and 106. In the FIR filters 102 and 106, the ROM 103
After filtering the input digital signal and correcting the frequency characteristic based on the filter coefficient given by the above, 2: 1 decimation is performed, a digital signal having a sampling frequency of 48 kHz is obtained, and output through the interface 107. Is done.

[0004]

However, in the above configuration, the FIR filter 10 which is a comb filter is used.
Since the change of the frequency characteristic caused by 0 (high frequency drop) is corrected by the digital filter in the subsequent stage for the frequency characteristic of the input signal, most of the filter coefficients have a value other than zero, and The number of calculations is reduced by using a filter coefficient that satisfies the first type Nyquist criterion (for example, Japanese Patent Application No. 63-203541)
) Cannot be used, and the number of calculations cannot be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a digital filter for decimation that can correct the frequency characteristics of an input signal and can greatly reduce the number of operations. Things.

[0006]

In order to achieve the above object, a digital filter for decimation according to the present invention performs convolution of an input digital signal with a first predetermined coefficient sequence to thereby convert the digital signal. Performs decimation and communication of the digital signal .
A first digital filter for giving a predetermined frequency characteristic with an increased high-frequency gain to the over-band component and outputting the same, an output of the first digital filter, and a second digital filter satisfying a first type Nyquist criterion. A second digital filter that performs 2: 1 decimation of the output of the first digital filter by performing convolution with a predetermined coefficient sequence.

[0007]

As described above, the decimation is performed in two steps, and the frequency characteristics of the input signal are corrected in the decimation filter in the preceding stage, so that the first type Nyquist criterion is satisfied as the filter coefficient of the decimation filter in the subsequent stage. Coefficient values can be used, with about half of the coefficient values being zero. Since the multiplication of the input signal multiplied by the coefficient value of zero can be omitted, the number of operations in the second stage decimation filter can be reduced to about half.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a digital filter for decimation according to the present invention. Referring to this figure, 1 is a first decimation filter,
The input 4 fs is converted into a 2 fs digital signal and output. 2 is a second decimation filter,
The input 2 fs digital input signal is converted into a 1 fs digital signal and output. The decimation filters 1 and 2 are respectively <Characteristic A> and <Characteristic B> in FIG.
Has the frequency characteristics shown in FIG. The aforementioned Japanese Patent Application No. 63
As shown in -184319 (title of the invention: digital filter for decimation), the first decimation filter 1 can be realized with a small number of taps because the transition region may be wide. Conversely, the second decimation filter 2 requires a large number of taps because the transition region is narrow. Here, the decimation filter 1 has 28 taps of a filter coefficient K1n (n = 0 to 27), and the decimation filter 2 has a filter coefficient K2n (n = 0 to 14).
The filter of 143 taps of 2) is used. Further, the filter coefficient K2n in the decimation filter 2
Satisfies the first type Nyquist criterion, so that K2 ₂ m ₊₁ = 0 (m = 0 to 70) and K2 ₇₁ = 0.5.

Next, the operation of the decimation filter shown in FIG. 1 will be described with reference to FIG. In FIG.
Reference numeral 21 denotes a register which stores an input digital signal and shifts in the direction of the arrow. 30 to 39 are multipliers for multiplying each input by a filter coefficient. 40 to 48 are adders. Registers 10-13,
The decimation filter 1 is constituted by the multipliers 30 to 34 and the adders 40 to 43. Registers 14-21,
The decimation filter 2 is constituted by the multipliers 35 to 39 and the adders 44 to 48. Since these decimation filters 1 and 2 perform 2: 1 decimation together with the filtering shown in FIG. 2, two inputs Dn are newly provided in the decimation filter 1 and two inputs En are newly provided in the decimation filter 2. It is sufficient to calculate one output every time.

In the decimation filter 1, an input Dn and a register 10 are input by multipliers 30-34.
13, the filter coefficient K1n (n = 0, 1,
2,..., 27) are multiplied. Therefore, in the decimation filter 1, the operation as shown in Expression (1) is performed on the input Dn, and En is output. In the decimation filter 1, in order to obtain a slightly higher characteristic in a pass band as shown in FIG.
A filter coefficient K1n of 28 taps as a result of convolution of the filter coefficient for frequency characteristic correction of the tap and the filter coefficient of the low pass filter of 24 taps is used.

[0012] In the decimation filter 2, the multipliers 35 to 3
9, the filter coefficients K2n (n = 0, 2, 4,..., 14) for the input En and the outputs of the registers 14 to 17
2) is multiplied. The input En is input to the register 14
Are input to the register 18 alternately.

Here, in the decimation filter 2, the filter coefficient K2 is K2 ₂ m ₊₁ = 0 (m =
0-70), K2 ₇₁ = 0.5, so there is no need to actually multiply these coefficients, and the number of times of multiplication is 71, which is about half of 143 which is the number of taps of the filter. Further, the multiplication of the filter coefficient K2 ₇₁ can be a 1-bit right shift of the multiplicand. Further, since one output Fn needs to be obtained for two new inputs, the input data En once multiplied by the even-numbered filter coefficient K2 ₂ n is always multiplied by the even-numbered filter coefficient. Similarly, the input data En once multiplied by the odd-numbered filter coefficient K2 ₂ n ₊₁ is always multiplied by the odd-numbered filter coefficient. Therefore, as shown in FIG. 3, the register group is multiplied by the filter coefficient (registers 14 to 17), and the register group is simply shifted right by one bit and added (registers 18 to 21).
Can be divided into groups. In this way, the decimation filter 2 performs the calculation as shown in Expression (2), and outputs the output Fn.

142 F _n = ΣE _{n−k + 2} · K2 _k (2) k = 0 As described above, since the filter for frequency characteristic correction is incorporated in the first-stage filter (decimation filter 1), the number of times of multiplication is originally determined. a lot 2 stage filter can be used to satisfy the first kind Nyquist criterion as the filter coefficients of (decimation filter 2), it is possible to dispense a number of multiplications of the filter at about half the number of taps, passing
It is possible to minimize the increase in the number of calculations due to increasing the gain in the high band of the overband component .

In FIG. 3, the filter coefficient K1
Since both n and K2n are symmetric coefficients, the output values may be sequentially added from both ends of the register group (registers 10 to 13 and registers 14 to 17) and then multiplied by the filter coefficients K1n and K2n.

FIG. 4 is a block diagram showing a specific embodiment of the digital filter for decimation according to the present invention. Referring to FIG. 1, reference numerals 50, 51, and 58 denote random access memories (hereinafter, referred to as RAMs). In this embodiment, the word length is 18 bits. RAM
Banks 50 and 51 are each composed of two banks, and bank 1 is composed of 14 words of addresses 0 to 13 and has 4fs →
Used for 2 fs decimation. Bank 2 is composed of 36 words of addresses 0 to 35, and 2fs → 1fs.
Used for decimation of The RAM 58 comprises 36 words of addresses 0 to 35. Gates 52 and 53 output data when the control signals OE1 and OE2 are 1, and have high impedance when the control signals OE1 and OE2 are 0. An adder 54 adds the 18-bit data supplied to the terminals A and B, and outputs a 19-bit addition result. 55 is a multiplier for multiplying the data given to the terminals X and Y. Here, multiplication of 19 bits × 18 bits is performed,
The upper 27 bits of the operation result are output. Reference numeral 56 denotes a read-only memory (hereinafter, referred to as a ROM), which stores filter coefficients. Here, 1 is used as the filter coefficient.
An 8-bit one is used. 57 is an accumulator.

First, the accumulator 57 will be described with reference to FIG. Based on the control signals P1 and P2, the selector 72 selects data to be input to the terminal B of the adder 70, adds the data to the terminal A of the adder 70, and adds the result to the rising edge of the clock signal φ. Synchronously, the data is fetched into the register 71 and output via the overflow limiter 73. In the selector 72, the data supplied to the terminal D when the control signal P1 = P2 = 0, and the data supplied to the terminal C when the control signals P1 = 1 and P2 = 0 similarly, P1 = 0 and P2 =
At the time of 1, the data given to the terminal B is also P1 =
When 1, P2 = 1, the data applied to the terminal A are respectively selected and output from the terminal Y. Therefore, when the control signals P1 and P2 = 0, the data supplied to the terminal A of the accumulator 57 is accumulated, and similarly, P1 = 1 and P2
= 0, the data supplied to the terminal B (the register 67
Is added to the data supplied to the terminal A of the accumulator 57, and P1 = 1, P2 = 1 or P1 =
When 0 and P2 = 1, the initial value INI1 or INI2 given to the terminal A or B of the selector 72 and the data given to the terminal A of the accumulator 57 are added.
Here, the initial values INI1 and INI2 are INI1 = 1.
00H and INI2 = 900H (see FIG. 6).
In addition, in the adder 70, 27 bits of the A input and B
The 28 bits of the input are given so that the positions of the LSB (least significant bit) are aligned. In the selector 72, the 18 bits of the C input are 28 bits of the D input and the MSB of the 28 bits of the D input is the MSB of the D input. It comes in two bits lower (see FIG. 6). MS in register 71
B is a headroom for preventing overflow.
The upper 19 bits of the 28 bits output from the register 71 are taken out, subjected to a limiter by an overflow limiter 73, and then output as 18-bit data (FIG. 6).
reference).

Referring back to FIG. 4, reference numeral 59 denotes a selector, and SEL = 0 based on a control signal SEL applied to a terminal S.
Then, the signal applied to terminal A is selected, and if SEL = 1, the signal applied to terminal B is selected and output from terminal Y. Reference numerals 60 to 67 denote registers for latching data at the rising edge of the clock signal φ. The register 66 takes in the upper 16 bits of the 18 bits output from the accumulator 57. Reference numeral 68 denotes a sequencer which sets the period of 1 fs to be finally output from 0 to 63.
Is divided into 64 time slots each having one cycle, and various control signals (OE1, OE2, P1,
P2, SEL, etc.), clock signal φ and RAM 50,
The generation of address signals for 51 and 58 is performed at a predetermined timing.

Next, the operation of FIG. 4 will be described with reference to the timing chart shown in FIG. First, the outline of the operation in FIG. 4 will be described. In the present decimation filter, in timeslots 0 to 13 and 14 to 27, filtering corresponding to the decimation filter 1 shown in FIG. 3, that is, decimation from 4 fs to 2 fs (hereinafter referred to as first stage decimation) is performed. ,
The input 18-bit, 4 fs signal is converted to an 18-bit, 2
fs signal. In the time slots 28 to 63, filtering corresponding to the decimation filter 2 in FIG. 3, that is, decimation of 2 fs → 1 fs (hereinafter referred to as decimation in the next stage) is performed, and signals of 18 bits and 2 fs are converted to 16 bits, 1f
s signal. Registers 10 to 13 in FIG.
Bank 1 of RAMs 50 and 51 as a register corresponding to
And banks 2 of the RAMs 50 and 51 are used as registers corresponding to the registers 14 to 17. The RAM 58 is used as a register corresponding to the registers 18 to 21.

Next, the operation will be described in detail. Based on the address signal output from the sequencer 68, the control signals SEL = 1 and OE2 = 1 in the time slot 0, so that the input data D26 becomes RA by the write signal WE2.
The data is written to bank 1 of M51. Furthermore, this value (D2
6) appears in the register 61 at time slot 1 by the clock signal φ. In time slots 1 to 13, RA
M51 is past input data D2 stored in bank 1
, D22,... Are sequentially output. On the other hand, the RAM 50 sequentially outputs the past input data D1, D3,... Stored in the bank 1 in time slots 0 to 12, and in the time slot 13, the control signals SEL = 1 and OE1 = 1. Is the write signal WE2
Written by Further, this value (D27) appears in the register 61 in the time slot 1 by the clock signal φ. As described above, the data is read from the RAM 50 in chronological order and the data is read from the RAM 51 in chronological order.

The data read as described above is
The data is sequentially written to the registers 60 and 61 by the clock φ. An adder 54 adds the two register outputs,
The addition result S is written to the register 62. Assuming that the output of the adder 54 in the time slot n + 1 is S1n, the relationship between S1n and the data D0 to D27 read from the RAMs 50 and 51 in the time slots 0 to 13 is as shown in Expression (3).

S1 _n = D _{2n + 1} + D _26-2n (where n = 0 to 13) (3) On the other hand, the ROM 56 stores the value of S ₀ = D1 + D26, which is the first operation in the first stage decimation, in the register 62.
Filter coefficient K1 so as to synchronize with the timing
₁ is being read. Filter coefficients of the decimation of the first stage in the time slot 1-14 K1 _1, K1 _3, K1
_{5, ..., K1 13, K1} 12, K1 10, ..., are read in the order of K1 _0, are sequentially stored in the time slot 2 to 15 in the register 63. Therefore, the outputs of the registers 62 and 63 are multiplied by the multiplier 55, and the multiplication result M is sequentially stored in the register 64. Time slot n + 2
The relationship between the addition results S1n output from the registers 62 and 63 in the time slots 2 to 15 and M1n is as shown in Expressions (4) and (5), where M1n is the output of the multiplier 55 in.

M1 _n = S1 _n · K1 _{2n + 1} (where n = 0 to 6) (4) M1 _n = S1 _n · K1 _26-2n (where n = 7 to 13) (5) Multiplier 55 Is stored in the register 64 and accumulated by the accumulator 57. In time slot 3 first multiplication result M1 ₀ in the first stage of decimation appears in the register 64, the control signal P
Since 1, P2 becomes both a 1, the initial value INI1 and the addition of the multiplication result M1 ₀ is performed, is stored in the register 71 in the accumulator 57, the accumulator in the time slot 4 5
Is output as 7 output A1 _0. Time slot 4-1
In 6, the control signals P1, P2 are both turned 0, performs accumulation of the multiplication results M1n (n = 1~13) relative accumulator output A1 ₀ described above in accumulator 57. Assume that the output of the accumulator 57 in the time slot n + 3 is A1n.
The relationship between A1n and the multiplication M1n in the time slots 3 to 16 is as shown in Expression (6). Therefore, the expression (7) is obtained by substituting the expressions (3) to (5) into the expression (6) for A1 ₁₃ which is the final output in the first stage decimation. As shown here, A1 ₁₃ obtained in time slot 17
Is equal to the input Dn passed through a digital filter having the coefficient K1n and the value of INI1 added.
Here, the value of INI1 is 100H, the accumulator 57 cuts off the lower 9 bits of the register 71, and
Since 9 bits are output as 18 bits via the limiter 73, the value of the register 71 is rounded off. This value is stored in the register 65 by the clock signal CK1 which becomes 1 in the time slot 17. Thus, the first decimation of the first stage is performed.

[0024] In the time slots 14 to 27, the first stage decimation is performed in the same manner. Here, the past input data D3 to D27 are read from the bank 1 of the RAM 50, and the latest input data D29 is written in the time slot 27 by the write signal WE1. Also, the RAM 51
Then, after the latest input data D28 is written to the bank 1 in the time slot 14 by the write signal WE2,
Past input data D26 to D2 are read. Less than,
Filtering is performed in the same manner as in the case of time slots 0 to 13. The difference between the filtering in the previous time slots 0 to 13 and the current filtering is that the control signals P1 and P2 in the time slot 17 are different.
Is 0,1. Thus, in time slot 17 in the accumulator 57 is carried out the addition of the output M2 ₀ of INI2 the multiplier 55. Therefore, the final output A2 ₁₃ in this sequence of filtering is as shown in equation (8). Here, the value of INI2 is 90
0H, the lower 9 of the register 71 in the accumulator 57.
Since the bits are discarded and the upper 19 bits are output as 18 bits via the limiter 73, the register 71
Is rounded, and the result is obtained by adding 4 to the result of passing the inputs D2 to D29 through the digital filter having the coefficient K1n (that is, the first stage decimation result). The reason for adding 4 will be described later. This value becomes the write signal WE which becomes 1 in the time slot 31.
3 is stored in the RAM 58. In this manner, the second initial stage decimation is performed.

[0025] Here, address signals for the RAMs 50 and 51 will be considered. .., 13 for the RAM 50, and for the RAM 51,
0, 1, ..., 13, time slot 1
4 to 27, the RAM 50 is 1, 2,..., 13, 0, R
It can be seen that the AM 51 should be set to 13, 0, 1,..., 12. That is, the change of the address signal to the RAMs 50 and 51 is as follows: RAM50 RAM51 1st time: 0, 1, 2, ..., 12, 130, 1, 2, ..., 13 2nd time: 1, 2, 3, ..., 13, 0 13,0,1, ..., 12 Third: 2,3, ..., 13,0,1 12,13,0, ..., 11 Fourth: 3,4, ..., 0,1,2,11,12 , 13,…, 10:: Thus, the input data is stored in the RAM 50,
By alternately writing data to the RAM 51 and reading data from the RAM 50 in the oldest order and reading data from the RAM 51 in the newest order, generation of address signals becomes very simple, and furthermore, data exchange between the RAMs 50 and 51 is performed. Also becomes unnecessary.

Next, in the time slots 28 to 63, the next stage of decimation is performed. Here, since the control signals SEL = 0 and OE2 = 1 in the time slot 28 based on the address signal output from the sequencer 68,
Output A1 ₁₃ in the first stage of decimation stored in the register 65 is next decimation input E142
As the write signal WE2 and the bank 2 of the RAM 51
Is written to. Further, this value (E142) appears in the register 61 in the time slot 29 by the clock signal φ. In the time slots 29 to 63 and the time slot 0 in the next cycle, the RAM 51 sequentially outputs the input data E138, E134,... Meanwhile, RA
M50 sequentially outputs past input data E0, E4,... Stored in bank 2 in time slots 28 to 63. As described above, the data is read from the RAM 50 in chronological order and the data is read from the RAM 51 in chronological order.

The data read as described above is sequentially written into the registers 60 and 61 by the clock φ. Thereafter, as in the case of the first-stage decimation, the adder 54 and the multiplier 55 perform calculations for decimation.

[0028] Here, the ROM 56, in the time slot 30-2, the filter coefficient K2n is for the next stage of _{decimation, K2 0, K2 4, K2} 8, ..., K
_{2 72, K2 70, K2 66} , ..., are read out in K2 ₂ order. Since this value is multiplied by the value En read from the RAMs 50 and 51 by the multiplier 55, the output M3n of the multiplier 55 is as shown in Expressions (9) and (10).

M3 _n = (E _4n + E _142-4n ) · K2 _4n (n = 0 to 17) (9) M3 _n = (E _4n + E _142-4n ) · K2 _70-4n (n = 18 to 35) (10) The multiplication result M3n obtained by the multiplier 55 is stored in the register 64 and accumulated by the accumulator 57. In time slot 31 ₀ The first multiplication result M3 appears in the register 64 in the next stage of decimation, the control signal P
Since 1,1 and P2 are 1,0, the output of the register 67 and the multiplication result M3 ₁ are added and stored in the register 71 in the accumulator 57. In the time slot 32, the output A3 of the accumulator 57 is output. Output as ₀ . In the time slot 32-2, the control signals P1, P2 are both turned 0, the multiplication result accumulation of M3n (n = 1~35) relative accumulator output A3 ₀ described above in accumulator 57 I do. The multiplication result M3n is as shown in Expressions (9) and (10).
As described above, the RAM 58 stores the past first-stage decimation output, and the register 67 captures this output (at this time, E71 is output as the first-stage decimation output) by the clock signal CK3. as shown in FIG. 6, because are shifted to the right by one bit relative to the a input of the accumulator 57, the A3 ₃₅ is the end result of a series of filtering the formula (11)
It is as shown in. Here, since K2 ₇₂ = 0.5 and K2 _{2m + 1} = 0 (m = 0 to 35), the equation (1)
The right side of 1) can be expressed as in equation (12), and it can be seen that the output of the digital filter having the filter coefficient K2n is obtained. The upper 16 bits of the output of the accumulator 57 are taken into the register 66 and output as a decimation output of the next stage, that is, a final output of the digital filter for decimation.

[0030] Here, considering the output E71 of the register 67,
This value is an output value in the second decimation described above. Therefore, this value is obtained by adding 4 to the first stage decimation result. Since this E71 is to be added to the bit position shown in FIG. 6, from the point of view of the register 66, the added value 4 is located at the most significant position of the bit that has just been truncated. That is, after adding 0.5, it is rounded down, and a rounding operation is substantially performed. As described above, in the first-stage decimation, when calculating the cumulative calculation power to be written to the RAM 58, the accumulation is performed after setting 900H as the initial value. The processing equivalent to the rounding operation can be performed by just performing the calculation. In this way, the next stage of decimation is performed, and a 16-bit, 1 fs output is obtained.

By the way, in the next stage of decimation in the next cycle, the RAM 50 writes the first stage decimation output A4 ₁₃ (= E144) to the bank 2 from the register 65, and then inputs the past input data En from the bank 2 to E140, Read in the order of E136,..., E4 (that is, in the new order). On the other hand, the RAM 51
The past input data En is read in the order of 6, E10,..., E142 (that is, the oldest order). Thus, RAM
The decimation of the next stage is performed by writing the decimation output of the first stage to the RAM 50 and the RAM 51 alternately.

Here, address signals for the RAMs 50 and 51 will be considered. In time slots 28-63,
For the RAM 50, 0, 1,...
, 0, 35, 34,..., 0, in time slots 28 to 63 in the next cycle,
AM50 is 1,2, ..., 13,0, RAM51 is 13,
It can be seen that 0, 1,... That is,
The change of the address signal to the RAMs 50 and 51 is as follows: RAM50 RAM51 1st time: 0, 1, 2, ..., 34, 3535, 34, 33, ..., 1, 0 2nd time: 0, 35, 34, ..., 2, 10, 0, 1, 2, ..., 34, 35 Third: 1, 2, ..., 34, 35, 00, 35, 34, ..., 2, 1 Fourth: 1, 0, 35, ..., 3, 2 1, 2, ..., 34, 35, 0:: Thus, the input data is stored in the RAMs 50, 5
1 is written alternately, and at the odd-numbered times, data is read out from the RAM 50 in the new order and from the RAM 51 in the oldest order.
In the even number of times, data is stored in RAM
By reading from the newest from 51,
The generation of the address signal becomes very simple and the RAM
There is no need to exchange data between the devices 50 and 51.

As described above, since the frequency characteristic correction is performed by the first stage decimation, in the second stage decimation, a filter coefficient K2n that satisfies the first type Nyquist criterion can be used. The number of times can be reduced to about half of the number of taps.

[0034]

As described above, the present invention performs the decimation of the digital signal by convolving the input digital signal with the first predetermined coefficient sequence, and also includes the pass band of the digital signal . A first digital filter for giving and outputting a frequency characteristic in which a high- frequency gain is increased with respect to the component; an output of the first digital filter; a second predetermined coefficient sequence satisfying a first type Nyquist criterion; And a second digital filter that performs 2: 1 decimation of the output of the first digital filter by performing convolution of
A coefficient value that satisfies the Nyquist first criterion can be used as a filter coefficient of the subsequent decimation filter,
As a result, the coefficient value of about half becomes zero, and the input signal multiplied by the coefficient value zero can omit the multiplication. As a result, the number of operations in the second-stage decimation filter can be reduced to about half, and the circuit scale can be significantly reduced.

Further, at the time of accumulating the product of the coefficient value and the input data string in the first stage decimation filter, the accumulation is started after presetting a predetermined value, so that in the operation in the second stage decimation filter, Even if the accumulation is started after a predetermined RAM output is preset in the accumulator, the rounding process can be performed correctly.

In addition, at the time of the product-sum operation in the decimation filters of the respective stages, one of the input data stored in each RAM is read out in the oldest order and the other is read out in the newest order, and the filter coefficients are rearranged in a corresponding order. Since the sum of the products is obtained, the generation of the address signal for each RAM is greatly simplified, which has an excellent effect that the address signal generation circuit can be greatly simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter for decimation according to the present invention.

FIG. 2 is a characteristic diagram showing frequency characteristics of a digital filter for decimation in the embodiment.

FIG. 3 is a block diagram for explaining the operation of the digital filter for decimation in the embodiment.

FIG. 4 is a block diagram showing a specific example of a digital filter for decimation according to the present invention.

FIG. 5 is a block diagram showing a specific example of an accumulator 57 in FIG.

FIG. 6 is an explanatory diagram showing selection conditions of a selector 72 in the accumulator 57 of FIG.

FIG. 7 is a timing chart showing the operation of the digital filter for decimation shown in FIG. 4;

FIG. 8 is a block diagram showing a configuration of a conventional digital filter for decimation.

[Explanation of symbols]

 1,2 decimation filter 10-21 delay circuit 30-39,55 multiplier 40-48,54 adder 50,51,58 RAM 56 ROM 57 accumulator 59,72 selector 60-66 register

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasunori Tani 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-2-33214 (JP, A) JP-A-62- 144415 (JP, A) JP-A-2-264509 (JP, A) Radio technology, July 1989 issue. P. 50-53

Claims (3)

(57) [Claims] 1. A decimation of the digital signal by convolving an input digital signal with a first predetermined coefficient sequence, and a high-frequency gain with respect to a pass band component of the digital signal. Performing a convolution of a first digital filter that gives an output with an increased frequency characteristic and outputs the first digital filter and a second predetermined coefficient sequence that satisfies the first type Nyquist criterion Thus, the first digital filter output 2:
1. A digital filter for decimation, comprising: a second digital filter that performs decimation of 1. 2. A storage device in which a first digital filter stores an input digital signal for a predetermined number of samples, a first memory storing a first predetermined coefficient sequence, and an output of the storage device. A first multiplier for multiplying the first multiplier with a value read from the first memory; an accumulator for accumulating an output of the first multiplier with a predetermined value other than zero as an initial value; And a second digital filter storing first and second storage devices to which the output of the first digital filter is alternately input, and a second predetermined coefficient sequence. A second memory, a second multiplier for multiplying data stored in the first storage device by a value read from the second memory, and initializing an output of the second storage device. The value of the output of the second multiplier as a value Decimation digital filter according to claim 1, characterized in that performing the convolution by that and a accumulator for performing. 3. A storage device in which at least one of the first and second digital filters stores data to be multiplied by a predetermined coefficient sequence is constituted by first and second storage means. And multiplying a value obtained by reading the predetermined data from the storage means and multiplying the sum by the predetermined coefficient sequence, and writing the data to the first and second storage means is performed by the storage device. Are alternately written to the first and second storage means,
2. The data reading device according to claim 1, wherein one of the first and second storage devices is read from an older one and the other is read from a newer one. Digital filter for decimation as described.