JPH05175785A - Digital filter for decimation - Google Patents

Abstract

PURPOSE:To obtain the digital filter for 4:1 decimation with simple configuration in which a frequency characteristic is corrected. CONSTITUTION:The 4:1 decimation digital filter consists of 4:2 and 2:1 decimation filters 1, 2 in two stages, the 1st stage decimation filter 1 implements frequency characteristic correction and the next stage decimation filter 2 is formed by using a filter coefficient satisfying the 1st class Nyquist criterion. Furthermore, the 1st stage decimation filter 1 is formed by using two RAMs and the next stage decimation filter is formed by using three RAMs, input data are written alternately, data are read in the older order from one stage and from the other stage. Furthermore, in the case of calculation of the 1st stage decimation filter 1, a prescribed value is used for an initial value for the accumulation and the output of the 1st stage decimation filter 1 is used for an initial value to attain accumulation in the calculation of the next stage decimation filter 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for decimation, and more particularly to a digital filter for performing decimation and changing frequency characteristics.

[0002]

2. Description of the Related Art With recent advances in digital signal processing technology, the importance of A / D conversion technology, which is an interface between analog signals and digital signals, is increasing. Especially recently, the required sampling frequency
A Δ-Σ type A / D conversion method with a sampling frequency of much higher than fs, for example, 64 fs is often used (1987, Institute of Electronics, Information and Communication Engineers Technical Report Meeting ICD87-52). Since the digital signal obtained by this A / D conversion has a sampling frequency of 64fs, the sampling frequency fs originally required
In order to obtain, a decimation of 64: 1 has to be done. As a method of this decimation, first, 16: 1 decimation is performed using a comb filter, and then 4: 1 decimation is performed using an FIR filter, so that decimation can be performed efficiently with a relatively small circuit configuration. Yes (1987, IEICE Technical Research Report Meeting ICD87-52). However, when the comb filter is used in the first stage decimation, the frequency characteristic of this filter is not flat,
The correction is needed. Usually, this correction is performed by the FIR filter at the latter stage. Such a decimation digital filter is shown in FIG. 8 and explained (for example, Radio Technical Journal, 1989, July issue, pp. 50-5).
3).

Two channels of digital inputs having a sampling frequency of 3072 kHz supplied from two A / D converters (not shown), the Lch input and the Rch input are comb filters 10.
It is given to 0,104. These comb filters 100,
Decimation of 8: 1 is performed by 104, and a digital signal having a sampling frequency of 384 kHz is obtained. The digital signal obtained here is a signal in which the high frequency band is slightly attenuated due to the frequency characteristics of the comb filter. Next, this signal is the first stage FIR filter 101, 1
Give to 05. In the FIR filters 101 and 105,
After filtering the input digital signal based on the filter coefficient given from the ROM 103,
Decimation of 4: 1 is performed, and a digital signal with a sampling frequency of 96 kHz is obtained. Next, this signal is applied to the second stage FIR filters 102 and 106. In the FIR filters 102 and 106, the ROM 103
After the input digital signal is filtered and the frequency characteristic is corrected based on the filter coefficient given by the filter coefficient, a 2: 1 decimation is performed, and a digital signal with a sampling frequency of 48 kHz is obtained and output via the interface 107. To be done.

[0004]

However, in the above configuration, the FIR filter 10 which is a comb filter is used.
Since the change of the frequency characteristic caused by 0 (the high frequency falls) is corrected in the frequency characteristic of the input signal in the digital filter in the latter stage, most of the filter coefficients have values other than zero, and The number of calculations is reduced by using a filter coefficient that satisfies the first type Nyquist criterion (for example, Japanese Patent Application No. 63-203541).
However, there is a problem that the number of calculations cannot be reduced.

In view of the above problems, it is an object of the present invention to provide a decimation digital filter capable of correcting the frequency characteristic of an input signal and significantly reducing the number of calculations. It is a thing.

[0006]

In order to achieve this object, a decimation digital filter according to the present invention convolves an input digital signal with a first predetermined coefficient sequence to obtain the digital signal. A first digital filter that performs decimation and outputs by giving a predetermined frequency characteristic to the digital signal, an output of the first digital filter, and a second predetermined filter that satisfies the first type Nyquist criterion And a second digital filter for performing a 2: 1 decimation of the output of the first digital filter by performing convolution with a coefficient sequence.

[0007]

As described above, since the decimation is performed in two steps and the frequency characteristic of the input signal is corrected in the decimation filter in the previous stage, the first-class Nyquist criterion is satisfied as the filter coefficient of the decimation filter in the subsequent stage. Coefficient values can be used and about half of the coefficient values will be zero. Since the input signal multiplied by the coefficient value zero can omit the multiplication, as a result, the number of operations in the second stage decimation filter can be reduced to about half.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a digital filter for decimation according to the present invention. To explain this figure, 1 is the first decimation filter,
The input 4fs is converted into a 2fs digital signal and output. 2 is a second decimation filter,
The input 2fs digital input signal is converted into a 1fs digital signal and output. The decimation filters 1 and 2 are <characteristic A> and <characteristic B> of FIG. 2, respectively.
It has the frequency characteristics shown in. The aforementioned Japanese patent application Sho 63
As described in No. 184319 (Title of Invention: Digital Filter for Decimation), the first decimation filter 1 can be realized with a small number of taps because the transition region can be wide. On the contrary, the second decimation filter 2 needs a large number of taps because the transition region is narrow. Here, the decimation filter 1 has 28 taps of the filter coefficient K1n (n = 0 to 27), and the decimation filter 2 has the filter coefficient K2n (n = 0 to 14).
The 143-tap filter of 2) is used. Furthermore, the filter coefficient K2n in the decimation filter 2
Satisfies the first type Nyquist criterion, and thus K2 ₂ m ₊₁ = 0 (m = 0 to 70) and K2 ₇₁ = 0.5.

Next, the operation of the decimation filter shown in FIG. 1 will be described with reference to FIG. In FIG.
Reference numeral 21 is a register, which stores an input digital signal and shifts in the direction of the arrow. Reference numerals 30 to 39 denote multipliers, which multiply each input by a filter coefficient. 40 to 48 are adders. Registers 10-13,
The decimation filter 1 is composed of the multipliers 30 to 34 and the adders 40 to 43. Registers 14-21,
The decimation filter 2 is composed of the multipliers 35 to 39 and the adders 44 to 48. Since the decimation filters 1 and 2 perform 2: 1 decimation together with the filtering as shown in FIG. 2, two inputs Dn are newly provided to the decimation filter 1 and two inputs En are newly provided to the decimation filter 2. It is sufficient to calculate one output for each.

In the decimation filter 1, multipliers 30 to 34 input Dn and registers 10 to 10.
For the output of 13, the filter coefficient K1n (n = 0, 1,
2, ..., 27) are multiplied. Therefore, in the decimation filter 1, the input Dn is arithmetically operated as shown in the equation (1), and En is output. In the decimation filter 1, in order to obtain a slightly high rise characteristic in the pass band as shown in <Characteristic A> in FIG.
A filter coefficient K1n of 28 taps is used as a result of convolution of the filter coefficient for correcting the frequency characteristic of the tap and the filter coefficient of the low pass filter of 24 taps.

[0012] In the decimation filter 2, the multipliers 35-3
The filter coefficient K2n (n = 0, 2, 4, ..., 14) is applied to the input En and the outputs of the registers 14 to 17 by 9
2) is multiplied. The input En is the register 14
And register 18 are alternately input.

In the decimation filter 2, the filter coefficient K2 is K2 ₂ m ₊₁ = 0 (m =
Since 0 to 70) and K2 ₇₁ = 0.5, it is not actually necessary to multiply these coefficients, and the number of multiplications is 71, which is about half of 143 which is the number of filter taps. Further, the multiplication of the filter coefficient K2 ₇₁ may be a 1-bit right shift of the multiplicand. Furthermore, since it is only necessary to obtain one output Fn for two new inputs, the input data En once multiplied by the even-numbered filter coefficient K2 ₂ n should always be multiplied by the even-numbered filter coefficient. Similarly, the input data En, which is once multiplied by the odd-numbered filter coefficient K2 ₂ n _+1, is always multiplied by the odd-numbered filter coefficient. Therefore, as shown in FIG. 3, there are two types of registers (registers 14 to 17) for multiplying the register group by the filter coefficient, and ones (registers 18 to 21) for simply shifting the registers by 1 bit to the right.
It can be divided into groups. In this way, the decimation filter 2 performs the calculation as shown in the equation (2) and outputs the output Fn.

[0014] Since the frequency characteristic correction filter is incorporated in the first-stage filter (decimation filter 1) in this way, the first-stage Nyquist criterion is satisfied as the filter coefficient of the second-stage filter (decimation filter 2) that originally has a large number of multiplications. The number of multiplications of the filter can be reduced to about half the number of taps, and the increase in the number of calculations due to the incorporation of the correction filter can be minimized.

In FIG. 3, the filter coefficient K1
Since n and K2n are symmetrical coefficients, the output values may be sequentially added from both ends of the register group (registers 10 to 13 and registers 14 to 17) and then the filter coefficients K1n and K2n may be multiplied.

FIG. 4 is a block diagram showing a specific embodiment of the digital filter for decimation according to the present invention. Explaining this figure, reference numerals 50, 51 and 58 are random access memories (hereinafter referred to as RAM). In this embodiment, the word length is 18 bits. RAM
50 and 51 are each composed of two banks, and bank 1 consists of 14 words of addresses 0 to 13 and 4fs →
Used for 2 fs decimation. Bank 2 consists of 36 words with addresses 0 to 35, and 2fs → 1fs
Used for the decimation of. The RAM 58 consists of 36 words of addresses 0 to 35. Reference numerals 52 and 53 denote gates, which output data when the control signals OE1 and OE2 are 1, and have high impedance when they are 0. An adder 54 adds the 18-bit data given to the terminals A and B and outputs a 19-bit addition result. A multiplier 55 multiplies the data given to the terminals X and Y. Here, multiplication of 19 bits x 18 bits is performed,
The upper 27 bits of the operation result are output. Reference numeral 56 is a read only memory (hereinafter referred to as ROM), which stores filter coefficients. Here, the filter coefficient is 1
The 8-bit one is used. 57 is an accumulator.

First, the accumulator 57 will be described with reference to FIG. Based on the control signals P1 and P2, the selector 72 selects the data to be input to the terminal B of the adder 70, adds the data to the terminal A of the adder 70, and adds the result to the rising edge of the clock signal φ. It is adapted to be synchronously loaded into the register 71 and output via the overflow limiter 73. In the selector 72, the data given to the terminal D when the control signal P1 = P2 = 0, the data given to the terminal C when P1 = 1 and P2 = 0, and the data P1 = 0 and P2 =
When it is 1, the data given to the terminal B is also P1 =
When 1 and P2 = 1, the data applied to the terminal A is selected and output from the terminal Y. Therefore, when the control signals P1 and P2 = 0, the data given to the terminal A of the accumulator 57 is accumulated, and similarly, P1 = 1 and P2.
= 0, the data (register 67
Output) and the data given to the terminal A of the accumulator 57 are added, and similarly, P1 = 1, P2 = 1 or P1 =
When 0 and P2 = 1, the initial value INI1 or INI2 given to the terminal A or B of the selector 72 and the data given to the terminal A of the accumulator 57 are added.
Here, the initial values INI1 and INI2 are INI1 = 1.
00H and INI2 = 900H (see FIG. 6).
In addition, in adder 70, 27 bits of A input and B
The 28 bits of the input are given such that the positions of the LSB (least significant bit) are aligned, and in the selector 72, the 18 bits of the C input are the 28 bits of the D input and the MSB of the MSB of the D input is It comes to be in the lower 2 bits (see FIG. 6). MS in register 71
B is a headroom for preventing overflow.
The upper 19 bits of the output 28 bits of the register 71 are taken out, subjected to a limiter by the overflow limiter 73, and then output as 18-bit data (FIG. 6).
reference).

Returning to FIG. 4, reference numeral 59 is a selector, and SEL = 0 based on the control signal SEL given to the terminal S.
If so, the signal applied to the terminal A is selected, and if SEL = 1, the signal applied to the terminal B is selected and output from the terminal Y. Reference numerals 60 to 67 are registers, which capture and latch data at the rising edge of the clock signal φ. Of these, the register 66 is adapted to capture the upper 16 bits of the output 18 bits of the accumulator 57. Reference numeral 68 is a sequencer, which sets the cycle of 1 fs to be finally output to 0 to 63.
Is divided into 64 time slots, and the various control signals (OE1, OE2, P1,
P2, SEL, etc.) and clock signal φ and RAM 50,
Address signals are generated for 51 and 58 at a predetermined timing.

Next, the operation of FIG. 4 will be described with reference to the timing chart of FIG. First, the outline of the operation of FIG. 4 will be described. In this decimation filter, in timeslots 0 to 13 and 14 to 27, filtering corresponding to decimation filter 1 shown in FIG. 3, that is, decimation of 4fs → 2fs (hereinafter referred to as first stage decimation) is performed. ,
Input 18-bit, 4fs signal to 18-bit, 2
Convert to fs signal. In the time slots 28 to 63, filtering corresponding to the decimation filter 2 in FIG. 3, that is, decimation of 2fs → 1fs (hereinafter referred to as decimation of the next stage) is performed, and a signal of 18 bits and 2fs is 16 bits. 1f
s signal. Registers 10 to 13 in FIG.
Bank 1 of RAM 50, 51 as a register corresponding to
The bank 2 of the RAMs 50 and 51 is used as a register corresponding to the registers 14 to 17. The RAM 58 is used as a register corresponding to the registers 18 to 21.

Next, details of the operation will be described. Based on the address signal output from the sequencer 68, the control signals SEL = 1 and OE2 = 1 at time slot 0, so that the input data D26 is RA by the write signal WE2.
Written to bank 1 of M51. Furthermore, this value (D2
6) appears in the register 61 in the time slot 1 by the clock signal φ. In time slots 1-13, RA
M51 is the past input data D2 stored in bank 1.
4, D22, ... are sequentially output. On the other hand, the RAM 50 sequentially outputs the past input data D1, D3, ... Stored in the bank 1 in the time slots 0 to 12, and the control signals SEL = 1 and OE1 = 1 in the time slot 13, so that at this time point. Input data D27 at write signal WE2
Written by Further, this value (D27) appears in the register 61 in the time slot 1 by the clock signal φ. In this way, the RAM 50 reads the data in the oldest order, and the RAM 51 reads the data in the newest order.

The data read out as described above is
It is sequentially written in the registers 60 and 61 by the clock φ. The adder 54 adds these two register outputs,
The addition result S is written in the register 62. When the output of the adder 54 in the time slot n + 1 is S1n, the relation between the data D0 to D27 read from the RAMs 50 and 51 in the time slots 0 to 13 and S1n is as shown in the equation (3).

S1 _n = D _{2n + 1} + D _26-2n (where n = 0 to 13) (3) On the other hand, in the ROM 56, the value of S ₀ = D1 + D26, which is the first operation in the decimation of the first stage, is registered in the register 62.
Filter coefficient K1 so as to synchronize with the timing
₁ is being read. In time slots 1 to 14, the filter coefficients of the first stage decimation are K1 ₁ , K1 ₃ , and K1.
₅ , ..., K1 ₁₃ , K1 ₁₂ , K1 ₁₀ , ..., K1 ₀ are read in this order, and are sequentially stored in the register 63 in the time slots 2 to 15. Therefore, the outputs of these registers 62 and 63 are multiplied by the multiplier 55, and the multiplication result M is sequentially stored in the register 64. Time slot n + 2
With the output of the multiplier 55 in M1n as M1n, the relationship between the addition results S1n and M1n output from the registers 62 and 63 in the time slots 2 to 15 is as shown in equations (4) and (5).

M1 _n = S1 _n · K1 _{2n + 1} (where n = 0 to 6) (4) M1 _n = S1 _n · K1 _26-2n (where n = 7 to 13) (5) Multiplier 55 The multiplication result M1n obtained by is stored in the register 64 and accumulated by the accumulator 57. In the time slot 3 in which the first multiplication result M1 ₀ in the decimation of the first stage appears in the register 64, the control signal P
Since both 1 and P2 are 1, the initial value INI1 and the multiplication result M1 ₀ are added and stored in the register 71 in the accumulator 57.
7 outputs are output as A1 ₀ . Time slots 4 to 1
In 6, the control signals P1 and P2 are both 0, so the accumulator 57 accumulates the multiplication result M1n (n = 1 to 13) with respect to the accumulator output A1 ₀ described above. The output of the accumulator 57 at time slot n + 3 is A1n,
The relationship between A1n and multiplication M1n in time slots 3 to 16 is as shown in equation (6). Therefore, for A1 ₁₃ which is the final output in the decimation of the first stage, equation (7) is obtained by substituting equations (3) to (5) into equation (6). As shown here, A1 ₁₃ obtained in time slot 17
Is equal to the input Dn filtered by a digital filter with coefficient K1n plus the value of INI1.
Here, the value of INI1 is 100H, and the lower 9 bits of the register 71 are truncated in the accumulator 57, and the upper 1
Since 9 bits are output as 18 bits via the limiter 73, the value in the register 71 is rounded off. This value is stored in the register 65 by the clock signal CK1 which becomes 1 in the time slot 17. In this way, the first decimation of the first stage is performed.

[0024] Similarly, in the time slots 14 to 27, the first stage decimation is performed. Here, the past input data D3 to D27 are read from the bank 1 of the RAM 50, and the latest input data D29 is written in the time slot 27 by the write signal WE1. In addition, RAM51
Then, after the latest input data D28 is written in the bank 1 in the time slot 14 by the write signal WE2,
The past input data D26 to D2 are read. Less than,
Filtering is performed in the same manner as in the case of time slots 0 to 13. The difference between the previous filtering in time slots 0 to 13 and the current filtering is that the control signals P1 and P2
Is that the values of 0 and 1 are 0 and 1, respectively. As a result, in the time slot 17, the accumulator 57 adds INI2 and the output M2 ₀ of the multiplier 55. Therefore, the final output A2 ₁₃ in this series of filtering is as shown in equation (8). Here, the value of INI2 is 90
0H, and the lower 9 bits of the register 71 in the accumulator 57
Since the bits are truncated and the upper 19 bits are output as 18 bits via the limiter 73, the register 71
Is rounded to the value obtained by passing the inputs D2 to D29 through the digital fill having the coefficient K1n (that is, the decimation result of the first stage) and adding 4. The reason for adding 4 will be described later. The write signal WE whose value becomes 1 in the time slot 31
3 is stored in the RAM 58. In this way, the second decimation of the first stage is performed.

[0025] Here, consider address signals for the RAMs 50 and 51. In time slots 0 to 13, 0, 1, ..., 13 for RAM 50, and RAM 51 for
0,1, ..., 13, time slot 1
In 4 to 27, the RAM 50 is 1, 2, ..., 13, 0, R
It can be seen that AM51 may be set to 13, 0, 1, ... That is, the change of the address signal with respect to the RAM 50, 51 is as follows: RAM50 RAM51 1st time: 0, 1, 2, ..., 12, 13 0, 1, 2, ..., 13 2nd time: 1, 2, 3, ..., 13, 0 13,0,1, ..., 12 3rd time: 2,3, ..., 13,0,1 12,13,0, ..., 11 4th time: 3,4, ..., 0,1,2,11,12 , 13,…, 10 ：: In this way, the input data is transferred to the RAM 50,
By alternately writing to 51, reading the data in the RAM 50 in the oldest order and reading the data in the RAM 51 in the newest order, the generation of the address signal becomes very simple, and moreover, the exchange of the data between the RAMs 50 and 51 is performed. Becomes unnecessary.

Next, in the time slots 28 to 63, the decimation of the next stage is performed. Here, since the control signals SEL = 0 and OE2 = 1 in the time slot 28 based on the address signal output from the sequencer 68,
The output A1 ₁₃ in the decimation of the first stage stored in the register 65 is the decimation input E142 of the next stage.
As a write signal WE2, the bank 2 of the RAM 51
Written in. Further, this value (E142) appears in the register 61 in the time slot 29 by the clock signal φ. In the time slots 29 to 63 and time slot 0 in the next cycle, the RAM 51 sequentially outputs the input data E138, E134, ... Stored in the bank 2 for the past decimation of the next stage. On the other hand, RA
The M50 sequentially outputs the past input data E0, E4, ... Stored in the bank 2 in the time slots 28 to 63. In this way, the RAM 50 reads the data in the oldest order, and the RAM 51 reads the data in the newest order.

The data read as described above is sequentially written into the registers 60 and 61 by the clock φ. Thereafter, as in the case of the decimation in the first stage, the adder 54 and the multiplier 55 perform the operation for decimation.

From the ROM 56, in the time slots 30 to 2, the filter coefficients K2n for the decimation at the next stage are K2 ₀ , K2 ₄ , K2 ₈ , ..., K.
2 ₇₂ , K2 ₇₀ , K2 ₆₆ , ..., K2 ₂ are read in this order. Since this value is multiplied by the value En read from the RAMs 50 and 51 by the multiplier 55, the output M3n of the multiplier 55 is as shown in equations (9) and (10).

M3 _n = (E _4n + E _142-4n ) · K2 _4n (n = 0 to 17) (9) M3 _n = (E _4n + E _142-4n ) · K2 _70-4n (n = 18 to 35) (10) The multiplication result M3n obtained by the multiplier 55 is stored in the register 64 and accumulated by the accumulator 57. In the time slot 31 in which the first multiplication result M3 ₀ in the decimation of the next stage appears in the register 64, the control signal P
Since 1 and P2 are 1 and 0, the output of the register 67 and the multiplication result M3 ₁ are added, stored in the register 71 in the accumulator 57, and the output A3 of the accumulator 57 in the time slot 32. Output as ₀ . Since the control signals P1 and P2 are both 0 in the time slots 32 to 2, the accumulator 57 accumulates the multiplication result M3n (n = 1 to 35) with respect to the accumulator output A3 ₀ described above. I do. The multiplication result M3n is as shown in equations (9) and (10),
As described above, the RAM 58 stores the decimation output of the first stage in the past, and the register 67 captures this output (E71 is output as the decimation output of the first stage at this point) by the clock signal CK3. as shown in FIG. 6, because are shifted to the right by one bit relative to the a input of the accumulator 57, the A3 ₃₅ is the end result of a series of filtering the formula (11)
It becomes as shown in. Here, since K2 ₇₂ = 0.5 and K2 _{2m + 1} = 0 (m = 0 to 35), the formula (1
It can be seen that the right side of 1) can be expressed as in equation (12), and the output of the digital filter having the filter coefficient K2n is obtained. The upper 16 bits of the output of the accumulator 57 are taken into the register 66 and output as the decimation output of the next stage, that is, the final output of the digital filter for decimation.

[0030] Here, considering the output E71 of the register 67,
This value is the output value in the second decimation described above. Therefore, this value is the decimation result of the first stage plus 4. Since this E71 will be added to the bit position shown in FIG. 6, when viewed from the register 66, the added value 4 is located at the most significant bit of the bit just truncated. That is, after adding 0.5, the data is rounded down, and the rounding operation is substantially performed. As described above, in the decimation of the first stage, when the cumulative calculation power to be written in the RAM 58 is calculated, the cumulative value is set after the initial value is set to 900H, so that the rounding process is simply performed in the time slot 3. It is possible to perform processing equivalent to the rounding operation with just In this way, the decimation of the next stage is performed, and a 16-bit, 1fs output is obtained.

By the way, in the decimation of the next stage in the next cycle, the RAM 50 writes the decimation output A4 ₁₃ (= E144) of the first stage to the bank 2 from the register 65 and then the past input data En from the bank 2 to E140, Reading is performed in the order of E136, ..., E4 (that is, new order). On the other hand, RAM51 is
The past input data En are read in the order of 6, E10, ..., E142 (that is, old order). Thus, RAM
The decimation of the next stage is performed by alternately writing the decimation output of the first stage into the RAM 50 and the RAM 51.

Now, consider address signals for the RAMs 50 and 51. In time slots 28-63,
For RAM 50, 0, 1, ..., 35, RAM 51
, 35, 34, ..., 0, then R in the time slots 28 to 63 in the next cycle.
AM50 is 1, 2, ..., 13, 0, RAM 51 is 13,
It can be seen that 0, 1, ... That is,
The change of the address signal with respect to the RAM 50, 51 is as follows: RAM50 RAM51 1st time: 0, 1, 2, ..., 34, 35 35, 34, 33, ..., 1, 0 2nd time: 0, 35, 34 ,. 10th, 1st, 2nd, ..., 34, 35 3rd time: 1, 2, 3, ..., 34, 35, 0 0th, 35, 34, ..., 2, 1 4th time: 1, 0, 35 ,. 2 1, 2, ..., 34, 35, 0 ::. In this way, input data is stored in RAM 50, 5
Alternately write data to 1, read data from RAM 50 in new order and read data from RAM 51 in old order at odd number of times,
In the even number of times, the data is transferred from RAM 50 in the order of oldest to RAM.
By reading from 51 in ascending order,
Generating address signals is very easy, and RAM
Data exchange between 50 and 51 is also unnecessary.

As described above, since the frequency characteristic correction is performed in the decimation in the first stage, in the decimation in the next stage, the filter coefficient K2n that satisfies the Nyquist criterion of the first kind can be used, and the multiplication of the filter can be performed. The number of taps can be reduced to about half the number of taps.

[0034]

As described above, according to the present invention, the digital signal is decimated by convolving the input digital signal and the first predetermined coefficient sequence, and A first digital filter for giving a predetermined frequency characteristic and outputting;
The first digital filter output is convolved with the second predetermined coefficient sequence satisfying the Nyquist criterion of the first kind by the convolution of the first digital filter output 2:
By providing the second digital filter that performs the decimation of 1, it is possible to use the coefficient value that satisfies the Nyquist first criterion as the filter coefficient of the decimation filter in the subsequent stage, and thereby the coefficient value of about half becomes zero. , The input signal multiplied by zero coefficient value can omit the multiplication. As a result, the number of calculations in the second stage decimation filter can be reduced to about half, and the circuit scale can be significantly reduced.

Furthermore, when the product of the coefficient value and the input data string in the first stage decimation filter is accumulated, the accumulation is started after presetting a predetermined value, so that in the calculation in the second stage decimation filter. Even if the accumulation is started after the predetermined RAM output is preset in the accumulator, the rounding process can be correctly performed.

In addition, at the time of multiply-accumulate operation in the decimation filter of each stage, one of the input data stored in each RAM is read in the old order and the other is read in the new order, and the filter coefficients are rearranged in the corresponding order. Since the sum of products is calculated, the generation of the address signal for each RAM is greatly simplified, which has an excellent effect that the address signal generation circuit can be greatly simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital filter for decimation according to the present invention.

FIG. 2 is a characteristic diagram showing frequency characteristics of a digital filter for decimation in the same example.

FIG. 3 is a block diagram for explaining the operation of the decimation digital filter in the embodiment.

FIG. 4 is a block diagram showing a specific example of a decimation digital filter according to the present invention.

5 is a block diagram showing a specific example of an accumulator 57 in FIG.

6 is an explanatory view showing selection conditions of a selector 72 in the accumulator 57 of FIG.

7 is a timing diagram showing the operation of the digital filter for decimation shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional digital filter for decimation.

[Explanation of symbols]

 1, 2 decimation filter 10-21 delay circuit 30-39,55 multiplier 40-48,54 adder 50,51,58 RAM 56 ROM 57 accumulator 59,72 selector 60-66 register

Claims (3)

[Claims] 1. A digital signal which is input is convoluted with a first predetermined coefficient sequence to decimate the digital signal, and a predetermined frequency characteristic is given to the digital signal for output. First
2) of the first digital filter output by convolving the first digital filter output with the second predetermined coefficient sequence satisfying the Nyquist criterion of the first kind:
A second digital filter for performing decimation of 1. and a second digital filter for decimation. 2. A storage device in which a first digital filter stores an input digital signal for a predetermined number of samples, a first memory for storing a first predetermined coefficient sequence, and an output of the storage device. A first multiplier that multiplies the value read from the first memory with a value that is read from the first memory; and an accumulator that accumulates the output of the first multiplier with a predetermined value other than zero as an initial value, By performing convolution, the second digital filter stores the first and second storage devices to which the output of the first digital filter is alternately input, and the second predetermined coefficient sequence. A second memory, a second multiplier that multiplies the data stored in the first storage device by a value read from the second memory, and an output of the second storage device is initialized. The value is the cumulative output of the second multiplier. Decimation digital filter according to claim 1, characterized in that performing the convolution by that and a accumulator for performing. 3. A storage device in which at least one of the first and second digital filters stores data to be multiplied with a predetermined coefficient sequence is composed of first and second storage means, respectively. Reading predetermined data from the storage means and multiplying the value obtained by adding each with the predetermined coefficient sequence, and writing the data to the first and second storage means is performed by the storage device. The data given to are alternately written in the first and second storage means,
Further, in reading data from each of the storage means, one of the first and second storage means is read in an old order, and the other is read in a new order. Digital filter for decimation described.