JP3243831B2 - FIR type filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FIR filter, and more particularly to an FIR filter having a reduced required memory.

[0002]

2. Description of the Related Art A non-recursive FIR filter shown in FIG. 1 is known. In the figure, a triangular block represents a multiplier, a square block represents a memory of a delay amount of D, and a circular block represents an adder. The notation of these blocks is the same in the following description. The FIR filter shown in FIG. 1 has an output y _k represented by the following equation.
It is well known to produce

[0003]

(Equation 1)

As described above, the n-order FIR filter of the conventional non-recursive configuration requires n memories. On the other hand, there has been proposed a method in which the memory can be reduced to n / m when performing the thinning-out of m: 1 by using a cyclic configuration in which only the intermediate result of the convolution is stored. This cyclic configuration produces an output represented by the following equation:

[0005]

(Equation 2)

[0006] w _k can be constituted by a cyclic circuit of a time-varying coefficient as shown in FIG. That is, the memory is reset (cleared) at time kn, and the multiplier coefficient alpha and alpha = a _n, the multiplication result captures a _n x _kn in memory. Thereafter, the cyclic operation is performed while changing α as described below until time k.

[0007] in the same manner described above and again from k + 1 of the time, and the α is calculated while changing from a _n up to _{a 0, w k + n =} a 0 x k + n + a 1 x k + n-1 + a 2 x k + _{n-2 + ···· + a n} x k + 1 is obtained.

On the other hand, the output is a cyclic output of a set of every nth output, such as y _k = w _k y _{k + n} = w _{k + n} y _{k + 2n} = w _{k + 2n.} Obtained in a mold configuration.

Further, an FIR type filter having a symmetric coefficient is known. In the conventional non-cyclic type configuration, the number of multipliers can be reduced by modifying the non-cyclic type configuration shown in FIG. 3 to the configuration shown in FIG.

[0010]

The previously proposed recursive configuration which saves memory requires changing the convolution formula, requiring two multipliers, and increasing the number of multiplications. was there.

It is therefore an object of the present invention to provide an FIR filter which can save memory in a recursive configuration and can make the multiplier and the number of multiplications equal to those of the prior art.

[0012]

According to the present invention, there is provided a shift register in which a plurality of coefficients are cyclically shifted, a plurality of IIR sections for multiplying an input digital signal by a coefficient from the shift register, and an IIR section. and a rotary selector for sequentially selecting the output section, IIR section includes a multiplier for multiplying the coefficients from the input digital signal and the shift register, and a memory for delay, the output of the output of the memory multiplier an adder for adding the and the output from the multiplier and an output from the adder, an FIR filter, characterized in that a switch selectively supplies the memory.

According to a second aspect of the present invention, there is provided an FIR filter in which the shift register includes a plurality of shift registers corresponding to a plurality of IIR sections, and supplies corresponding coefficients to each IIR section cyclically.

According to a third aspect of the present invention, at least one of the IIR sections includes a multiplier for multiplying an input digital signal by a coefficient from a shift register, a memory for delaying an output of the multiplier, and a product for multiplying an output of the memory. An adder for adding to the output of the adder, and an output from the adder and an output from the multiplier,
A switch for selectively supplying the memory,
The IR section includes a multiplier for multiplying an input digital signal by a coefficient from a shift register, a memory for delaying an output of the multiplier, and an adder for adding an output of the memory to an output of the multiplier. It is.

[0015]

When performing thinning or rate conversion, the amount of required memory can be reduced, and a frame memory for processing in the time direction or a line memory for processing in the vertical direction can be saved. Further, the IIR sections, may be provided a single multiplier can be hardware easily.

[0016]

An embodiment of the present invention will be described below with reference to the drawings. With the previously proposed cyclic configuration shown in FIG. 2, every third output is obtained. The example of the nth-order filter shown in FIG.
An output y _k including the output between them can be obtained.

In FIG. 5, reference numeral 1 denotes a shift register for providing coefficients to a multiplier cyclically. These coefficients are supplied to multipliers included in each of the n sets of IIR sections. The outputs of the n sets of IIR sections are supplied to input terminals s0, s1,..., Sn of a rotary selector (or multiplexer) S, respectively. An output y _k is _obtained from the rotary selector S. In the configuration of FIG. 5, the coefficient stored in the shift register 1 is shifted every clock, the selection of the rotary selector S is shifted every clock, and the memory of the circuit selected by the rotary selector S is reset. The output y
_k is obtained.

[0018] Here, the output in the case of the FIR type filter (n = 4) _{is, y k = a 0 x k} + a 1 x k-1 + a 2 x k-2 + a 3 x k-3
+ A ₄ × _k-4 . In this example, the contents w0 to w4 of the memories of the five IIR sections change as shown in FIG. Sand
To describe w ₀ as an example, if w ₀ is an input data sequence x ₀
Is a ₄ x ₀ , and when the input data sequence is x ₁ , a ₃ x ₀
x ₁ is applied to the memory, the input data sequence x ₂ Noto
A ₂ x ₂ is added to the memory, and the input data sequence is x
_{At 3} , a ₀ x ₄ is added to the memory. Contents w ₀ to w ₄ of the memory, the output is reset at the timing to be fetched.

As shown in FIG . 5, when input data x _k
Five sets of the memory of the IIR section the contents w ₀ ~w ₄ of
If you _{w 0, k ~w 4, k} , output data y ₄ is as follows:
Become. The timing of the output data y _4, the rotary cell
Since the collector S is connected to S0 in FIG.
Of the sections connected to the first IIR section w ₀
It is. Therefore, y ₄ is the output of w ₀ at that time . So
This is the result of multiplying the new coefficient by the new input data to the previous memory
Is added. Multiply the new coefficient by the new input data
Flip ones is a ₀ x _4, the contents of the last memory is w _0,
Because it is _3, and _{y 4 = w 0,3 + a 0} x 4. After that, the output of the memory contents w ₀ is retrieved.
Since it is reset at the timing of, the w _{0, 4} = _0. At the next timing, new input data
The multiplied result is a ₄ × ₅ , and the content of the previous memory is w
From _{0, 4,} Becomes Similarly it as below output sequence y ₅ ~y ₈
You. _{y 5 = w 1, 4 +} a 0 x 5, w 1, 5 = 0, w 1, 6 = a 4 x 6 y 6 = w 2, 5 + a 0 x 6, w 2, 6 = 0, w 2, _{7 = a 4 x 7 y 7} = w 3, 6 + a 0 x 7, w 3, 7 = 0, w 3, 8 = a 4 x 8 y 8 = w 4, 7 + a 0 x 8, w 4, 8 _{= 0, w 4, 9 =} a 4 x 9 output y _9, after memory w ₀ was stored is reset, using the data stored in the memory, y ₉ = w _{0, 3} + A ₀ x ₉ ...

Further, when a symmetric coefficient filter is configured according to the present invention, it is possible to reduce the number of cyclic loops by devising timing control. FIG. 7 shows (a) in FIG.
₀ = a _4, is obtained by a a ₁ = a _3). That is,
Output y _4, the contents of the memory at time t ₄ w ₀ and a ₀
It is given as the sum of x _4. Since the value stored in the w ₄ when this is also a ₀ x _4, if after reading the output of w ₀ to apply a ₀ x _4, memory w ₄ is not required, a set of IIR sections Can be omitted. However, it is necessary to write the read and a ₀ x ₄ value stored until t ₃ at time t _4, the high-speed operation about twice is required for the circuit.

More specifically [0021] to reset the w ₀ between t _4, then a ₀ x ₄ values Rhodes Luca from stable, or as shown in FIG. 8, the switch SW ₀ ~ SW
₃ is provided, made in the second half of the period of t ₄ to load the a ₀ x ₄ in the memory. In FIG. 8 and the block diagrams described below, a reset signal supply path for the memory is omitted.

FIG. 9 shows a calculation process when the input data sequence x _k is thinned out by 4: 1 at (n = 12, 13 taps).
X ₀ , x ₄ , x ₈ , x ₁₂ , x ₁₆ , x in the input data sequence
The values of the output data series y _k are formed at the timing of ₂₀ ,. That is, the output data sequence y _k is represented by y _k = a ₀ x _k + a ₁ x _k-1 +... + A ₁₂ x _k-12

[0023] As an example, the calculation of the time of x _{12 is, y k = w 0 + a} 0 x 12 w 1 = w 1 + a 4 x 12 w 2 = w 2 + a 8 x 12 w 0 = a 12 x 12

The calculation of the time of x _{13 is, w 1 = w 1 + a} 3 x 13 w 2 = w 2 + a 7 x 13 w 0 = w 0 + a 11 x 13

[0025] The calculation of the time of x _{14 is, w 1 = w 1 + a} 2 x 14 w 2 = w 2 + a 6 x 14 w 0 = w 0 + a 10 x 14

[0026] The calculation of the time of x _{15 is, w 1 = w 1 + a} 1 x 15 w 2 = w 2 + a 5 x 15 w 0 = w 0 + a 9 x 15

The calculation of the time of x _{16 is, y k + 1 = w 1} + a 0 x 16 w 2 = w 2 + a 4 x 16 w 0 = w 0 + a 8 x 16 w 1 = a 12 x 16

FIG. 1 shows a configuration for realizing the operation shown in FIG.
0 is shown. This is basically the same as the configuration shown in FIG. 8, but since it is a thinning filter, an arithmetic circuit is connected to the shift register 1 in which coefficients are stored for every four taps.

In the case of coefficient symmetry, that is, (a ₀
= A ₁₂ , a ₁ = a ₁₁ , a ₂ = a ₁₀ , a ₃ = a ₉ , a ₄ =
In the case of a ₈ , a ₅ = a ₇ ), the following operation is performed.

As described above, in the decimation filter, the circuit configuration is simpler in the recursive configuration than in the non-recursive configuration, and when the n-order FIR filter decimates m: 1, the output of the filter is reduced. Should be taken out every m units. Furthermore, there are various forms in the case of the cyclic structure, but in any case, the [symmetrical] filter has [n / 2] +1 multipliers, n adders, and n memories. Needed. According to the cyclic configuration, it is sufficient to take out the output every m units, so that it can be realized by [n / m] +1 sets of cyclic circuits.

Next, several examples in which the present invention is applied to conversion of a sampling rate will be described. The method described below converts the sampling rate to m: p. Not only (m> p) but also (m <p) (where
Even in the case of m レ ー ト 1), rate conversion can be performed.

In order to perform m: p sampling rate conversion, first, the rate is interpolated p times, and then thinning is performed to extract every m outputs. As a result, the sampling rate is p / m times the original rate. Now, the nth order (n
A calculation order when performing p / m rate conversion by a filter of (+1 tap) will be considered. However, a coefficient symmetric filter is assumed.

More specifically, a case will be described in which a 3 (= m): 4 (= p) rate conversion is performed by a 15 (= n) order filter. In this example, as shown in the calculation shown in FIG. 11, a process of converting the input data sequence into a quadruple rate and extracting values every third data sequence is performed. This can be realized by the configuration of FIG. The number of IIR sections is determined in consideration of how many vertical directions the shift register 1 in FIG. In general, the IIR section (the number of memories to store) is represented by the following equation using n and m.

M _s = [(n−1) / m + 1] [] is a Gaussian parenthesis expression and represents the largest integer not exceeding the number.

In the example of FIG. 11, (n = 15), and when (n = 13, 14, 15), [(n-1) / 3 + 1] = 5.

Number i of coefficient a _i of each IIR section
Decreases by 4 (= p) each time _k of x _k increases by one. Each time _j of w _{j in} each IIR section increases by one, it increases by 3 (= m).

Next, the order of the filter is set to n ₁ . When _{n 1 = m × m s n} 1 is greater than n, the value of a _n + 1 ~a _n1 to 0. When n is divisible by m, it and n ₁ and n equal.

Here, consider the coefficient α _j used in the IIR section from 0 to ms _-1 . 0th I
The coefficients a _{i of the} IR section are x ₀ , x ₁ , x ₂ ,.
, X _k , a ₀ , a _n1-p , a _n1-2p , ...
, Take the value of a _n1-kp . However, when n ₁ -kp becomes 0, the data is output via the switch S and a new data
_The value obtained by multiplying _n1 is stored in the memory by turning the switch SW sideways. When n ₁ > n, only the memory needs to be reset.

Consider the non-zero coefficient of the j-th IIR section. The coefficient of the j-th IIR section is
For x ₀ , x ₁ , x ₂ ,..., a _jm , a _jm-p , a
Take the value of _jm-2p , ... Where jm-kp is p
If it becomes smaller, it outputs via switch S and resets the memory. Then, pull the p and the n ₁ in addition to jm-kp.

The coefficient shift register 1 is set such that when n ₁ is divisible by p, a portion of a _i circulates in each IIR section. When n ₁ is not divisible by p, as in the example of FIG. 11, the order of a _i is set as shown in FIG. 12, and circulation is performed as one shift register. Then, each IIR section extracts coefficients from the middle of the shift register 1.

[0041] In the configuration of FIG. 12, a ₀ to each multiplier alpha _j,
When a ₁ , a ₂ , and a ₃ come, the signal is output. When the signal is a ₀ , the switch SW _j is tilted sideways, the product of a ₀ and x _kk is stored in a memory, and the other a ₁ , a ₂ , when the a _3,
Reset the memory after outputting.

The transfer function of the n-th order FIR filter is expressed by the following equation.

[0043]

(Equation 3)

As can be seen from FIG. 11, for the prototype filter of the above equation, a filter which performs convolution with non-zero actual data (indicated by an arrow) is as follows.
It is called a polyphase filter. When decimating to m filters, the above equation is divided into m polyphase filters. That is, the transfer function is represented by the following equation.

[0045]

(Equation 4)

The coefficients a _{im + j} decomposed by the polyphase filter are used as coefficients of each IIR section.

When n is divisible by m, for example, (n =
12) When the (4: 3) rate conversion is performed by the next filter, the processing shown in FIG. 13 is performed.
Circuit. The number of IIR sections is four. Number i of coefficients ai for each IIR sections, k of x _k is smaller by 4 (= P) in each additional one. In the case of (n = 12), since it is divisible by 4, _ai can be separated and circulated in each IIR section. Therefore, the circuit shown in FIG.
The coefficients correspond to the respective shift registers 1a, 1b,
1c and 1d, and correspond to each of a plurality of IIR sections.
And a corresponding plurality of shift registers. Shift register
First IIR section for calculating the coefficient stored in 1a
The input digital signal x _k and the shift register 1a
Multiplier alpha ₀ and stored coefficients, the output of the multiplier alpha ₀
Memory D, the multiplier alpha ₀ of an output of the memory D for delaying
An adder for adding the, from the output multiplier alpha ₀ from the adder
Switch SW0 for selectively supplying the output of
It is composed of The shift number stored in the shift register 1b
In the IIR section for calculating numbers, the input digital signal
Signal _xk and the coefficient stored in the shift register 1b
Α ₁ , memory D for delaying the output of multiplier α ₁ , memory
It is constituted by an adder for adding the output of the multiplier alpha ₁ the output of the D
Have been. Coefficients stored in shift registers 1c and 1d
The configuration of the IIR section that computes
Same as IIR section for calculating coefficient stored in b
Is configured. As can be seen from FIG.
In the section, the same fixed polyphase filter coefficient is always used. However, when n is not divisible by m, as shown in FIG. 12, after output, a different coefficient of the polyphase filter is used. In addition,
FIG. 15 illustrates the operation of the switches SW0 and S in FIG. This switch S has a 4 _k rate x
/ 3.

FIG. 16 shows a circuit at the time of general m: p rate conversion. In this circuit, the number of IIR sections is represented by the following equation. _ms = [(n-1) / m + 1]

The coefficients of each IIR section change as shown. Here, when the coefficient of the 0th polyphase filter is used, the product of x _k and a ₀ (= a _n ) is stored in the memory by traversing the switch SW _j after the output. When the coefficients of the other polyphase filters are used, the memory is reset after outputting, and the convolution by the next polyphase filter is prepared.

[0050]

According to the present invention, when thinning or rate conversion is performed, the number of memories can be reduced by using a cyclic configuration (IIR section). In particular, in the processing in the time direction, the memory is a frame memory, and in the processing in the vertical direction, the memory is a line memory,
The effect of reducing these numbers is great, and the size of the hardware can be reduced when configuring a high-order filter. Further, in the cyclic type configuration, only one multiplier is required, and there is an advantage that the configuration is simple.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of an FIR filter to which the present invention can be applied.

FIG. 2 is a block diagram of the previously proposed IIR section.

FIG. 3 is a block diagram illustrating an example of a coefficient symmetric FIR filter.

FIG. 4 is a block diagram showing an example of a coefficient symmetric FIR filter.

FIG. 5 is a block diagram of an example of an FIR filter according to the present invention.

FIG. 6 is a schematic diagram showing processing of the configuration of FIG. 5;

FIG. 7 is a schematic diagram illustrating processing of a coefficient symmetric filter.

FIG. 8 is a block diagram of an example of a coefficient symmetric filter.

FIG. 9 is a schematic diagram showing the processing of a thinning filter according to the present invention.

FIG. 10 is a block diagram showing a configuration of a thinning filter according to the present invention.

FIG. 11 is a schematic diagram illustrating processing of an example of a rate conversion filter according to the present invention.

FIG. 12 is a block diagram of an example of a rate conversion filter according to the present invention.

FIG. 13 is a schematic diagram illustrating a process of another example of the rate conversion filter according to the present invention.

FIG. 14 is a block diagram of another example of the rate conversion filter according to the present invention.

FIG. 15 is a schematic diagram illustrating a process of another example of the rate conversion filter according to the present invention.

FIG. 16 is a block diagram showing a general configuration of a rate conversion filter according to the present invention.

[Explanation of symbols]

 1 Shift register storing coefficients

Continuation of the front page (56) References JP-A-2-79615 (JP, A) JP-A-61-28221 (JP, A) JP-A-53-77438 (JP, A) JP-A-4-311159 (JP, A) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03H 17/06 671 H03H 17/06 655 H03H 17/04 613

Claims (3)

(57) [Claims] 1. A shift register in which a plurality of coefficients are cyclically shifted, a plurality of IIR sections for multiplying an input digital signal by a coefficient from the shift register, and a rotary register for sequentially selecting an output of the IIR section.
A selector for multiplying the input digital signal by a coefficient from the shift register; a delay memory; and an adder for adding an output of the memory to an output of the multiplier. An FIR filter comprising: a filter; and a switch for selectively supplying an output from the adder and an output from the multiplier to the memory. 2. The FIR filter according to claim 1, wherein the shift register comprises a plurality of shift registers corresponding to the plurality of IIR sections, and a coefficient corresponding to each of the IIR sections is circulated. FIR filter to supply. 3. The FIR filter according to claim 2, wherein at least one of the IIR sections includes a multiplier for multiplying an input digital signal by a coefficient from the shift register, and an output of the multiplier. A memory for delaying, an adder for adding an output of the memory to an output of the multiplier, and a switch for selectively supplying an output from the adder and an output from the multiplier to the memory, Another IIR section includes a multiplier for multiplying an input digital signal by a coefficient from the shift register, a memory for delaying an output of the multiplier, and an addition for adding an output of the memory to an output of the multiplier. FIR filter consisting of a filter.