JP2929807B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates the transmission side of a digital radio communication system to a digital filter used as a low-pass filter, in particular 2 ^k times (k ≧ 2)
The present invention relates to an oversampling FIR digital filter.

[0002]

2. Description of the Related Art In digital radio communication, a modulator and a demodulator each require a low-pass filter (LPF) for waveform shaping. Conventionally, an LC filter combining a coil and a capacitor has been used for this LPF, but in recent years, with the advancement of digital signal processing technology, a digital filter that performs digital filtering on a time axis has been practically used. It has become.

[0003] Digital filters include IIR (Infini
te Impulse Response) and FIR (finite ImpulseRe
Although there is a sponse type, an FIR type digital filter capable of realizing a linear phase is used as the LPF for digital wireless communication. Can be realized without adjustment. That is, the roll-off filter can be easily realized.

[0004] Here, a ^2k- fold (k ≧ 2) oversampling FIR type digital filter is basically configured as shown in FIG. That is, in FIG.
One time slot T _S (T _S = 1 / f) of the data signal 128
Shift register (291 with a delay amount of 1/2 ^k-1 of the _S)
To 294) are cascade-connected in multiple stages to sequentially delay the data signal input from the input terminal 211 by T _S / 2 ^k−1 and provide a multiplier (271 to 276) at each stage to provide a corresponding data signal. Multiplying by (2 ^k · n + 1) (n ≧ 2) corresponding tap coefficients (C ₁ , C ₂ , C ₃ ,...), The outputs of the respective multipliers are summed by an adder 306, and Is output from the output terminal 224 to the outside as a digital filter output signal 154. Note that the number of taps may be even.

In a digital filter, the higher the value of k, the easier it is to prevent harmonics in the output of the filter, but the operating speed of the circuit is limited, and the value of k cannot be increased without any change. That is, the shift register, the multiplier, the adder, etc., which are the constituent elements, have a frequency of 2 ^k−1 f _S
However, even if k = 2, the driving speed is considerably high. Therefore, a device for reducing the operation speed of the circuit is required. Conventional digital filters are configured from this point of view, and various types have been proposed (for example, Japanese Patent Application Laid-Open No. 60-77542). FIG. 11 shows a 2n-tap double oversampling FIR digital filter described in the above publication. Hereinafter, a conventional digital filter will be described with reference to FIG.

In FIG. 11, this digital filter has two delay-and-sum circuits connected in parallel to a data signal input terminal 210, each delay-and-sum circuit handles a data signal subjected to zero interpolation, A selection circuit (SEL) 243 selects the output of each delay-and-sum circuit operating in the cycle of the slot T _S.
Are switched and output at a time interval of T _S / 2.

That is, the first delay-and-sum circuit has an input stage of (n-1) shift registers (284 to 286) connected in cascade with a delay amount of one time slot T _S of the data signal. A multiplier (263 to 266) is provided in the output stage,
The corresponding data signal and tap coefficients (C ₁ , C ₃ , C ₅ ,...,
C _2n-1 ), the outputs of the respective multipliers are summed by an adder 304, and the sum is output to a selection circuit (SEL) 2
43 as one input.

The second delay-and-sum circuit is cascaded with a shift register 290 having a delay amount of 1/2 of one time slot T _S of the data signal with a delay amount of time slot T _S. (N-1) shift registers (28
7 to 289), multipliers (267 to 270) are provided at the output stage of each shift register, and the corresponding delayed data signals and tap coefficients (C ₂ , C ₄ , C ₆ ,..., C _2n ) And the outputs of the multipliers are summed up by an adder 305, and the sum is used as the other input of the selection circuit (SEL) 243.

Here, the zero interpolation means that 0 is inserted into a gap in the signal of the original speed f _S due to an increase in the speed of the sampling clock. That is, since the present example is a case of twice oversampling, the signal subjected to zero interpolation is, as shown in FIG. 10, a sampling clock corresponding to a time slot T _{S of} one bit of the original signal (FIG. of one time slot (T _S / 2) after leaving only partial portion is a signal set to 0 (FIG. 10 (b)
(C) (d)).

Therefore, in FIG. 10, if (a) is the original data signal, the first delay product-sum circuit handles the signal (b) and the second delay product-sum circuit uses The signal of (c) is handled.

The reason for performing the zero interpolation is as follows.
That is, the output frequency characteristic of the digital filter is obtained by multiplying the frequency characteristic of the input signal by the frequency characteristic of the digital filter. However, when the zero interpolation is performed, the input signal becomes an impulse for the digital filter.
This is because the frequency characteristics of the input signal can be made flat, and the frequency characteristics of the digital filter itself can be used as the output frequency characteristics.

[0012] Then, in the signal subjected to zero interpolation in the case of double oversampling, as shown in FIG. 10, a zero is inserted between the signals once. Therefore, if the taps are divided into two groups of even and odd numbers, At this time, only one set of non-zero signals is input, and all the other sets have zero input signals. That is, there is no need to perform multiplication on taps of a set where the input signal is 0. Therefore, as shown in FIG. 11, a delay-and-sum circuit for each set is formed and operated in parallel, and the output of each of the delay-and-sum circuits is switched by the selection circuit (SEL) 243 for each T _S / 2. When output, a digital filter output as double oversampling is obtained. As is clear from the above description, since each delay-and-sum circuit only needs to operate in the period of T _S , the operation speed of the circuit can be reduced.

Although the above is an example of double oversampling, the operation speed of the circuit can be reduced to f _S also in 2 ^k times oversampling using a similar configuration.

[0014]

In the above-mentioned conventional ^2k- times oversampling FIR type digital filter, the operation speed of the circuit can be reduced. However, the number of multipliers is as shown in FIG. Since the same number (2 ^k · n + 1) is required, there is a problem that it is difficult to miniaturize the circuit. That is, in a digital filter, a multiplier occupies considerable specific gravity in a circuit, but a digital filter used in digital wireless communication usually requires several tens of taps. It is desired to develop a digital filter having a configuration with reduced noise.

An object of the present invention is to provide a digital filter capable of reducing the size of a circuit and suitable as a low-pass filter used on the transmission side of a digital radio communication system.

[0016]

In order to achieve the above object, a digital filter according to the present invention has the following configuration. That is, the digital filter according to the first aspect of the invention operates in parallel with 2 ^{k -1} operating in parallel with the same operation clock signal (speed f _s ).
Basic digital filters [number of taps (n + 1):
n ≧ 2], and ^2k times (k ≧ 2: an integer) the (2 ^k · n + 1) tap coefficients (the number of bits m) originally possessed by the oversampling FIR type digital filter are continuously adjacent to each other. ^{A set of k} or less tap coefficients [2 ^k−1 ·
(N + 1) divided into pieces of the set, the ² k-1 · (n + 1)
At least one tap included in each set of tap coefficients
Are multiplied by the same data signal.
The sum of the tap coefficients for the calculation and the digit
2 ^k−1 (n + 1) integrated tap coefficients (number of bits m) formed taking into account the symmetry of the tap coefficients of the Tal filter
And 2 ^k-1 elementary digital filters, given by:
Rate ² x _f S XOR (x = 1,2, ......, k -1) is the (k-1) pieces one operation clock signal of the control clock signal and speed _{f S} of A selection signal forming circuit for forming (k-1) selection signals;
Each output of ^k-1 basic digital filters is referred to as (k
-1) a first selection circuit for outputting a number of selection signals rearranged operated by one row of the signal (speed 2 ^{k f} _S);
Wherein the 2 ^k-1 pieces of basic digital filter
Each of the (n + 1) taking the product of the individual with a corresponding allocated from the <br/> integrated tap coefficients as a tap coefficient and the input data signal (the number of bits l) (n + 1) multipliers and; shift Two delay adder circuits in which registers and adders are alternately arranged in series, wherein each output from the first to (n + 1) th multipliers of the (n + 1) multipliers is 1 A first delay / addition circuit for forming a first signal sequentially added while being delayed by a time slot T _S , and delaying each output from the (n + 1) th to the first multiplier by a time slot T _S A second delay adding circuit for forming a second signal sequentially added while the second delay adding circuit;
Each output signal of the first and second delay addition circuits is set to a period T
_And a second selection circuit that alternately switches and outputs the selected signal according to the selection signal of _S.

The digital filter according to the second aspect of the present invention
A set of (4n + 1) (n ≧ 2) tap coefficients (number of bits m) originally included in a 4 × oversampling FIR digital filter and a set of four or less adjacent tap coefficients [(2n + 2) sets ] And [(2n +
2) sets of tap coefficients of at least 1
Tap coefficients for the same data signal
The sum of the tap coefficients to be multiplied and configured
(2n + 2) integrated tap coefficients (number of bits m) formed taking into account the symmetry of the tap coefficients of the digital filter
(2n + 2) multipliers which take the product of the corresponding one assigned from, and the input data signal (number of bits l);
A shift register and an adder are arranged in series alternately in a series of four delay-and-addition circuits, and each of the (2n + 2) multipliers outputs respective outputs from the first to (n + 1) -th multipliers. A first delay / addition circuit that forms a first signal sequentially added while being delayed by one time slot T _{S, and} outputs each output from the (n + 1) th to first multipliers by 1
A second (n + 2) th delay adding circuit for forming a second signal sequentially added while being delayed by a time slot T _S,
Each output from the 2nd to the (2n + 2) th multiplier is 1
Third delay adding circuit for forming a third signal obtained by sequentially adding while delayed by the time slot T _S, and the (2n
+2) th from the (n + 2) -th 1 each output to multiplier timeslots T _S by a fourth delay adding circuit for forming a fourth signal obtained by sequentially adding while delaying; the first, second , A third signal and a fourth signal by a period T _S and a period T
A selection circuit that alternately switches and outputs the selection signals according to two columns of selection signals of _S / 2.

[0018]

Next, the operation of the digital filter of the present invention configured as described above will be described. In the present invention, the transmission side 2
Focusing on the property of ^k- times oversampling and the symmetry of the tap coefficients of the roll-off filter, the number [2] obtained by integrating the number of tap coefficients from the original number (2 ^k · n + 1)
^k-1 · (n + 1)], and the same speed (f
_Let the tap coefficients of 2 ^{k -1} basic digital filters operating in parallel in _S ). Each basic digital filter includes a multiplier, two delay addition circuits having different delay addition directions,
Although it is composed of a selection circuit as an output circuit, since the number of taps of each basic digital filter is (n + 1), the total number of multipliers is 2 ^k−1 · (n + 1). Conventional (Fig. 1
2, FIG. 11) requires (2 ^k · n + 1) multipliers, and when the ratio between the two is taken, Equation 1 is obtained.
When n is large, the number of multipliers is reduced to about 1 / regardless of the value of k.
It can be reduced to 2.

[0019]

(Equation 1)

Note that the digital filter of the second invention is
This is composed of two basic digital filters of the first invention.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a 2 ^k oversampling F of the present invention.
1 shows an IR type digital filter. This filter is
2 ^{k -1} basic digital filters (1
２2 ^k−1 ) and (k−1) exclusive OR circuits (250
251) and a (first) selection circuit (SEL) 240.

2 ^{k -1} basic digital filters (1 to 1)
2 ^k-1 ), which will be described in detail later, share the data input terminal 201 and the operation clock input terminal 202, operate in parallel with the same operation clock signal (speed f _S ) 122, and The signal 121 is processed in parallel, and the output signals (130 to 133) are selected by the selection circuit (SEL) 240.
Give to.

(K-1) exclusive OR circuits (250
251), one input terminal is the operation clock input terminal 2
02 are commonly connected, the other input end (k-1) are connected to corresponding ones of the pieces of control clock input terminal (203-204), the operating clock signal (speed f _S) 122 and (k-1) Control clock signals [speed 2 ^x f _S (x =
1, 2,..., K−1)] (123 to 124), and (k−1) selection signals (134 to 135) are formed and selected. To the circuit 240. That is, (k-1) exclusive OR circuits (25
0 to 251) constitute a selection signal forming circuit as a whole.

The selection circuit (SEL) 240 has (k-1)
Number of selection signals (134-135) according to 2 ^k-1 pieces of output signals of the basic digital filter (1 to 2 ^k-1) (130
And rearranged operations to 133) to form a row of data signals (speed 2 ^k f _S) 150, transmitted from the output terminal 220 to the outside.

The basic digital filter is configured as shown in FIG. 2, for example. This basic digital filter is a double oversampling FIR type filter, and shows a configuration when n = 2. Since the 2 × oversampling FIR filter originally requires (2n + 1) taps, if n = 2, 2n
Although + 1 = 5 taps are required, this is realized by n + 1 = 3 taps.

That is, this basic digital filter has 3
Multipliers (21, 22, 23), two delay addition circuits (60a, 60b), and a (second) selection circuit (SE)
L) 50 basically.

In FIG. 2, a data signal (number of bits 1) 101 input from an input terminal 10 has three multipliers (2
1, 22, 23) in parallel, where the product of the three tap coefficients (number of bits m) _dj (j = 1, 2, 3) and the corresponding ones is obtained.

Here, the three tap coefficients _dj are set based on 2n + 1 = 5 tap coefficients (the number of bits m), which are originally required but not more than two successive tap coefficients, although the setting basis will be described later. When there are a plurality of tap coefficients belonging to the set in each set [n + 1 = 3 sets], a sum of them is taken as one tap coefficient, and a tap coefficient belonging to the set is obtained. Is an integrated tap coefficient having the number of bits m, which is formed by using it as a new one as it is.

Then, three multipliers (21, 22, 2)
The output of 3) is two delay addition circuits (60a, 60b)
Given to. The first delay addition circuit 60a includes a shift register (40, 41) and an adder (30, 31). The second delay addition circuit 60b includes shift registers (42, 43) and adders (32, 33). Here, each of the four shift registers (40 to 43) has a delay amount of one time slot T _S of the data signal 101.

That is, two delay addition circuits (60a, 60
FIG. 3B shows an example in which shift registers and adders are alternately arranged. The first delay / addition circuit 60a converts each output from the first multiplier 21 to the third multiplier 23 into one time slot. A first signal 111 that is sequentially added while being delayed by T _S is formed (FIG. 3A), and the second delay and addition circuit 60b performs processing from the third multiplier 23 to the first multiplier 21. Are sequentially added while delaying each output by one time slot T _S to form a second signal 112.
(B)) are applied to the selection circuit 50, respectively.

The selection circuit 50 has two input signals (11
1, 112) are alternately switched such that the output signal 111 is taken out in the first half and the output signal 112 is taken out in the second half by the selection signal 102 (FIG. 3 (c)) having the period T _S applied to the input terminal 11. And outputs it as an output signal 103 (FIG. 3D) from the output terminal 13 to the outside.

Next, the grounds for the configuration shown in FIG. 2 will be described with reference to FIG.
This will be described with reference to FIG. FIG. 12 shows that 2 ^k
Since this is the basic form of the double oversampling FIR digital filter, the configuration of the double oversampling FIR filter is analogized from this basic form. That is, in the conventional configuration of the 5-tap double oversampling FIR type filter, the frequency of the operation clock is 2 f _S , but T _S
/ 4 shift registers having second delay amount are cascaded, a multiplier provided in the output stage and the input stage, T _S / 2 one by delayed input data signal a _i (-∞ ≦ _i ≦ + ∞) is multiplied by the corresponding _{one of the five} tap coefficients (C _{1 to} C ₅ ), and the outputs of the five multipliers are summed. The input data signal a _i and the tap coefficient (C ₁ to
Time relationship between the C ₅₎ is, for example, as shown in FIG.

FIG. 8A shows the time relationship between the input data signal a and the tap coefficients (C _{1 to} C ₅ ) at time t ₁ .
Assuming that it is as shown in 1), at time t ₂ , which is one unit time after the operation clock of frequency 2f _S , FIG.
Then, at time t ₃ and time t ₄ , FIG.
3) indicates that the same (A4), the product-sum b _i of the tap coefficients and the data signal at each time (-∞ ≦ i ≦ + ∞) is shown that is as shown in FIG. 8 (B) I have.

[0034] Here, focusing on the relationship between the tap coefficient input data signal in Fig. 8 (Al to A4), the filter output of the transmitting side, C ₅ and C _4, C ₃ and C ₂ are the same 1
It can be seen that two data signals can be defined, and C ₄ and C ₃ , and C ₂ and C ₁ can be defined in two forms, that is, one data signal. This is the basis for setting the integrated tap coefficient.

That is, since the two tap coefficients correspond to the same one data signal, the two tap coefficients having a fixed relationship from the beginning can be added to one integrated tap coefficient by the setting method described above. , The number of taps, that is, the number of multipliers can be reduced from five to three in the above example.

Specifically, three integrated tap coefficients d
_j is C ₅ + C ₄ = d ₁ , C ₃ +
Set C ₂ = d ₂ and C ₁ = d ₃ .

It should be noted here that when used as a roll-off filter, C ₅
= C ₁ , C ₄ = C ₂ , and d ₁ = C ₁ + C ₂ , d ₂ =
C ₃ + C ₄ and d ₃ = C ₅ .

[0038] Then, the output signal b in relation to the input data signal a _i and the integrated tap coefficients d _j which is set in this way
Expressing _i, the output signal b _i is, d ₁ from the temporally preceding data signal and correspond to d _1, d _2, d ₃ in sequence, in order from the data signal after temporally, d _2, d It can be seen that those corresponding to ₃ appear alternately.

From the above, in the case of a 5-tap transmission-side roll-off filter, three types of multipliers, a circuit for delay-adding the output of each multiplier from the data input side, and a delay-addition circuit for the output side If there is a circuit that performs the switching, and a selection circuit that alternately switches and outputs the two series of outputs of the two delay addition circuits every T _S / 2, a digital filter of double oversampling can be configured. FIG. 2 is configured in this way, and as shown in FIG. 3D, an output having exactly the same contents as the output of the conventional filter (FIG. 8B) is obtained. Operating speed of the circuit other than the output stage of the selection circuit 50 are all f _S.

Although the above-described digital filter of twice oversampling can be used alone, the present invention provides a digital filter of four times or more oversampling by arranging 2 ^{k -1} digital filters in parallel, that is, FIG. 2 shown in
It is intended to obtain a ^k- fold oversampling FIR digital filter. However, it should be noted that the integrated tap coefficient is not set as the above-described double oversampling digital filter, but is set as a ^2k- times oversampling digital filter.

That is, in a digital filter of 2 ^k times oversampling, 2 ^{k −1} basic digital filters [the number of taps (n + 1): n ≧ 2] are 2 ^k times (k ≧ 2).
(2: integer) A set of 2 ^k or less tap coefficients adjacent to (2 ^k · n + 1) tap coefficients (number of bits m) which the oversampling FIR digital filter originally has [2 ^k−1 · (N + 1) sets], and when there are a plurality of tap coefficients belonging to the set in each set, 2 ^{k -1} (n + 1) pieces are formed by, for example, taking the sum and forming a new tap coefficient. Are provided. Hereinafter, the configuration of the 2 ^k times oversampling filter will be described by taking a 4 × oversampling FIR type digital filter with k = 2 as an example.

As shown in FIG. 4, the quadruple oversampling FIR type digital filter includes two basic digital filters (234 and 235) and a selection circuit (SE).
L) 241 and an exclusive OR circuit 252 as a selection signal generation circuit. Here, since the two basic digital filters (234, 235) each have three taps in the above example, the number n of taps is 4n + 1.
That is, 9 taps with 2 = 2 can be realized by 6 taps.

In FIG. 4, the two basic digital filters (234, 235) share the data input terminal 205 and the operation clock input terminal 206, respectively, and have the same operation clock signal (speed f _S ) 127 (FIG. 5). (C))
Operate in parallel to process the same data signal 126 in parallel, and output signals (138, 139) to the selection circuit (SE).
L) 241 (FIGS. 5A and 5B).

The exclusive OR circuit 252 has one input terminal connected to the operation clock input terminal 206, the other input terminal connected to the control clock input terminal 207, and controls the operation clock signal (speed f _S ) 127 and the control signal. Clock signal (speed 2
f _S ) 128 (FIG. 5D) is exclusive-ORed to form a selection signal 155 (FIG. 5E), which is supplied to the selection circuit 241.

The selection circuit (SEL) 241 outputs the selection signal 1
When 55 is at the high level, the basic digital filter 2
34, and the output signal 139 of the basic digital filter 235 is selected when the output signal 138 is at the low level.
The output signals (138, 139) of (35) are rearranged to form one column of data signals (speed 4f _S ) 151 (FIG. 5 (f)), and transmitted from the output terminal 221 to the outside.

FIG. 6 shows an example of a specific configuration of the 4 × oversampling FIR digital filter shown in FIG. Hereinafter, a method of setting the integrated tap coefficient and a specific operation of the circuit will be described with reference to FIG. 6, and it will be shown that the general configuration of FIG. 1 can be obtained.

In FIG. 6, the selection circuit (50) for each basic digital filter and the selection circuit (241) for selecting the output of each basic digital filter are combined into a single selection circuit (SEL) 91. An exclusive OR circuit (252) is housed therein. That is, an operation clock signal (selection signal 60) having a speed f _S (period T _S ) is input to the input terminal 21.
6) is applied, and the speed 2 f _S (period T _S ) is applied to the input terminal 22.
/ 2) control clock signal (selection signal 607).

In FIG. 6, a data signal (number of bits 1) 601 input from a data input terminal 20 is input to six multipliers (61 to 66) in parallel, where six tap coefficients ( The number of bits m) is multiplied by the corresponding one of _dj (j = 1, 2,..., 6), and the six multipliers (61 to 66) are divided into two by three. . For one of the three multipliers (61 to 63), a shift register (7
1, 72) and adders (81, 82), and a second delay adder circuit including shift registers (73, 74) and adders (83, 84). (The above corresponds to one basic digital filter 234), and for the other three multipliers (64 to 66), shift registers (75, 76) and adders (85, 8) are used.
6), and a fourth delay / addition circuit including shift registers (77, 78) and adders (87, 88).
(The above corresponds to the other basic digital filter 235).

Then, eight shift registers (71 to 7)
8) each has a delay amount of one time slot T _S of the data signal 601. The four delay addition circuits are obtained by alternately arranging shift registers and adders in series, as described above. Operate. That is, the first delay / addition circuit includes the first multiplier 61 to the third multiplier 63
To form a first signal 602 which is sequentially added while delaying each output by one time slot T _S , and the second delay adding circuit includes a third multiplier 63 to a first multiplier 61 Are sequentially added while delaying each output of the second signal by one time slot T _S to form a second signal 603,
Forms a third signal 604 obtained by sequentially adding the outputs from the fourth multiplier 64 to the sixth multiplier 66 while delaying them by one time slot T _S. The delay adding circuit sequentially adds the outputs from the sixth multiplier 66 to the fourth multiplier 64 by one time slot T _S while adding a fourth signal 605.
To form

The selection circuit (SEL) 91 is taken out by switching the four input signals (602-605) alternately by a selection signal 606 and the period T _S / 2 of the selection signal 607 in the period T _S, the output signal thereof Output terminal 70 as 608
3 to the outside.

Here, the integrated tap coefficient d _j is 4 · n + 1 = 9 tap coefficients (the number of bits m) originally required.
Are successively set to four or less tap coefficients (2 (n +
1) = 6 sets), and in each set, when there are a plurality of tap coefficients belonging to the set, the sum thereof is taken, and when one tap coefficient belongs to the set, it is left as it is. It is composed of 2 (n + 1) = 6 tap coefficients formed as one new tap coefficient.

Next, the grounds for adopting the configuration of FIG. 6 by the same method as that described for the basic digital filter will be described. 9 derived from the basic form of the 2 ^k times oversampling FIR type digital filter shown in FIG.
Conventional structure of 4 times oversampling FIR filter taps, the frequency of the operation clock is 4f _S,
Eight shift registers having a delay amount of T _S / 4 are connected in cascade, multipliers are provided at the input stage and the output stage, and input data signals a _i (−∞ ≦ i) sequentially delayed by T _S / 4. ≤ + ∞)
Is multiplied by the corresponding _{one of the nine} tap coefficients (C _{1 to} C ₉ ), and the outputs of the nine multipliers are summed. Then, the time relationship between the input data signal a _i and the tap coefficients (C _{1 to} C ₉ ) from the time t ₁ to the time t ₅ is as shown in FIG. 9A, for example. Sum of products b _i (−∞ ≦ i
<+ ∞) is as shown in FIG. Although the time direction of the signal is opposite to that in FIG. 8, it is not essential.

Then, as shown in FIG. 9A, C _{1 to} C ₄ and C _{5 to} C ₈ correspond to one and the same data signal in the filter output on the transmission side, and C _{2 to} C ₅ and C ₆ to C _{6 9} corresponds to one and the same data signal, and C _{3 to} C ₆ , C _{7 to} C ₉
Correspond to one and the same data signal, and C _{1 to} C ₃ , C ₄
~C _7, C _8, C ₉ corresponds to one of the same data signal, there are four aspects of.

That is, as described above, since a plurality of tap coefficients correspond to one and the same data signal, a plurality of tap coefficients which have a fixed relationship from the beginning are integrated into one.
In other words, the number of multipliers can be reduced. In the present embodiment, from the above four aspects, six integrated tap coefficients d _j (j = 1, 2, 3, 4, 5,
6) can be defined. This is the matter described above. This allows the number of multipliers to be reduced from nine to six.

[0055]

(Equation 2)

[0056]

(Equation 3)

[0057]

(Equation 4)

[0058]

(Equation 5)

[0059]

(Equation 6)

[0060]

(Equation 7)

When used as a roll-off filter, tap coefficients have symmetry, so that C ₁ = C ₉ ,
C ₂ = C ₈ , C ₃ = C ₇ , and C ₄ = C ₆ . Therefore,
The above Equations 2 to 7 become the following Equations 8 to 13.

[0062]

(Equation 8)

[0063]

(Equation 9)

[0064]

(Equation 10)

[0065]

[Equation 11]

[0066]

(Equation 12)

[0067]

(Equation 13)

[0068] Then, the output b _i of a conventional digital filter becomes as in FIG. 9 (b), expressed this in new integrated tap coefficients d _j, so Equation 14 the 18.

[0069]

[Equation 14]

[0070]

(Equation 15)

[0071]

(Equation 16)

[0072]

[Equation 17]

[0073]

(Equation 18)

That is, since b ₅ is obtained by delaying b ₁ by one time slot, b _{1 to} b ₄ are repeated. Accordingly, there are four output signals b ₁ , b ₂ , b ₃ , and b ₄ , which can be formed by delay-adding the outputs of the three multipliers. And b ₁ and b
_4, focusing on b ₂ and b ₃ of the relationship, both tap coefficient corresponds to the reverse direction to the same data signal.
Therefore, the four output signals are generally represented by b _4i , b _{4i + 1} ,
If b _{4i + 2} and b _{4i + 3} are described, the signal formation of the output signals b _{4i + 1} and b _4i , and the signal formation of the output signals b _{4i + 3} and b _{4i + 2} are respectively performed by the outputs of the three multipliers. Can be performed by a circuit that adds delay from the data input side and a circuit that adds delay from the data output side.

Then, the four output signals (b _4i , b _{4i + 1} ,
b _{4i + 2} , b _{4i + 3} ) are switched and output in a fixed order at intervals of a period T _S / 4, so that the period T _S is the same as the conventional filter.
The digital filter output of the original 9 tap 4 times oversampling can be obtained with the operation speed of
The configuration shown in FIG. 6, and therefore, the configuration shown in FIG.

That is, referring to FIG. 6, in one of the three multipliers (61 to 63), the first delay addition circuit outputs the output signal b.
_A first signal 602 corresponding to _{4i + 1} is output, a second delay / addition circuit outputs a second signal 603 corresponding to the output signal b _4i , and the other three multipliers (64 to At 66), the third delay / addition circuit outputs a third signal 604 corresponding to the output signal b _{4i + 3} , and the fourth delay / addition circuit outputs a signal 605 corresponding to the output signal b _{4i + 2.} A selection circuit (SEL) 91 selectively outputs the outputs of the four delay addition circuits.

Since the data signal 601 is not a signal subjected to zero interpolation (FIG. 7A), the outputs (602, 603, 604, 605) of the four delay addition circuits are shown in FIG.
(B). Then, as shown in FIG. 7C, the selection signal 606 is a signal having a period T _S , and the selection signal 607 is a signal having a period T _S / 2. Therefore, the outputs (602, 603, 604, 605) of the four delay addition circuits are connected to the selection circuit 91 in the relationship shown in FIG. 6 (the order of 602, 605, 604, 603), and the selection circuit 91 606
, The first and third signals from the top are alternately selected, and the selection signal 607 is the second and fourth signals from the top.
If the third signal is alternately selected, the output signal 608 of the digital filter becomes as shown in FIG. This is shown in FIG.
The signal is exactly the same as that shown in FIG.

As can be easily inferred from the above description,
Extending the idea of a 4 × oversampling FIR digital filter, 2 ^k times oversampling FI
An R-type digital filter can be configured. The circuit configuration is as follows.

First, the number of taps of each basic digital filter is 2 ^k times (k ≧ 2: integer) oversampling F
The IR digital filter originally has (2 ^k · n +
1) Two tap coefficients (number of bits m) are successively
^Since the number is divided into ^k or less tap coefficient sets,
2 ^k sets and less than 2 ^k sets are respectively n sets and 1 set, or (n−1) sets and 2 sets, and in any case (n +
1) It becomes pieces.

Further, since the total number of multipliers is the number of sets of 2 ^k , there are 2 ^k ways of selecting the end tap coefficient d ₁ (a 1 to 2 ^k configuration can be made). Multiplying the number of taps (n + 1) of the basic digital filter by 2 ^k · (n +
1) The same number is 2 due to the symmetry of the tap coefficient.
The number of times is 2 ^k−1 · (n + 1).

Therefore, the number of basic digital filters is
Since the number of multipliers may be divided by the number of taps of the basic digital filter, the number is 2 ^k−1 .

Since the output of each basic digital filter has a regularity, the selection circuit may be basically configured as shown in FIG. However, the number of selection signals is log ₂ 2 ^k-1 = k because the number of basic digital filters is 2 ^k-1.
It becomes -1.

FIG. 1 is configured as described above. The basic digital filters (1 to 2 ^k-1 ) have the same configuration, and have (n + 1) taps,
Operating speed is f _S. From the relationship of Equation 1, when n is large, the number of multipliers can be reduced to about half regardless of the value of k.

In the present invention, the input data signal of the digital filter is not zero-interpolated. for that reason,
Although the frequency characteristics of the input signal appear in the output frequency characteristics of the filter, the effect can be eliminated by adding the inverse characteristics of the frequency characteristics of the input signal to the frequency characteristics of the filter.

[0085]

As described above, according to the digital filter of the present invention, the number of tap coefficients is determined by focusing on the ^2k- times oversampling property of the transmitting side and the symmetry of the tap coefficients of the roll-off filter. Is the original number (2 ^k
(n + 1) is reduced to the integrated number [2 ^k−1 · (n + 1)] and the number of multipliers is set to 2 ^k−1 · (n + 1).
The number of multipliers can be greatly reduced, and there is an effect that a digital filter that can reduce the size of a circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a 2 ^k- times oversampling FIR digital filter according to the present invention.

FIG. 2 is a configuration block diagram of a basic digital filter in FIG.

FIG. 3 is an operation time chart of a basic digital filter.

FIG. 4 is a block diagram showing a basic configuration of a 4 × oversampling FIR digital filter.

FIG. 5 is an operation time chart of the digital filter of FIG. 4;

FIG. 6 is a specific configuration block diagram of a 4 × oversampling FIR digital filter.

FIG. 7 is an operation time chart of the digital filter of FIG. 6;

FIG. 8 is an operation time chart of a conventional 2 × oversampling FIR digital filter.

FIG. 9 is an operation time chart of a conventional 4 × oversampling FIR digital filter.

FIG. 10 is an explanatory diagram (0 interpolation explanatory diagram) of an input signal of a conventional 2 × oversampling FIR digital filter in which the operation speed is reduced.

FIG. 11 is a block diagram showing a configuration of a conventional 2 × oversampling FIR digital filter in which the operation speed is reduced.

FIG. 12 is a block diagram showing a basic configuration of a conventional 2 ^k times oversampling FIR digital filter.

[Explanation of symbols]

1-2 ^k-1 basic digital filter 21-23 multiplier 30-33 adder 40-43 shift register 50 selection circuit 60a delay addition circuit 60b delay addition circuit 61-66 multiplier 71-78 shift register 81-88 adder 91 selection circuit 234 to 235 basic digital filter 240 to 241 selection circuit 250 to 252 exclusive OR circuit

Claims (2)

(57) [Claims] 1. 2 ^k−1 basic digital filters [number of taps (n + 1): n ≧ 2] that operate in parallel with the same operation clock signal (speed f _s ), and are 2 ^k times (k ≧ 2: integer) oversampling FIR digital filter is inherent ⁽² k · n + 1) number of tap coefficients (a ^{2 k} or fewer tap coefficients adjacent successively the number of bits m) set ^{[2 k-1}・ (N + 1) sets]
For each set of 2 ^k−1 · (n + 1) tap coefficients
At least one tap coefficient included in
The sum of tap coefficients that perform multiplication on the data signal
Of the tap coefficients of the digital filter to be configured
2 ^k-1 (n + 1) integrated tap coefficients (number of bits m) given by taking into account the symmetry ; 2 ^k-1 basic digital filters; and 2 ^x f _S (x = 1,
2, ......, k-1) is a (k-1) pieces of the control clock signal and speed takes the exclusive OR of the one of the operation clock signal of f _S (k-1) pieces of selection signals A selection signal forming circuit for forming a signal; and rearranging the outputs of the 2 ^k-1 basic digital filters by the (k-1) selection signals to produce a row of signals (speed 2 ^kf _S ). a first selection circuit for outputting a; wherein the each of the 2 ^k-1 groups <br/> the digital filter, the (n + 1) number of allocated from the integrated tap coefficient as the tap coefficient
Are taking the product and (n + 1) multipliers and corresponding as the input data signal (the number of bits l); a two delay adding circuit in series alternately arranged with a shift register and an adder, said (n + 1) of the multipliers, a first delay for forming a first signal obtained by sequentially adding while delaying the output by one time slot T _S from the first to the (n + 1) th multiplier An adder circuit, a second delay adder circuit for forming a second signal obtained by sequentially adding the outputs from the (n + 1) th to the first multiplier by one time slot T _S to form a second signal; and a second selection circuit for outputting alternately switching the selection signal of the output signals period T _S of the second delay adding circuit; a digital filter, characterized in that it comprises a. 2. A 4 × oversampling FIR type digital filter (4n + 1) (n ≧ 2)
2) the tap coefficient (the number of bits m) is divided into four or less consecutive sets of tap coefficients [(2n + 2) sets],
Included for each set of tap coefficients of [(2 n + 2) sets]
At least one tap coefficient is assigned to the same data
The sum of the tap coefficients that perform multiplication on the data signal,
And the symmetry of the tap coefficients of the digital filter to be constructed
(2n + 2) multipliers which take the product of the input data signal (bit number 1) and the corresponding one assigned from the (2n + 2) integrated tap coefficients (bit number m) formed taking into account the characteristics ; shift Four delay addition circuits in which registers and adders are alternately arranged in series, wherein (2n +
2) First delay addition for forming a first signal obtained by sequentially adding the outputs from the first to (n + 1) th multipliers by one time slot T _S among the multipliers Circuit, a second delay-and-addition circuit for forming a second signal obtained by sequentially adding each output from the (n + 1) -th to the first multiplier while delaying the output by one time slot T _S , a (n + 2) -th circuit the the first (2n + 2) th outputs of up to multiplier third delay adding circuit for forming a third signal obtained by sequentially adding while delayed by one time slot T _S, and from the (2n + 2) -th from (n + 2 A) a fourth delay-and-addition circuit for forming a fourth signal obtained by sequentially adding the outputs up to the first multiplier while delaying each output by one time slot T _S ; and the first, second, third, and fourth circuits. Each signal has a period T _S and a period T A selection circuit that alternately switches and outputs the signals according to two columns of selection signals of _S / 2.