JPH0555875A - Digital filter - Google Patents

Abstract

PURPOSE:To obtain a digital filter whose circuit size is contracted. CONSTITUTION:Plural reference digital filters (1 to 2<k-1>) execute parallel operation by the same operation clock signal (speed fs) 122 and process the same data signal 121 in parallel. On the other hand, (k-1) exclusive OR circuits 250, 251 respectively find out exclusive OR operation between the signal 122 and a corresponding control clock signal out of (k-1) control clock signals [speed 2<x>fs (x=1 to (k-1)] 123, 124 and form (k-l) selection signals 134, 135. A selection circuit(SEL) 240 executes the rearrangement operation of 2<k-1> output signals 130 to 133 to form a data signal (speed 2<k>fs) 150 and sends the data signal 150 from an output terminal 220 to the external. In this case, a reference digital filter has (n+1) taps and a new integrated tape coefficient including the tap coefficient of a conventional digital filter is applied.

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates the transmission side of a digital radio communication system to a digital filter used as a low-pass filter, in particular 2 ^k times (k ≧ 2)
The present invention relates to an oversampling FIR type digital filter.

[0002]

2. Description of the Related Art In digital wireless communication, a low pass filter (LPF) for waveform shaping is required for each of a modulator and a demodulator. An LC filter in which a coil and a capacitor are combined has been conventionally used for this LPF, but in recent years, with the progress of digital signal processing technology, a digital filter for digitally filtering on a time axis has been put to practical use. It started to come.

IIR (Infini
te Impulse Response) type and FIR (finite ImpulseRe
There is a sponse type, but an FIR type digital filter that can realize a linear phase is used as an LPF for digital wireless communication, which makes it difficult to realize an LC filter with an amplitude characteristic and a delay characteristic at a low roll-off rate. Can be realized without adjustment. That is, the roll-off filter can be easily realized.

Here, a 2 ^k times (k ≧ 2) oversampling FIR type digital filter is basically constructed as shown in FIG. That is, in FIG.
One time slot T _S of the data signal 128 (T _S = 1 / f
Shift register (291 with a delay amount of 1/2 ^k-1 of the _S)
To 294) are cascaded in multiple stages to sequentially delay the data signal input from the input terminal 211 by T _S / 2 ^k−1 , and a multiplier (271 to 276) is provided in each stage to generate a corresponding data signal. (2 ^k · n + 1) (n ≧ 2) tap coefficients (C ₁ , C ₂ , C ₃ , ...) Corresponding ones are multiplied, and the output of each multiplier is summed by an adder 306, Is output as a digital filter output signal 154 from the output terminal 224 to the outside. The number of taps may be even.

In a digital filter, the higher the value of k, the easier it is to block harmonics of the filter output, but the operating speed of the circuit is limited, and the value of k cannot be increased as it is. That is, the components such as the shift register, the multiplier, and the adder have a frequency of 2 ^k-1 f _S
However, even if k = 2, the speed is considerably high. Therefore, it is necessary to devise to reduce the operating speed of the circuit. Conventional digital filters are constructed from such a viewpoint, and various types have been proposed (for example, Japanese Patent Laid-Open No. 60-77542). FIG. 11 shows the digital filter of the 2n tap double oversampling FIR type described in the above publication. Hereinafter, a conventional digital filter will be described with reference to FIG.

In FIG. 11, this digital filter has two delay product-sum circuits connected in parallel to a data signal input terminal 210, and each delay product-sum circuit handles a data signal subjected to zero interpolation for one time. The output of each delay product sum circuit operating in the cycle of the slot T _S is selected by the selection circuit (SEL) 243.
Is to be switched and output at a time interval of T _S / 2.

That is, the first delay product-sum circuit has a delay amount of one time slot T _S of the data signal, and is the input stage of (n-1) shift registers (284 to 286) connected in cascade. Multipliers (263 to 266) are provided in the output stage,
Corresponding data signals and tap coefficients (C ₁ , C ₃ , C ₅ , ...,
C _{2n -1} ) and the corresponding ones are summed in the adder 304, and the sum is added to the selection circuit (SEL) 2
43 is one of the inputs.

Further, the second delay product-sum circuit has a shift register 290 having a delay amount of 1/2 of one time slot T _S of the data signal and a cascade connection having a delay amount of the time slot T _S. (N-1) shift registers (28
Prefixed to 7-289), a multiplier in the output stage of each shift register (267-270) is provided, corresponding delayed data signal and the tap coefficients _{(C 2, C 4, C} 6, ......, C 2n) Of the respective multipliers are summed, and the outputs of the respective multipliers are summed by the adder 305, which is used as the other input of the selection circuit (SEL) 243.

Here, the zero interpolation is to insert 0 in the gap due to the increase in the speed of the sampling clock in the signal of the original speed f _S. That is, since the present example is a case of double oversampling, the zero-interpolated signal is, as shown in FIG. 10, a sampling clock for the original signal 1-bit time slot T _S (FIG. 10A). Is a signal in which only one time slot (T _S / 2) is left and the latter part is set to 0 (FIG. 10 (b)).
(C) (d)).

Therefore, assuming that (a) is the original data signal in FIG. 10, the signal of (b) is handled by the first delay product sum circuit, while the signal of (b) is handled by the second delay product sum circuit. The signal of (c) is handled.

The reason for performing the zero interpolation is as follows.
That is, the output frequency characteristic of the digital filter is obtained by multiplying the frequency characteristic of the input signal by the frequency characteristic of the digital filter. However, if zero interpolation is performed, the input signal becomes an interval for the digital filter.
This is because the frequency characteristic of the input signal can be made flat and the frequency characteristic itself of the digital filter can be used as the output frequency characteristic.

As a result, the zero-interpolated signal in the case of double oversampling has a zero between the signals as shown in FIG. 10, so the taps can be divided into two groups, an even number and an odd number. Only one set is input with a signal that is not 0 at the time point, and all other input signals are 0. That is, it is not necessary to perform multiplication with a tap having a set of 0 input signals. Therefore, as shown in FIG. 11, a delay product-sum circuit for each set is created and operated in parallel, and the output of each delay product-sum circuit is switched by the selection circuit (SEL) 243 for each T _S / 2. If output, a digital filter output as double oversampling can be obtained. As is clear from the above description, each delay-sum product circuit may be operated in the cycle of T _S , so that the operating speed of the circuit can be reduced.

The above is an example of 2 × oversampling, but the operating speed of the circuit can be reduced to f _S even in 2 ^k × oversampling using a similar configuration.

[0014]

In the above-mentioned conventional 2 ^k times oversampling FIR type digital filter, the operating speed of the circuit can be reduced, but the number of multipliers is the basic structure of the digital filter shown in FIG. Therefore, there is a problem that it is difficult to miniaturize the circuit because the same number (2 ^k · n + 1) is required. That is, in the digital filter, the multiplier occupies a considerable weight in the circuit, but in the digital filter used in the digital wireless communication, several tens of taps are normally required. Therefore, the number of multipliers must be reduced in order to miniaturize the circuit. It is desired to develop a digital filter with a reduced number of components.

It is an object of the present invention to provide a digital filter which can be downsized and which is suitable as a low pass filter used on the transmitting side of a digital radio communication system.

[0016]

In order to achieve the above object, the digital filter of the present invention has the following configuration. That is, the digital filter of the first invention, the same operation clock signal (speed f _S) at 2 ^k-1 pieces of basic digital filter [number of taps parallel operation (n + 1) number: n ≧
2] and a 2 ^k times (k ≧ 2: integer) oversampling FIR type digital filter originally has (2
^k · n + 1) number of tap coefficients (a 2 ^k or fewer tap coefficients adjacent successively the number of bits m) set ^{[2 k-1 · (n} +
1 ^k pieces], and in each set, when there are a plurality of tap coefficients belonging to that set, the sum is taken to form a new tap coefficient, etc. 2 ^k-1 (n + 1)
2 ^k-1 given the number of integrated tap coefficients (number of bits m)
Basic digital filters; and the speed is 2 ^x f _S (x =
, 2, ..., K-1) (k-1) control clock signals and one operation clock signal having a speed f _S are exclusive-ORed to obtain (k-1) A selection signal forming circuit for forming a selection signal; each output of the 2 ^k-1 basic digital filters is rearranged by the (k-1) selection signals, and a single column of signals (speed 2 ^k f _A first selection circuit for outputting as ( _S ); and the basic digital filter multiplies a corresponding one of the (n + 1) integrated tap coefficients by an input data signal (bit number 1) (n + 1). 2) delay multiplier circuits in which shift registers and adders are alternately arranged in series, wherein the first to the (n +) th of the (n + 1) multipliers are provided.
1) Output each output up to the 1st multiplier by one time slot T _S
Each of the outputs from the first (n + 1) th to the first multiplier, which forms the first signal that is sequentially added while being delayed by one, is sequentially added while being delayed by one time slot T _S. A second delay addition circuit that forms a second signal; and a second selection circuit that alternately outputs the output signals of the first and second delay addition circuits according to the selection signal of the period T _S. It is characterized by including.

The digital filter of the second invention is
4-fold oversampling FIR type digital filter originally has (4n + 1) (n ≧ 2) tap coefficients (the number of bits m), which are adjacent to each other in series of 4 or less tap coefficients [(2n + 2) groups ], And when there are a plurality of tap coefficients belonging to each group in each group, the sum of the tap coefficients is taken as a new tap coefficient, etc. to form (2n + 2) integrated tap coefficients (bit number m). (2n + 2) multipliers that take the product of the corresponding ones and the input data signal (the number of bits 1); and four delay adder circuits in which shift registers and adders are alternately arranged in series,
Of the (2n + 2) multipliers, the first to the (n + 1) th multipliers are sequentially added while delaying each output by one time slot T _S to form a first signal. Delay adder circuit, from (n + 1) th to first
The second signal is formed by sequentially adding the respective outputs up to the th multiplier by one time slot T _S while forming a second signal.
Delay adder circuit from (n + 2) th to (2n + 2) th
A third signal is formed by sequentially adding each output to the th multiplier by delaying by one time slot T _S to form a third signal.
Delay adder circuit, and (2n + 2) th to (n +)
2) Output each output up to the second multiplier by one time slot T _S
A fourth delay-and-add circuit that forms a fourth signal that is sequentially added while delaying each; two columns of the cycle T _S and cycle T _S / 2 of the first, second, third, and fourth signals And a selection circuit for alternately switching and outputting according to the selection signal of.

[0018]

Next, the operation of the digital filter of the present invention configured as described above will be described. In the present invention, the sender 2
Paying attention to the property of ^k- times oversampling and the symmetry of the tap coefficient of the roll-off filter, the number of tap coefficients integrated from the original number (2 ^k · n + 1) [2
^k−1 · (n + 1)], and the same speed (f
_S ) are the tap coefficients of 2 ^k-1 basic digital filters operating in parallel. Each basic digital filter includes a multiplier, two delay addition circuits having different delay addition directions,
The number of taps of each basic digital filter is (n + 1), but the total number of multipliers is 2 ^k-1 · (n + 1). Conventional (Fig. 1
(2, FIG. 11) requires (2 ^k · n + 1) multipliers, and the ratio of the two is given by Equation 1.
When n is large, the number of multipliers is about 1 / irrespective of the value of k.
It can be reduced to 2.

[0019]

[Equation 1]

The digital filter of the second invention is
It is composed of two basic digital filters of the first invention.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the 2 ^k times oversampling F of the present invention.
An IR type digital filter is shown. This filter
2 ^k-1 basic digital filters (1
.About.2 ^k-1 ) and (k-1) exclusive OR circuits (250
˜251) and a (first) selection circuit (SEL) 240.

2 ^k−1 basic digital filters (1 to 1)
2 ^k-1 ), whose details will be described later, share the data input terminal 201 and the operation clock input terminal 202, respectively, and operate in parallel with the same operation clock signal (speed f _S ) 122 to obtain the same data. The signal 121 is processed in parallel, and the output signals (130 to 133) are selected by the selection circuit (SEL) 240.
Give to.

(K-1) exclusive OR circuits (250
251), one of the input terminals is the operation clock input terminal 2
02, and the other input terminal is connected to the corresponding one of the (k-1) control clock input terminals (203 to 204), and the operation clock signals (speed f _S ) 122 and (k-1). Control clock signals [speed 2 ^x f _S (x =
1, 2, ..., K-1)] (123 to 124) and the exclusive OR with corresponding ones to form (k-1) selection signals (134 to 135) and select them. It is given to the circuit 240. That is, (k-1) exclusive OR circuits (25
0 to 251) constitute a selection signal forming circuit as a whole.

The selection circuit (SEL) 240 has (k-1)
Number of selection signals (134-135) according to 2 ^k-1 pieces of output signals of the basic digital filter (1 to 2 ^k-1) (130
˜133) rearrangement operation is performed to form a column of data signals (speed 2 ^k f _s ) 150, and the data signals are sent from the output terminal 220 to the outside.

The basic digital filter is constructed, for example, as shown in FIG. This basic digital filter is a 2 × oversampling FIR type filter, and shows the configuration when n = 2. The 2 × oversampling FIR filter originally requires (2n + 1) taps, and therefore 2n when n = 2.
Although + 1 = 5 taps are required, it is realized by n + 1 = 3 taps.

That is, this basic digital filter has 3
Number of multipliers (21, 22, 23), two delay addition circuits (60a, 60b), and (second) selection circuit (SE
L) 50.

In FIG. 2, the data signal (bit number l) 101 input from the input terminal 10 is composed of three multipliers (2
1, 22, 23) in parallel, where they are multiplied with the corresponding ones of the three tap coefficients (number of bits m) d _j (j = 1, 2, 3).

Here, although the grounds for setting the three tap coefficients d _j will be described later, 2n + 1 = 5 tap coefficients (bit number m) that are originally required are consecutively adjacent to two or less taps. If there are a plurality of tap coefficients belonging to each group in each group [n + 1 = 3 groups], the sum of them is taken as one tap coefficient, and the tap coefficient belonging to that group Is one, it is an integrated tap coefficient of bit number m formed by using it as a new one tap coefficient.

The three multipliers (21, 22, 2)
The output of 3) is two delay addition circuits (60a, 60b).
Given to. The first delay addition circuit 60a includes a shift register (40, 41) and an adder (30, 31). The second delay addition circuit 60b is composed of shift registers (42, 43) and adders (32, 33). Here, each of the four shift registers (40 to 43) has a delay amount corresponding to one time slot T _S of the data signal 101.

That is, two delay addition circuits (60a, 60)
In b), shift registers and adders are alternately arranged, and the first delay adder circuit 60a outputs each output from the first multiplier 21 to the third multiplier 23 to one time slot. The first signal 111 that is sequentially added while being delayed by T _S is formed (FIG. 3A), and the second delay-and-add circuit 60b operates from the third multiplier 23 to the first multiplier 21. The respective outputs of the above are sequentially added while being delayed by one time slot T _S to form a second signal 112 (see FIG. 3).
(B)), which are respectively applied to the selection circuit 50.

The selection circuit 50 has two input signals (11
1 and 112) are applied to the input terminal 11 according to the selection signal 102 (FIG. 3C) of the cycle T _S , the output signal 111 is taken out in the first half and the output signal 112 is taken out in the second half. And outputs it as an output signal 103 (FIG. 3D) from the output terminal 13 to the outside.

Next, the grounds for the configuration shown in FIG. 2 are shown in FIG.
2 will be described. FIG. 12 shows 2 ^k as described above.
Since it is the basic form of the double oversampling FIR type digital filter, the structure of the double oversampling FIR type filter is analogized from this basic form. That is, in the conventional configuration of the 5-tap 2 × oversampling FIR filter, the operating clock frequency is 2f _S , but T _S
Four shift registers having a delay amount of / 2 are connected in cascade, and a multiplier is provided at the input stage and the output stage of the shift register, and the input data signal a _i (-∞≤i≤ +) sequentially delayed by T _S / 2 is provided. ∞) and the corresponding five tap coefficients (C _{1 to} C ₅ ) are multiplied to sum the five multiplier outputs. Input data signal a _i and tap coefficient (C ₁ ~
The time relationship with C ₅ ) is as shown in FIG. 8, for example.

In FIG. 8, the time relationship between the input data signal a and the tap coefficients (C _{1 to} C ₅ ) at time t ₁ is shown in FIG.
In the case of 1), at time t ₂ one unit time after the operating clock of frequency 2f _S , FIG.
Is as following time t _3, the same t ₄ FIG 8 (A
3) and the same (A4), and the product sum b _i (−∞ ≦ i ≦ + ∞) of the tap coefficient and the data signal at each time is as shown in FIG. 8B. There is.

[0034] Here, focusing on the relationship between the tap coefficient input data signal in Fig. 8 (Al to A4), the filter output of the transmitting side, C ₅ and C _4, C ₃ and C ₂ are the same 1
It can be seen that it can be defined in two ways, corresponding to one data signal, C ₄ and C ₃ , and C ₂ and C ₁ to the same one data signal. This is the basis for setting the integrated tap coefficient.

That is, since two tap coefficients correspond to the same one data signal, if two tap coefficients having a constant relationship from the beginning are added by the above-described setting method to form one integrated tap coefficient. , The number of taps, that is, the number of multipliers can be reduced from 5 to 3 in the above example.

Specifically, the three integrated tap coefficients d
_j is C ₅ + C ₄ = d ₁ , C ₃ + from the above two modes.
Set C ₂ = d ₂ and C ₁ = d ₃ .

It should be noted here that, when used as a roll-off filter, C ₅ because of the symmetry of the tap coefficient.
= C ₁ , C ₄ = C ₂ , and d ₁ = C ₁ + C ₂ , d ₂ =
That is, C ₃ + C ₄ and d ₃ = C ₅ .

Then, according to the relationship between the integrated tap coefficient d _j set in this way and the input data signal a _i , the output signal b
Expressing _i, the output signal b _i is, d ₁ from the temporally preceding data signal and correspond to d _1, d _2, d ₃ in sequence, in order from the data signal after temporally, d _2, d It can be seen that the one corresponding to ₃ and the one corresponding to ₃ appear alternately.

From the above, in the case of a 5-tap transmission side roll-off filter, three types of multipliers, a circuit for delaying and adding the outputs of each multiplier from the data input side, and a delay and addition from the output side are provided. A double-oversampling digital filter can be constructed if there is a circuit for going forward and a selection circuit for alternately outputting the two series outputs of the two delay adder circuits for each T _S / 2. FIG. 2 is configured in this way, and as shown in FIG. 3D, an output having exactly the same content as the output of the conventional filter (FIG. 8B) can be obtained. The operation speed of all the circuits other than the output stage of the selection circuit 50 is f _S.

The 2 × oversampling digital filter described above can be used alone, but in the present invention, 2 ^k−1 pieces of such digital filters are arranged in parallel to each other and the 4 × or more oversampling digital filter, that is, FIG. 2 shown in
It is intended to obtain a ^k- fold oversampling FIR type digital filter. However, it should be noted that the integrated tap coefficient is not set as the 2 × oversampling digital filter described above, but is set as the 2 ^k × oversampling digital filter.

That is, in the 2 ^k times oversampling digital filter, 2 ^{k -1} basic digital filters [number of taps (n + 1): n ≧ 2] are 2 ^k times (k ≧
2: an integer) oversampling FIR digital filter is inherent (2 ^k · n + 1) number of tap coefficients (a 2 ^k or fewer tap coefficients adjacent successively the number of bits m) set [2 ^k-1 · (N + 1) sets], and when there are a plurality of tap coefficients belonging to each set in each set, the sum is taken to newly form one tap coefficient, etc., and 2 ^k-1 (n + 1) sets are formed. The integrated tap coefficient (number of bits m) of is given. The configuration of the 2 ^k times oversampling filter will be described below by taking a 4 times oversampling FIR type digital filter with k = 2 as an example.

As shown in FIG. 4, the 4 × oversampling FIR type digital filter includes two basic digital filters (234, 235) and a selection circuit (SE).
L) 241 and an exclusive OR circuit 252 which is a selection signal generating circuit. Here, since the two basic digital filters (234, 235) each have 3 taps in the above example, when the number of taps is 4n + 1, n
The requirement of 9 taps with = 2 can be realized with 6 taps.

In FIG. 4, the two basic digital filters (234, 235) share the data input terminal 205 and the operation clock input terminal 206, respectively, and have the same operation clock signal (speed f _S ) 127 (FIG. 5). (C))
Operate in parallel to process the same data signal 126 in parallel and output signals (138, 139) to the selection circuit (SE
L) 241 (FIGS. 5 (a) and 5 (b)).

The exclusive OR circuit 252 has one input end connected to the operation clock input terminal 206, the other input end connected to the control clock input terminal 207, and controls the operation clock signal (speed f _S ) 127. Clock signal (speed 2
f _S ) 128 (FIG. 5 (d)) is exclusive ORed to form the selection signal 155 (FIG. 5 (e)), which is applied to the selection circuit 241.

The selection circuit (SEL) 241 has a selection signal 1
When 55 is high level, basic digital filter 2
Output signal 138 of the two basic digital filters (234, 2) by selecting the output signal 138 of the basic digital filter 235 when the output signal 138 of
The output signals (138, 139) of (35) are rearranged to form one row of data signals (speed 4f _S ) 151 (FIG. 5 (f)), which are sent to the outside from the output terminal 221.

Next, FIG. 6 shows an example of a concrete configuration of the 4 × oversampling FIR type digital filter shown in FIG. Hereinafter, the method of setting the integrated tap coefficient and the specific operation of the circuit will be described with reference to FIG. 6 to show that the general configuration of FIG. 1 can be obtained.

In FIG. 6, the selection circuit (SEL) 91 is formed by combining the selection circuit (50) in each basic digital filter and the selection circuit (241) for selecting the output of each basic digital filter into one. An exclusive OR circuit (252) is stored. That is, the operation clock signal (selection signal 60) of the speed f _S (cycle T _S ) is input to the input terminal 21.
6) is applied, and the speed of 2 f _S (cycle T _S
/ 2) control clock signal (selection signal 607) is applied.

In FIG. 6, the data signal (the number of bits 1) 601 input from the data input terminal 20 is input in parallel to the six multipliers (61 to 66), where the six tap coefficients ( The number of bits m) d _j (j = 1, 2, ..., 6) is multiplied by the corresponding one, and the six multipliers (61 to 66) are divided into three parts. .. For one of the three multipliers (61 to 63), the shift register (7
1, 72) and an adder (81, 82), and a second delay adder circuit including a shift register (73, 74) and an adder (83, 84). (The above corresponds to one basic digital filter 234), and the other three multipliers (64 to 66) are provided with shift registers (75, 76) and adders (85, 8).
6) and a fourth delay addition circuit, which is composed of a shift register (77, 78) and an adder (87, 88).
And a delay adder circuit (the above corresponds to the other basic digital filter 235).

Then, eight shift registers (71 to 7
8) each has a delay amount corresponding to one time slot T _S of the data signal 601, and the four delay addition circuits are serially arranged shift registers and adders, and as described above. Operate. That is, the first delay adder circuit includes the first multiplier 61 to the third multiplier 63.
Form a first signal 602 by sequentially adding the respective outputs up to 1 time slot T _S while delaying them by one time slot T _S , and the second delay-and-add circuit operates from the third multiplier 63 to the first multiplier 61. the second signal 603 is formed by sequentially adding while delaying the output by one time slot T _S of the third
The delay-and-add circuit of (3) forms the third signal 604 by sequentially adding the outputs from the fourth multiplier 64 to the sixth multiplier 66 by delaying by one time slot T _S, and forming the third signal 604. The delay addition circuit sequentially adds the respective outputs from the sixth multiplier 66 to the fourth multiplier 64 by one time slot T _S while sequentially adding the fourth signal 605.
To form.

The selection circuit (SEL) 91 is taken out by switching the four input signals (602-605) alternately by a selection signal 606 and the period T _S / 2 of the selection signal 607 in the period T _S, the output signal thereof Output terminal 70 as 608
Send from 3 to the outside.

Here, the integrated tap coefficient d _j is the originally required 4 · n + 1 = 9 tap coefficients (the number of bits m).
And a set of 4 or less tap coefficients adjacent to each other (2 (n +
1) = 6 sets), and in each set, when there are multiple tap coefficients belonging to that set, take the sum of them, and when there is one tap coefficient belonging to that set, leave it as it is. The number of new tap coefficients is 2 (n + 1) = 6.

Next, the grounds for constructing the configuration of FIG. 6 by the same method as that described for the basic digital filter will be described. By analogy with the basic form of the 2 ^k times oversampling FIR type digital filter shown in FIG.
In the conventional configuration of the 4 × tap oversampling FIR filter, the frequency of the operation clock is 4f _S ,
Eight shift registers having a delay amount of T _S / 4 are connected in cascade, a multiplier is provided at the input stage and the output stage thereof, and an input data signal a _i (−∞ ≦ i) sequentially delayed by T _S / 4 is provided. ≤ + ∞)
Is multiplied by nine corresponding tap coefficients (C _{1 to} C ₉ ), and nine multiplier outputs are summed. Then, the time relationship between the input data number a _i and the tap coefficients (C _{1 to} C ₉ ) from time t ₁ to time t ₅ is as shown in, for example, FIG. 9A, and the tap coefficient at each time is Sum of products with data signal b _i (−∞ ≦ i
≦ + ∞ becomes as shown in FIG. Note that the time advancing / retarding direction of the signal is opposite to that in FIG. 8, but this is not an essential matter.

Then, from FIG. 9A, C _{1 to} C ₄ and C _{5 to} C ₈ correspond to one and the same data signal in the filter output on the transmission side, and C _{2 to} C ₅ and C ₆ to C. ₉ corresponds to one and the same data _{signal, C 3 ~C 6, C 7} ~C 9
Correspond to one and the same data signal, and C _{1 to} C ₃ and C ₄
~C _7, C _8, C ₉ corresponds to one of the same data signal, there are four aspects of.

That is, as described above, since a plurality of tap coefficients correspond to one and the same data signal, a plurality of tap coefficients having a certain relationship from the beginning are integrated into one.
In this case, the number of multipliers can be reduced. In the present embodiment, from the above-described four types, the six integrated tap coefficients d _j (j = 1, 2, 3, 4, 5,
6) can be defined. This is the matter described above. As a result, the number of multipliers can be reduced from 9 to 6.

[0055]

[Equation 2]

[0056]

[Equation 3]

[0057]

[Equation 4]

[0058]

[Equation 5]

[0059]

[Equation 6]

[0060]

[Equation 7]

When used as a roll-off filter, since tap coefficients have symmetry, C ₁ = C ₉ ,
C ₂ = C ₈ , C ₃ = C ₇ , and C ₄ = C ₆ . Therefore,
Formulas 2 to 7 above become Formulas 8 to 13 below.

[0062]

[Equation 8]

[0063]

[Equation 9]

[0064]

[Equation 10]

[0065]

[Equation 11]

[0066]

[Equation 12]

[0067]

[Equation 13]

Then, the output b _i of the conventional digital filter is as shown in FIG. 9B, and when this is represented by the new integrated tap coefficient d _j , it becomes as shown in equations 14-18.

[0069]

[Equation 14]

[0070]

[Equation 15]

[0071]

[Equation 16]

[0072]

[Equation 17]

[0073]

[Equation 18]

That is, since b ₅ is obtained by delaying b ₁ by one time slot, b _{1 to} b ₄ are repeated. Therefore, it can be seen that there are _four output signals b ₁ , b ₂ , b ₃ , and b ₄ , which can be formed by delaying and adding the outputs of the three multipliers. And b ₁ and b
Focusing on the relationship between ₄ , b ₂ and b ₃ , both tap coefficients correspond to the same data signal in opposite directions.
Therefore, the four output signals are typically b _4i , b _{4i + 1} ,
When described as b _{4i + 2} and b _{4i + 3} , the signal formation of the output signals b _{4i + 1} and b _4i and the output signals b _{4i + 3} and b _{4i + 2} are respectively the outputs of the three multipliers. It is understood that the above can be performed by a circuit that performs delay addition from the data input side and a circuit that performs delay addition from the data output side.

The four output signals (b _4i , b _{4i + 1} ,
b _{4i + 2} , b _{4i + 3} ) are switched in a fixed order at intervals of the cycle T _S / 4 and output, the cycle T _S is the same as in the conventional filter.
The original 9-tap 4x oversampling digital filter output can be obtained at the operating speed of
The configuration shown in FIG. 6, and hence the configuration shown in FIG. 4, is obtained.

That is, referring to FIG. 6, in one of the three multipliers (61 to 63), the first delay adder circuit outputs the output signal b.
The first signal 602 corresponding to _{4i + 1} is output, the second delay adder circuit outputs the second signal 603 corresponding to the output signal b _4i , and the other three multipliers (64 to 66), the third delay adder circuit outputs the third signal 604 corresponding to the output signal b _{4i + 3} , and the fourth delay adder circuit outputs the signal 605 corresponding to the output signal b _{4i + 2.} The selection circuit (SEL) 91 selectively outputs the outputs of these four delay addition circuits.

Since the data signal 601 is not a zero-interpolated signal (FIG. 7 (a)), the outputs (602, 603, 604, 605) of the four delay addition circuits are shown in FIG.
(B). Then, as shown in FIG. 7C, the selection signal 606 is a signal with a period T _S , and the selection signal 607 is a signal with a period T _S / 2. Therefore, the outputs (602, 603, 604, 605) of the four delay addition circuits are connected to the selection circuit 91 in the relationship (order of 602, 605, 604, 603) shown in FIG. 6, and the selection circuit 91 outputs the selection signal. 606
, The first and third signals from the top are alternately selected, and the second and fourth signals from the top are selected for the selection signal 607.
If the second signal is selected alternately, the output signal 608 of the digital filter is as shown in FIG. 7 (d). This is shown in FIG.
The signal is exactly the same as in (b), indicating that the configuration was successful.

As can be easily inferred from the above explanation,
If the idea of the 4 × oversampling FIR digital filter is expanded, it is 2 ^k × oversampling FI.
An R type digital filter can be constructed. The circuit configuration is as follows.

First, the tap number of each basic digital filter is 2 ^k times (k ≧ 2: integer) oversampling F
The IR type digital filter originally has (2 ^k · n +
1) Two tap coefficients (the number of bits m) are consecutively adjacent to each other 2
Since it is the number when divided into a set of tap coefficients of ^k or less,
The 2 ^k sets and the sets less than 2 ^k become n sets and 1 set, or (n-1) sets and 2 sets, respectively (n +
1) It becomes one.

Since the total number of multipliers is the number of sets of 2 ^k , there are 2 ^k ways of selecting the tap coefficient d ₁ at the end (which can be made up of 1 to 2 ^k ). Multiply the number of taps (n + 1) of the basic digital filter by 2 ^k · (n +
1), but 2 are the same due to the symmetry of tap coefficients
Since the number of times comes, it will be 2 ^k-1 · (n + 1) after all.

Therefore, the number of basic digital filters is
Since it suffices to divide the number of multipliers by the number of taps of the basic digital filter, the number is 2 ^k-1 .

Further, in the selection circuit, since the output of each basic digital filter has regularity, the configuration shown in FIG. 4 is basically acceptable. However, since the number of basic digital filters is 2 ^k-1 , the number of selection signals is log ₂ 2 ^k-1 = k.
It becomes -1.

FIG. 1 is constructed as described above. The basic digital filters (1 to 2 ^k-1 ) all have the same configuration and the number of taps is (n + 1),
The operating speed is f _S. From the relationship of Equation 1, when n is large, the number of multipliers can be reduced to about half regardless of the value of k.

In the present invention, the input data signal of the digital filter is not subjected to zero interpolation. for that reason,
The frequency characteristic of the input signal appears in the output frequency characteristic of the filter, but the effect can be eliminated by adding the inverse characteristic of the frequency characteristic of the input signal to the frequency characteristic of the filter.

[0085]

As described above, according to the digital filter of the present invention, the number of tap coefficients is determined by paying attention to the property of 2 ^k times oversampling on the transmission side and the symmetry of tap coefficients of the roll-off filter. The original number (2 ^k
Since n + 1) is reduced to the integrated number [2 ^k-1 · (n + 1)] and the number of multipliers is set to 2 ^k−1 · (n + 1),
There is an effect that the number of multipliers can be greatly reduced, and a digital filter that can miniaturize the circuit can be realized.

[Brief description of drawings]

FIG. 1 is a basic configuration block diagram of a 2 ^k times oversampling FIR type digital filter of the present invention.

FIG. 2 is a block diagram showing the configuration of a basic digital filter shown in FIG.

FIG. 3 is an operation time chart of a basic digital filter.

FIG. 4 is a basic configuration block diagram of a 4 × oversampling FIR digital filter.

5 is an operation time chart of the digital filter of FIG.

FIG. 6 is a specific configuration block diagram of a 4 × oversampling FIR digital filter.

FIG. 7 is an operation time chart of the digital filter of FIG.

FIG. 8 is an operation time chart of a conventional double oversampling FIR digital filter.

FIG. 9 is an operation time chart of a conventional 4 × oversampling FIR digital filter.

FIG. 10 is an input signal explanatory diagram (zero interpolation explanatory diagram) of a conventional double oversampling FIR type digital filter designed to reduce the operation speed.

FIG. 11 is a block diagram showing a configuration of a conventional double oversampling FIR type digital filter designed to reduce the operation speed.

FIG. 12 is a basic configuration block diagram of a conventional 2 ^k- fold oversampling FIR digital filter.

[Explanation of symbols]

1-2 ^k-1 basic digital filter 21-23 multiplier 30-33 adder 40-43 shift register 50 selection circuit 60a delay addition circuit 60b delay addition circuit 61-66 multiplier 71-78 shift register 81-88 adder 91 selection circuit 234 to 235 basic digital filter 240 to 241 selection circuit 250 to 252 exclusive OR circuit

Claims (2)

[Claims] ^{1. A} number of 2 ^k-1 basic digital filters [number of taps (n + 1): n ≧ 2] that operate in parallel with the same operation clock signal (speed f _S ) and are 2 ^k times (k ≧
2: an integer) oversampling FIR digital filter is inherent (2 ^k · n + 1) number of tap coefficients (a 2 ^k or fewer tap coefficients adjacent successively the number of bits m) set [2 ^k-1 · (N + 1) sets], and when there are a plurality of tap coefficients belonging to each set in each set, the sum is taken to form a new tap coefficient, etc., and 2 ^k-1 (n + 1) sets are formed. 2 ^k-1 basic digital filters to which the integrated tap coefficient (the number of bits m) is given; and the speed is 2 ^x f _S (x = 1, 2, ..., K-1) (k-1) A selection signal forming circuit for forming (k-1) selection signals by taking the exclusive OR of the control clock signals and one operation clock signal of speed f _S ;
^The output of each of the ^k-1 basic digital filters is (k-
1) a first selection circuit that performs a rearrangement operation according to the number of selection signals and outputs a signal of one column (speed 2 ^k f _s ); and the basic digital filter includes the (n + 1)
(N + 1) multipliers that take the product of the corresponding one of the integrated tap coefficients and the input data signal (the number of bits is 1);
A delay adder circuit in which a shift register and an adder are alternately arranged in series, wherein each output from the first to the (n + 1) th multiplier among the (n + 1) multipliers is output. A first delay adder circuit that forms a first signal that is sequentially added while being delayed by one time slot T _S , and outputs the outputs from the (n + 1) th to the first multiplier to 1
A second delay adder circuit that forms a second signal that is sequentially added while being delayed by each time slot T _S ;
And a second selection circuit that alternately outputs each output signal of the second delay-and-add circuit according to a selection signal with a period T _S , and a second selection circuit; 2. A (4n + 1) number (n ≧) originally possessed by a 4 × oversampling FIR type digital filter.
The tap coefficient (bit number m) of 2) is divided into a set of 4 or less adjacent tap coefficients in succession [(2n + 2) sets],
In each set, when there are a plurality of tap coefficients belonging to that set, the sum of the tap coefficients is taken as a new tap coefficient to form a new tap coefficient, and (2n + 2) integrated tap coefficients (the number of bits m) correspond to (2n + 2) number of multipliers that take the product of the input data signal (the number of bits is 1); Out of the multiplier
A first delay adder circuit that forms a first signal by sequentially adding the outputs from the first to (n + 1) th multipliers by one time slot T _S ,
A second delay adder circuit that forms a second signal by sequentially adding the outputs from the 1) th to the 1st multipliers by one time slot T _S , from the (n + 2) th to the (2n + 2) th ) Th delay adder circuit that forms a third signal by sequentially adding each output to the multiplier by delaying each time slot T _S , and (2n + 2) th delay adder circuit
Fourth output in which outputs from the (n + 2) th multiplier to the (n + 2) th multiplier are sequentially added while being delayed by one time slot T _S
A fourth delay-and-add circuit that forms a signal of
The second signal, the third signal, and the fourth signal are given a period T _S and a period T _S / 2.
And a selection circuit that alternately switches and outputs the selection signals according to the selection signals of the two columns.