JPH0865107A - Digital interpolation filter circuit - Google Patents

Abstract

PURPOSE: To obtain the digital interpolation filter circuit making a high speed operation by adopting a switch circuit for at least one of adders used for a filter and setting a filter coefficient to a power of 2. CONSTITUTION: A sampling frequency is converted into 2fs from a frequency fs , and the converted frequency signal is given to an input terminal 1. When signal data x [T] subject to 0 insertion and whose sampling frequency is converted are given to the filter circuit, the data are fed to a delay register 3-1 and a multiplier 8-1 . The data x [T] are multiplied with a coefficient a1 by the multiplier 8-1 and the resulting data a1 .x [T] are given to a switch (circuit 9-1 , which is thrown to the position of the multiplier 8-1 . The delay register 3-1 receiving the data x [T] provides an output of delayed data x [T] by one sample to a multiplier 8-2 , in which a coefficient, a2 is multiplied with the data x [T], and the product is given to the switch circuit 9-1 . In this case, succeeding data are given to the multiplier 8-1 and the data are 0, then the switch circuit 9-1 is thrown to the position of a multiplier 8-2 and the data are outputted finally to an output terminal 7 by the similar switching operation to above.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital interpolation filter circuit used for digitized communication equipment, broadcasting equipment, transmission equipment and other digitized equipment.

[0002]

2. Description of the Related Art As a conventional digital interpolation filter circuit, there is an N-fold digital interpolation filter circuit as shown in the schematic view of FIG. The N-fold digital interpolation filter circuit will be described with reference to FIGS. In FIG. 3, 31 is a digital signal input terminal, 3
Reference numeral 2 is a reset pulse generator that generates a reset pulse having a repetition cycle of 1 / (f × N), 39 is a switch circuit that is switched by the reset pulse generated by the reset pulse generator 32, 34 is a digital filter, and 37 is a digital signal. Indicates the output terminal.

An n-bit digital signal sampled at the sampling frequency fs and having a frequency characteristic as shown in FIG. 4 is input to the digital signal input terminal 31 and applied to one terminal of the switch circuit 39. The other terminal of the switch circuit 39 is grounded and 0 level is applied. When the switch circuit 39 is switched to the terminal side to which the 0 level is applied by the reset pulse having the repeating period 1 / (f × N) generated by the reset pulse generator 32 and 0 is inserted to convert the sampling frequency, The frequency characteristics obtained by frequency conversion are shown in FIG. However, the signal required in the frequency characteristics shown in FIG. 5 is only the shaded area, and the aliasing component repeated for each other sampling frequency fs becomes noise. Therefore, a digital filter 34 for removing this is used. Must be used. The circuit configuration of the digital filter 34 according to the prior art includes those shown in FIGS. First, the digital filter shown in FIG.
The case where the sampling frequency is converted to s will be described with reference to FIGS. 6 and 8.

FIG. 6 is a first block diagram showing a conventional digital filter, and FIG. 8 is a diagram for explaining changes in a digital signal input to a digital interpolation filter circuit. As for the input signal input to the digital signal input terminal 31 of the digital interpolation filter circuit shown in FIG. 3, as shown in FIG. 8, the data is x [T], and the data of the input signal one sample before is x [T-1]. Assuming that the data of the input signal two samples before is x [T-2], the switch circuit 39 is switched by the reset pulse, and the signal 0 inserted by the sampling frequency conversion becomes the data as shown in FIG. 0s are arranged alternately. This data and 0 are alternately arranged in FIG.
Signal is input from the digital filter input terminal 61 and input to the delay register 3 _-1 and the multiplier 8 _-1 . A signal obtained by delaying one sample by the delay register 3 _-1 shown in FIG. 8 by a coefficient a ₂ at the multiplier 8 _-2 is multiplied by a signal a ₁ at the multiplier 8 _-1 to which the signal in FIG. 8 is input. The added signal is added by the adder 5 _-1 . The result of this addition is as shown in FIG.

Further, the addition output of the adder 5 _-1 is delayed by a total of 2 samples by the delay register 3 _-1 , 3 _-2 from the input signal from the digital filter input terminal 61, and a coefficient a is obtained by the multiplier 8 _{-3. 3} adder _5-2 what the multiplied, delayed and so, multiply, the added signal by adding n times and outputs the result from the digital filter output terminal 67. In the digital filter shown in FIG. 6, the adder used has two inputs, and the multipliers 8 _-1 , 8 _-2 ,.
.. It is not possible to add all the outputs of 8- _{n + 1} at the same time, so the adders _5-1 , _5-2 , ... 5- _n are added in order. Therefore, the maximum delay time increases as the number of taps increases.

Next, a second block diagram of another conventional digital filter shown in FIG. 7 will be described. In FIG. 7, the digital filter input terminal 71 is connected to a plurality of multipliers 8 _{-n + 1} , ... 8 _-1, and the output of the multiplier 8 _{-n + 1} is connected to the delay register 3 _-n. There is. Further, the multiplier 8 outputs an output of the delay register 3 _-n of _-n are connected to the respective adders 5 _-n, adder 5 _-n output delay register 3
It is connected to _-n-1 . Similarly, the multiplier 8 outputs of the delay register 3 _-n-1 of _-n-1 are connected to respective adders 5 _-n-1, the output of the adder 5 _-n-1 delay register 3 _- is connected to the _n-2, (hereafter, after connecting as well), the output from the multiplier 8 outputs a delay register 3 _{-n-2 -2} are connected to an adder _5-2, respectively, the adder the output of _5-2 is connected to the delay register _3-1. Further, the output of the delay register 3 _-1 and the output of the multiplier _28-1 is connected to the adder 5 _-1, the output of the adder 5 _-1 is connected to the digital filter output terminal 77.

Similar to the description of FIG. 6 described above, a case where the sampling frequency fs is converted into a sampling frequency of 2fs which is doubled will be described with reference to FIG. A digital input signal sampling frequency fs inputted to the digital signal input terminal 31 of the digital interpolation filter circuit shown in FIG. 3, entering 0 sampling frequency converted signal by insertion from the digital filter input terminal 71, the multiplier 8 _{- n + 1} , 8- _n ,
・ ・ ・ Input in each of 8 _-1 . Next, a signal obtained by multiplying the input signal from the digital filter input terminal 71, into which 0 is inserted, by the coefficient a _{n + 1} by the multiplier 8- _{n + 1} , is _added to the delay register 3 _-n.
The signal delayed by 1 sample by the above and the signal obtained by multiplying the input signal with 0 inserted by the coefficient a _n by the multiplier 8- _n are the adders 5- _n.
And added to the delay register 3 _-n-1 . Further, the output of this delay register 3 _-n-1 and the signal obtained by multiplying the 0-inserted input signal by the coefficient a _n-1 by the multiplier 8 _{-n -1} are added by the adder 5 _-n-1 . The output signal from the delay register is input to the delay register 3 _-n-2 , and the signal obtained by multiplying the input signal from the digital filter input terminal 1 with the coefficient by the multiplier is added n times. The result is output from the digital filter output terminal 77.

The filter structure shown in FIG. 7 is functionally the same as the filter shown in FIG. 6, but has a delay register after the multiplier and the adder. In this filter configuration, since the output timing can be adjusted by the delay register after addition, the maximum delay time is the sum of the delay times of the adder and the multiplier, and does not change even if the number of taps increases. Therefore, it is possible to configure a filter that can operate at a higher speed than the filter configuration of FIG.

[0009]

In the first conventional example, there is a problem that the delay due to the gate inside the adder accumulates each time it propagates, and the operating speed of the entire filter is limited. Further, in both the first and second conventional examples, when the number of bits is increased to increase the operation word length in the filter, carry propagation delay occurs between the adders connected in parallel, which increases the delay time of the adder. Therefore, there is a problem that the processing speed of the entire filter is limited. The delay time of the filter is the sum of the delay times of the multiplier and the adder as described above, and the multiplier can be omitted by selecting the filter coefficient to be a power of 2 or can be replaced with the adder. However, the adder is an essential element of the digital filter and cannot be omitted. According to the present invention, in a digital interpolation filter circuit that performs sampling frequency conversion, at least one of the adders used in the digital filter is replaced with a switch circuit, and the filter coefficient is multiplied by a power of 2 to use a multiplier. It is an object of the present invention to provide a digital interpolation filter circuit which operates at high speed by minimizing the total number of gates.

[0010]

In order to achieve the above object, a digital interpolation filter circuit of the present invention repeats a digital signal of sampling frequency f with a repetition period 1 / (f × N).
In a digital interpolation filter circuit having a switch circuit that interpolates N times by switching with a reset pulse of (where N is an integer) and a digital filter having a sampling frequency N · f, n (however, n is a filter order) number of delay registers, n + 1 multipliers connected to the first input side and each output side of the n number of delay registers and multiplying a predetermined filter coefficient, and n +
A plurality of switch circuits that form a set of N multipliers of one multiplier and select one of the multiplier outputs of each set, and a plurality of adders that add the outputs of the plurality of switch circuits. It has a digital filter provided with.

Further, the digital interpolation filter circuit of the present invention repeats the digital signal of the sampling frequency f with the repetition period 1
/ (F × N) (where N is an integer) reset pulse switching circuit and sampling frequency N
In a digital interpolation filter circuit having a digital filter of f, n + 1 multipliers that are connected in parallel to the input and multiply a predetermined filter coefficient, and the second to N−1th multipliers of the n + 1 multipliers. Up to (N-1) switch circuits, the adders connected to the (N + 1) th to (n + 1) th outputs of the (n + 1) multipliers, and the output of the first multiplier. And a digital filter having n delay registers connected to the output of the switch circuit and the output of the adder.

Further, the digital interpolation filter circuit of the present invention repeats the digital signal of the sampling frequency f with the repetition period 1
/ (F × N) (where N is an integer) reset pulse switching circuit and sampling frequency N
In a digital interpolation filter circuit having a digital filter of f, n (where n is the filter order) delay registers connected in series to the input, and the first input side of the n delay registers N + 1 adders connected to the respective output sides for bit-shifting and adding data in accordance with filter coefficients that are powers of 2;
A group of N adders of one adder is formed, and a plurality of switch circuits for selecting one of the adder outputs of each group and two switch circuits of the plurality of switch circuits are grouped. The digital filter has a plurality of adders for adding respective outputs.

Further, the digital FM communication apparatus of the present invention includes the digital interpolation filter circuit and an adder for adding the modulation data input from the digital interpolation filter circuit to a separately input carrier wave and outputting a phase-modulated modulated wave. And a direct digital synthesizer that integrates the modulated waves input from the adder and outputs an FM modulated wave signal.

[0014]

The digital interpolation filter circuit of the present invention repeats the digital signal of the sampling frequency f with the repetition period 1 / (f ×
N) (where N is an integer) reset pulse
A digital interpolation filter circuit having a switch circuit for performing double interpolation and a digital filter having a sampling frequency N · f, the digital interpolation filter circuit having:
N (where n is the filter order) delay registers connected in series to the input and a first of the n delay registers
An n + 1 multiplier connected to the second input side and each output side for multiplying a predetermined filter coefficient, and N multipliers of each of the n + 1 multipliers are set as a set, and the output of each set of multipliers is A digital filter including a plurality of switch circuits for selecting one of them and a plurality of adders for adding outputs of the plurality of switch circuits outputs a required digital signal from a digital signal interpolated N times. .

The digital interpolation filter circuit of the present invention is
A digital signal of sampling frequency f is repeated at a cycle of 1 / (f
XN) (where N is an integer), a digital interpolation filter circuit having a switch circuit for interpolating N times by switching with a reset pulse and a digital filter having a sampling frequency N · f, wherein the digital interpolation filter circuit is Having n (where n is a filter order) delay registers connected in series to the inputs, and a first power input of each of the n delay registers and a power of 2 connected to each output. N + 1 adders for bit-shifting and adding data according to the filter coefficient, and N of the n + 1 adders
A digital filter provided with a plurality of switch circuits each including a plurality of adders and selecting one output from each of the adder outputs, and a plurality of adders configured to add the outputs of the plurality of switch circuits, A desired digital signal is output from the digital signal interpolated N times.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. Note that the description will be given for the case where the sampling frequency fs is doubled to 2fs for sampling frequency conversion. In FIG. 1, the digital filter input terminal 1 is connected to the delay register 3 _-1 , and thereafter, the delay register 3 _-2 ,
... 3- _n-1 and the delay register 3- _n are continuously connected. The digital filter input terminal 1 is
It is connected to the multiplier 8 _-1, and is connected to the delay register 3 _-i (i = 1 ...
The output of (n, and so on) is connected to the multiplier 8- _{i + 1} .

Further, the outputs of the multiplier 8 _-1 and the multiplier 8 _-2 are connected to the switch circuit 9 _-1 , and the outputs of the multiplier 8 _-3 and the multiplier 8 _-4 are connected to the switch circuit 9 _-2 , respectively. The respective signals of the switch circuits 9 _-1 , 9 _-2 are connected to the adder 5 _-1 . Thereafter, similarly, two multipliers are paired and their outputs are connected to the switch circuit, and the output of the switch circuit is connected to the adder. However, when the filter order n is an even number, the multiplier 8 _{-n + 1} connects the output to the adder 5 _-P without using the switch circuit. The adder 5 _-1 outputs its output to the adder 5 _-2 , the adder 5 _-2 outputs its output to the adder 5 _-3 , ... and the output of the adder 5 _-P to the filter output terminal 7 Connect to.

Next, the operation of the digital filter shown in FIG. 1 will be described with reference to FIG. When the data x [T] of the signal of FIG. 8 which has been subjected to sampling frequency conversion by inserting 0 is input from the digital filter input terminal 1,
This data x [T] is input to the delay register 3 _-1 and the multiplier 8 _-1 . The data a ₁ x [T] multiplied by the coefficient a ₁ in the multiplier 8 _-1 is input to the switch circuit 9 _-1 . At this time, the switch circuit 9 _-1 is switched so as to be connected to the multiplier 8 _-1 side.

The delay register 3 _-1 to which the data x [T] is input is delayed by one sample and the data x [T] is delayed.
Is output, multiplied by a coefficient a ₂ by the multiplier 8 _-2 , and input to the switch circuit 9 _-1 . At this time, the next data is input to the multiplier 8 _-1 , but since this data is 0, the switch circuit 9 _-1 is switched so as to be connected to the multiplier 8 _-2 side. The output of the switch circuit 9 _-1 is the same as that of FIG. 8 showing the output of the adder 5 _-1 in the circuit using the adder according to the prior art shown in FIG. And so on
Among the output signals of the multipliers 8 _-3 and 8 _-4 , the one with data is alternately switched and selected, and the one with data of the two sets of multipliers is switched by each switch circuit. The data switched and selected by the respective switch circuits are added, and all the added data are output from the digital filter output terminal 7.

In the circuit configuration shown in FIG. 1, when a signal interpolated by fs × N times is input to the input, when the filter order n is an odd number, ((n + 1) / N) switch circuits and (m- 1) number of adders, and when the filter order n is an even number, it can be configured by (n / N) switch circuits and m number of adders. However, m
Is the number of switch circuits.

A second embodiment of the present invention will be described with reference to FIG. The circuit configuration of this digital filter is the same as the circuit configuration of the conventional digital filter shown in FIG. 7, _except that the adders 5 _-n to 5 _{-n -m + 1} are changed to switch circuits. Is. As for the switch circuits used in this digital filter, one having data is switched and selected by each switch circuit as in the circuit of FIG.

In the circuit configuration of the digital filter shown in FIG. 2, when a signal interpolated by fs × N times is input to the digital filter input terminal 1, (N-1) switch circuits and (nm) are provided. It can be configured with an adder. Further, in the above-described first and second embodiments, if the filter coefficients a _{1 to} a _{n + 1} are set to values of powers of 2,
The multiplier may not be used. This is because if the multiplier is ... 2 to ¹ , 2 ⁰ , 2 ¹ , ... For certain data, only the bit shift operation is required. This makes it possible to further reduce the delay time of the digital interpolation filter.

FIG. 9 shows a block diagram of an embodiment in which the present invention is applied to a digital FM communication device. N digital signal bits input from the digital signal input terminal 91, a reset pulse generated by the reset pulse generator 92, and a 0 inserted sampling frequency converting the delay register 3 _-0, 1 or FIG. Filter 9 shown in 2
4 is input. Outputs the output signal of the filter 94 to the adder 5 _-0, the adder 5 _-0 phase modulated by adding a carrier, integrated to FM modulation required frequency in DDS (direct digital synthesizer) 96 A wave signal is obtained. In general, the frequency of the carrier wave signal is higher than that of the input signal by about 2 to 3 digits, so that the filter 94 shown in FIG. 9 performs the digital interpolation operation. Therefore, if the digital interpolation filter of the present invention is applied to this filter 94, a digital FM communication device with a small amount of hardware and capable of high-speed operation can be realized.

[0024]

According to the present invention, in a digital interpolation filter circuit for performing sampling frequency conversion, at least one of the adders used in the filter is replaced with a switch circuit, and the filter coefficient is a power of 2. By not using the multiplier, the total number of gates can be minimized and a digital interpolation filter circuit that operates at high speed can be provided. Further, according to the present invention, a high-speed and highly stable digital FM communication device can be constructed. Furthermore, the digital interpolation filter circuit of the present invention is applied to a wide range of digital interpolation filters in which digital filters are used, such as digital communication devices, broadcasting equipment, transmission equipment, digital audio equipment such as CDs and DATs, video equipment, and measurement equipment. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a digital filter according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the digital filter according to the present invention.

FIG. 3 is a block diagram showing a digital interpolation filter circuit.

FIG. 4 shows frequency characteristics of a digital input signal before sampling frequency conversion.

FIG. 5 shows frequency characteristics after sampling frequency conversion of a digital input signal.

FIG. 6 is a first block diagram showing a conventional digital filter.

FIG. 7 is a second block diagram showing a conventional digital filter.

FIG. 8 is a diagram illustrating a change in a digital signal input to a digital interpolation filter circuit.

FIG. 9 is a block diagram showing an embodiment of a digital FM communication device using a digital interpolation filter circuit according to the present invention.

[Explanation of symbols]

1, 61, 71 ... Digital filter input terminal, 3 ... Delay register, 5 ... Adder, 7, 67, 77 ... Digital filter output terminal, 8 ... Multiplier, 9 ... Switch circuit, 3
1, 91 ... Digital signal input terminal, 32, 92 ... Reset pulse generator, 34, 94 ... Digital filter,
96 ... Direct Digital Synthesizer (DD
S), 37, ... Digital signal output terminal, 39 ... Switch circuit, 97 ... FM modulated wave signal output terminal.

Claims (4)

[Claims] 1. A switch circuit for interpolating a digital signal of a sampling frequency f with a reset pulse having a repeating period 1 / (f × N) (where N is an integer) by N times, and a sampling circuit of a sampling frequency N · f. In a digital interpolation filter circuit having a digital filter, n (where n is a filter order) delay registers connected in series to an input, a first input side of the n delay registers, and respective outputs N + 1 connected to the side for multiplying a predetermined filter coefficient
Number of multipliers and N number of multipliers of the n + 1 multipliers as a set, and a plurality of switch circuits for selecting one of the multiplier outputs of each set, and an output of the plurality of switch circuits. A digital interpolation filter circuit having a digital filter having a plurality of adders for adding. 2. A switch circuit for interpolating a digital signal of a sampling frequency f with a reset pulse having a repeating period of 1 / (f × N) (where N is an integer) by N times, and a sampling frequency of N · f. In a digital interpolation filter circuit having a digital filter, n connected to the input in parallel and multiplied by a predetermined filter coefficient
+1 multipliers, N−1 switch circuits connected to the second to N−1th outputs of the n + 1 multipliers, and the N + 1th and subsequent N + 1 multipliers. A digital filter including an adder connected to the (n + 1) th output, an output of the first multiplier, an output of the switch circuit, and n delay registers connected to the output of the adder A digital interpolation filter circuit having: 3. A switch circuit for interpolating a digital signal of a sampling frequency f with a reset pulse having a repeating period 1 / (f × N) (where N is an integer) by N times, and a sampling frequency of N · f. In a digital interpolation filter circuit having a digital filter, n (where n is a filter order) delay registers connected in series to an input, a first input side of the n delay registers, and respective outputs Connected to the side and adding n + 1 adders for bit-shifting and adding data in accordance with filter coefficients of powers of 2 and N adders of the n + 1 adders, and adding each set A digital filter having a plurality of switch circuits that select one of the switch outputs and a plurality of adders that add the outputs of the plurality of switch circuits. Interpolation filter circuit. 4. The digital interpolation filter circuit according to claim 1, and the modulation data input from the digital interpolation filter circuit is added to a separately input carrier wave to output a phase-modulated modulation wave. A digital FM communication device comprising: an adder and a direct digital synthesizer that integrates the modulated waves input from the adder and outputs an FM modulated wave signal.