JP2002368584A - Digital filter and digital video encoder using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital filter and a digital video encoder with which the number of gates is reduced, a degree of freedom in layout and a maximum operating frequency are increased as a result, an area per chip is reduced and yield is improved. SOLUTION: A prestage filter part 2 for outputting a signal S2, while setting the number of taps is set to a value, with which sharpness at close region to a cutoff frequency can be made smooth, within a range not to generate pass band ripples and setting a coefficient h(n) and a total sum thereof to a value which is the square of '2', is cascade-connected with a post-stage filter part 3 for generating and outputting a signal SOUT having characteristics such as its pass band is flattened without ripples and the neighborhood of a cutoff frequency fc is sharpened, while setting the number of taps to a prescribed value with which a smooth part in the pass band of the signal S2 can be held up and characteristics at close region to the cutoff frequency fc can be corrected to become sharp, and setting the coefficient h(n) and a total sum thereof to a value which is the square of '2'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter required for digital signal processing and a digital video encoder using the same.

[0002]

2. Description of the Related Art In digital signal processing of images and sounds,
Filtering is often used. The filter used for the filtering process has a linear phase characteristic with a finite number of taps, and thus has a linear phase FIR (Finite Impulse Response).
se: Finite impulse response) filter is often used.

FIG. 21 is a diagram showing a configuration example of a conventional FIR filter. The FIR filter 1, n multipliers 2-1 to 2-n, and n-1 delay elements 3-1 to 3-n-1 and n-1 adders 4 alternately cascaded. -1
To 4-n-1.

In the FIR filter 1, an input signal S
IN is multiplied by filter coefficients h (0) to h (N) by multipliers 2-1 to 2-n, respectively. The output signal of the multiplier 2-1 is delayed by the delay element 3-1 and input to the adder 4-1. The output signal of the multiplier 2-2 is input to the adder 4-1. The signal multiplied by the coefficient h (1) and the signal multiplied by the coefficient h (2) are added. Is delayed by the delay element 3-2 and the adder 4-2
Is input to The output signal of the multiplier 2-3 is input to the adder 4-2, and the signal multiplied by the coefficient h (1) and the signal multiplied by the coefficient h (2) further have a coefficient h (3). The multiplied signal is added, and the added signal is delayed by the delay element 3-3 and input to the adder 4-3. Similarly, the signals multiplied by the coefficients h (4) to h (N-1) are sequentially added, and finally, the coefficient h (4) is added by the adder 4-n-1.
The signals multiplied by (N) are added, and as a result, a signal obtained by adding the output signals of the n multipliers is output as a signal SOUT.

[0005]

As described above, in the conventional FIR filter 1, the input signal SIN is multiplied by the coefficients h (1) to h (N) by the multipliers 2-1 to 2-n, and the delay is obtained. The signals are input to the elements 3-1 to 3-n-1 and the adders 4-1 to 4-n-1.

The coefficients h (1) to h (N) are real constants calculated from the frequency characteristics required of the FIR filter 1. A multiplier 2 multiplies the real signal by the real constant. 1 to 2-n required a large number of gates. As a result, there are disadvantages such as the layout freedom is restricted, the maximum operating frequency is restricted, the area per chip increases, and the yield decreases.

The present invention has been made in view of the above circumstances, and has as its object to reduce the number of gates, thereby increasing the degree of freedom in layout, increasing the maximum operating frequency, and increasing the area per chip. It is an object of the present invention to provide a digital filter which can be reduced and the yield can be improved and a digital video encoder using the same.

[0008]

In order to achieve the above object, the present invention provides a method in which an impulse response is represented by a finite time length,
The impulse response is a filter coefficient, and includes a plurality of coefficient assigning means for assigning a predetermined filter coefficient to an input signal in parallel, and an adding means for adding a plurality of signals to which the filter coefficient is assigned. The digital filter includes an output unit that sets the sum of the filter coefficient and the filter coefficient to a value of a power of 2, and outputs the added signal by multiplying the sum of the filter coefficients by one.

In the present invention, the plurality of coefficient assigning means and the output means include a bit shifter.

Further, the present invention is a digital filter in which an impulse response is represented by a finite time length, the impulse response is a filter coefficient, and has a linear phase characteristic with a finite number of taps. In a range where the passband ripple does not occur, the value is set to a value that can have a frequency characteristic in which the steepness near the cutoff frequency becomes gentle, and the filter coefficient and its sum are at least one set to a power of two. One of the first filter units and the number of taps can cancel out and lift a gentle portion in the pass band of the frequency characteristics of the first filter unit, so that the characteristics near the cutoff frequency become steep. At least one second filter unit set to a value having a frequency characteristic that can be corrected, wherein the first filter unit and the second filter unit Filter unit is cascaded.

Also, the present invention is a digital filter in which an impulse response is represented by a finite time length, and the impulse response is a filter coefficient, and has a linear phase characteristic with a finite number of taps. Within the range where the passband ripple does not occur, the steepness near the cutoff frequency is set to a value that has a gentle frequency characteristic, and the filter coefficient and its sum are set to powers of two. The first to pass the low frequency components of the signal
And the number of taps can cancel out and lift a gentle part in the pass band in the frequency characteristic of the output signal of the first filter part, so that the characteristic near the cutoff frequency becomes steep. A second filter unit that generates and outputs a signal having a characteristic that is set to have a frequency characteristic that can be corrected, has a flat passband without ripple, and has a sharp characteristic near a cutoff frequency. .

Further, in the present invention, at least one of the first filter unit and the second filter unit includes a plurality of coefficient assigning means for assigning a predetermined filter coefficient in parallel to an input signal; And an output means for multiplying the signal added by the adding means by one times the sum of the filter coefficients and outputting the resultant signal.

In the present invention, the plurality of coefficient assigning means and the output means include a bit shifter.

Further, the present invention includes a luminance signal filter for extracting a low frequency component of a luminance signal, and a color difference signal filter for extracting a low frequency component of a color difference signal. A digital video encoder that generates a video signal based on a color difference signal by the color difference signal filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length. Impulse response is a filter coefficient, a plurality of coefficient providing means for providing a predetermined filter coefficient in parallel to the input signal,
An adding means for adding a plurality of signals to which the filter coefficients are given, wherein the sum of the filter coefficients and the filter coefficients is set to a value of a power of two, and the added signal is calculated by dividing the sum of the filter coefficients by 1 / It includes a digital filter having output means for multiplying and outputting.

The present invention also includes a luminance signal filter for extracting a low frequency component of a luminance signal, and a color difference signal filter for extracting a low frequency component of a color difference signal. A digital video encoder that generates a video signal based on a color difference signal by the color difference signal filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length. A filter whose impulse response is a filter coefficient and has a linear phase characteristic with a finite number of taps, and the number of taps is such that the steepness near the cutoff frequency becomes gentle within the range where no passband ripple occurs. The value is set to a value that has characteristics, and the filter coefficient and its sum are set to a power of 2 Also, the first filter section and the number of taps can cancel out and lift a gentle part in the pass band of the frequency characteristic of the first filter section, and the characteristic near the cutoff frequency becomes steep. At least one second filter unit set to a value having a frequency characteristic that can be corrected as described above,
The digital filter includes a digital filter in which the first filter unit and the second filter unit are cascaded.

Further, the present invention includes a luminance signal filter for extracting a low frequency component of a luminance signal, and a color difference signal filter for extracting a low frequency component of a color difference signal. A digital video encoder that generates a video signal based on a color difference signal by the color difference signal filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length. A filter whose impulse response is a filter coefficient and has a linear phase characteristic with a finite number of taps, and the number of taps is such that the steepness near the cutoff frequency becomes gentle within the range where no passband ripple occurs. Is set to a value that has characteristics, and the filter coefficients and their sum are set to powers of two. A first filter section that passes a low-frequency component of the digital signal, and a tap number, in which the smoothed portion in the pass band in the frequency characteristic of the output signal of the first filter section can be canceled and lifted, and cut. It is set to a value that has a frequency characteristic that can be corrected so that the characteristic near the off-frequency becomes steep, the passband generates a signal with flat characteristics without ripple and a sharp characteristic near the cutoff frequency. A digital filter having a second filter unit for outputting the output signal.

According to the present invention, an input digital signal such as a luminance signal and a color difference signal is input to the first filter unit. In the first filter unit, for example, a low-frequency component is extracted, and a signal having no passband ripple and having a frequency characteristic in which the steepness near the cutoff frequency becomes gentle is output to the second filter unit. In the second filter section,
In the frequency characteristic of the output signal of the first filter unit, the gentle part in the pass band is offset and lifted, and the characteristic near the cutoff frequency is corrected to be steep. As a result, the pass band is rippled. A signal which is flat and has a characteristic in which the vicinity of the cutoff frequency is steep is generated and output.

[0018]

FIG. 1 is a block diagram showing an embodiment of an FIR filter according to the present invention.

The FIR filter 1A constitutes a low-pass filter (LPF), and as shown in FIG.
It has a first-stage filter unit 2A as a first filter unit and a second-stage filter unit 3A as a second filter unit cascade-connected to IN. Specifically, as described in detail below, the FIR filter 1A cascade-connects LPFs having different frequency characteristics in two stages, and calculates the coefficient h (n) of each filter unit and its sum to the power of two. By setting the value, a passband ripple RPL as shown in FIG. 2 is eliminated, and a steep characteristic near a so-called cutoff frequency fc is realized.

The pre-filter unit 2A sets the number of taps to a value at which the steepness near the cutoff frequency becomes gentle, for example, 11 within a range where no passband ripple occurs, and the FIR filter coefficient h (n) And their sum
Power of 2 values (1,2,4,8,16,32 ...), for example, (1,1,1,2,2,2,2,2,1,
1,1 × 1/16) to pass the low-frequency component of the input digital signal SIN up to the frequency fp,
2 and is output to the post-filter unit 3A.

The post-filter unit 3A is different from the signal S2 from the pre-filter unit 2A in that the number of taps does not cause any passband ripple and has a gentle frequency characteristic near the cutoff frequency. It is set to a value that can lift a gentle part in the pass band (for example, the number of ripples is 1), and can be corrected so that the characteristic near the cutoff frequency fc becomes steep, for example, 19, and FIR. The filter coefficient h (n) and its sum are power of two values, for example, as shown in FIG.
(-2, -1, 0, 0, 2, 2, 2, 2, 2, 2, 2,
2,2,2,2,0,0, -1, -2 × 1/16), a signal SOUT having a flat characteristic without a ripple in the passband and having a sharp characteristic near the cutoff frequency fc. And output.

Next, the selection of the number of taps and the reason for the two-stage configuration will be described with reference to the drawings.

FIG. 4 is a diagram showing the relationship between the number of taps of the FIR filter and the frequency characteristics. As shown in FIG. 4, when the number of taps is small, the FIR filter has a small attenuation, the steepness near the cutoff frequency is gentle, the amplitude of the pass band ripple RPL is large, and the pass band ripple RP
L has a characteristic that the wave number is small (it becomes 0 ultimately). Conversely, the FIR filter has a large number of taps.
The amount of attenuation is large, the steepness near the cutoff frequency is steep, the amplitude of the passband ripple RPL is small, and the wavenumber of the passband ripple RPL is large.

FIGS. 5 to 7 show the numbers of taps 11, 17, and 51.
3 shows the frequency characteristics of the FIR filter of FIG. 5 to 7, the horizontal axis represents the frequency f, and the vertical axis represents the gain. In this case, the coefficient h (n) is rounded to an integer such that the sum of the frequency fp = 6.5 MHz and the filter coefficient h (n) becomes 128.

As shown in FIGS. 5 to 7, when the number of taps is 11, there is no passing ripple RPL. When the number of taps is 17, there is one passing ripple RPL.
In the case of 1, there are multiple passing ripples RPL.
Therefore, as can be seen from FIGS. 5 to 7, the number of taps cannot be set to a certain number or more to eliminate the passing ripple RPL. In this example, only up to 11 taps can be set. However, the tap number (11 in this example) lacks sharpness near the cutoff frequency fc as shown in FIG. Therefore, in the present embodiment, the filter has a two-stage configuration.

That is, in the present embodiment, the number of taps of the pre-filter unit 2A is set to, for example, 11, to obtain a frequency characteristic that has no passband ripple but lacks sharpness near the cutoff frequency fc. The number of taps of 3A is set to 17 or more, and in the present embodiment, to 19, the frequency characteristic in which only one passband ripple is present and the steepness near the cutoff frequency fc is sufficient is obtained. By synthesizing the frequency characteristics, the FIR filter 1A is configured to obtain a signal SOUT having a flat passband with no ripple and a characteristic having a sharp characteristic near the cutoff frequency fc.

As described above, in the present embodiment, since the FIR filter coefficients h (n) of the pre-stage filter unit 2A and the post-stage filter unit 3A and their sum are powers of 2, each pre-stage filter unit 2 and the post-filter unit 3A can use a bit shifter instead of a multiplier having a large number of gates. Hereinafter, specific configurations of the pre-filter unit 2A and the post-filter unit 3A using the bit shifter will be described.

FIG. 8 is a circuit diagram showing a specific configuration example of the pre-filter unit having 11 taps according to the present embodiment.

As shown in FIG. 8, the pre-filter unit 2A includes bit shifters 201 to 21 as coefficient applying means.
2. It has delay elements 213 to 222 and adders 223 to 232 as adding means. Output means is constituted by the bit shifter 212.

In the pre-filter unit 2A, the bit shifters 201-203 and 209-203
At 211, the input signal SIN is multiplied by 1 and the bit shifter 2
From 04 to 208, the input signal SIN is doubled. Also,
The output signal of the adder 232 is multiplied by 1/16 by the bit shifter 212 as output means.

The signal S 201 multiplied by 1 by the bit shifter 201 is delayed by a predetermined time by the delay element 213 and input to the adder 223. The signal S202 multiplied by 1 by the bit shifter 202 is input to the adder 223.
In the adder 223, the two signals S201 and S
202 are added, and as a signal S223, the delay element 21
4, the signal is delayed by a predetermined time and input to the adder 224. The signal S203 multiplied by one by the bit shifter 203 is input to the adder 224.

In the adder 224, a signal S223 including two signals S201 and S202 multiplied by 1 and a signal S203
Are added to each other, delayed as a signal S224 by a delay element 215 for a predetermined time, and input to an adder 225. The signal S204 doubled by the bit shifter 204 is added to the adder 2
25.

In the adder 225, the signal S224 including the three signals S201, S202 and S203 multiplied by 1 and the signal S204 are added, and the signal S225 is delayed by a predetermined time by the delay element 216 and input to the adder 226. You. The signal S20 doubled by the bit shifter 205
5 is input to the adder 226.

In the adder 226, a signal S225 including three signals S201, S202, S203 multiplied by 1 and a signal S204 multiplied by 2 are added to a signal S205, and the added signal is set as a signal S226 by a delay element 217 for a predetermined time. The signal is delayed and input to the adder 227. The signal S206 doubled by the bit shifter 206 is input to the adder 227.

The adder 227 outputs a signal S226 including three signals S201, S202 and S203 multiplied by 1 and two signals S204 and S205 multiplied by 2 and a signal S2.
06 is added to the delay element 218 as a signal S227.
, And is input to the adder 228. The signal S207 doubled by the bit shifter 207 is input to the adder 228.

The adder 228 outputs a signal S227 including three signals S201, S202 and S203 multiplied by one and three signals S204, S205 and S206 multiplied by two.
And a signal S 207 are added, delayed as a signal S 228 by a delay element 219 for a predetermined time, and input to an adder 229. The signal S2 doubled by the bit shifter 208
08 is input to the adder 229.

In an adder 229, a signal S228 including three signals S201, S202, S203 multiplied by one and four signals S204, S205, S206, S207 multiplied by two and a signal S208 are added, and a signal S229 is added.
Is delayed for a predetermined time by the delay element 220,
Input to 0. The signal S209 multiplied by the bit shifter 209 is input to the adder 230.

In the adder 230, three signals S201, S202, S203 multiplied by one and five signals S204, S205, S206, S207, S2 multiplied by two are obtained.
08 is added to the signal S229 and the signal S209.
The signal S230 is delayed for a predetermined time by the delay element 221 and input to the adder 231. Also, the bit shifter 21
The signal S210 multiplied by 0 is input to the adder 231.

In the adder 231, four signals S201, S202, S203, 209 multiplied by one and five signals S204, S205, S206, S20 multiplied by two are obtained.
7, the signal S230 including S208 and the signal S210 are added, delayed as a signal S231 by the delay element 222 for a predetermined time, and input to the adder 232. The signal S211 multiplied by the bit shifter 211 is input to the adder 232.

In the adder 232, the five signals S201, S202, S203, 209, and S210 which have been multiplied by one and the five signals S204, S205, and S20 which have been multiplied by two.
S231 and S2 including S207, S207 and S208.
11 is added to the bit shifter 2 as a signal S232.
12 is input.

In the bit shifter 212, the six signals S201, S202, S203, 20
9, S210, S211 and five doubled signals S
The signal S232 including 204, S205, S206, S207, and S208 is multiplied by (1/16) and output to the subsequent-stage filter unit 3 as the signal S2.

FIG. 9 is a diagram showing the frequency characteristics of the pre-filter unit of FIG. 8 having such a configuration. As shown in FIG. 9, the pre-filter unit 2A of FIG. 8 has a frequency characteristic that has no passband ripple but lacks sharpness near the cutoff frequency fc.

FIG. 10 shows a case where the number of taps according to this embodiment is 19
FIG. 9 is a circuit diagram illustrating a specific configuration example of a subsequent-stage filter unit.

As shown in FIG. 10, the post-filter unit 3A includes bit shifters 301 to 301 as coefficient adding means.
20, delay elements 321 to 338, and adders 339 to 356 as adding means. Output means is constituted by the bit shifter 320.

In the latter-stage filter section 3A, the input signal SIN is multiplied by 2 in the bit shifters 301 and 319, and the input signal SIN is multiplied by 1 in the bit shifters 302 and 318, and the bit shifters 303, 304, 316 and 3
17, the input signal SIN is multiplied by 0, and the bit shifter 30
At 5 to 315, the input signal SIN is doubled. Further, the output signal of the adder 356 is multiplied by 1/16 by the bit shifter 320 as output means.

The signal 301 multiplied by -2 by the bit shifter 301 is delayed for a predetermined time by the delay element 321 and input to the adder 339. The signal S302 multiplied by −1 by the bit shifter 302 is input to the adder 339. In the adder 339, the signal S301 multiplied by -2 and-
The signal S302 multiplied by 1 is added, delayed as a signal S339 by the delay element 322 for a predetermined time, and input to the adder 340. The signal S303 multiplied by 0 by the bit shifter 303 is input to the adder 340.

In the adder 340, the signal S3 multiplied by -2
The signal S 339 including the signal S 302 multiplied by 01 and −1 is added to the signal S 303, delayed as a signal S 340 by the delay element 323 for a predetermined time, and input to the adder 341. The signal S30 multiplied by 0 by the bit shifter 304
4 is input to the adder 341.

In the adder 341, the signal S3 multiplied by -2 is obtained.
The signal S 340 and the signal S 304 including the signal S 302 multiplied by 01 and −1 and the signal S 303 multiplied by 0 are added, and the signal S 341 is delayed for a predetermined time by the delay element 324 and input to the adder 342. The signal S305 doubled by the bit shifter 305 is input to the adder 342.

In the adder 342, the signal S3 multiplied by -2
A signal S341 and a signal S305 including a signal S302 multiplied by 01 and -1 and signals S303 and S304 multiplied by 0.
Are added to each other, delayed as a signal S342 by a delay element 325 for a predetermined time, and input to an adder 343. The signal S306 doubled by the bit shifter 306 is added to the adder 34.
3 is input.

In the adder 343, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the signal S342 including the doubled signal S305 and the signal S306 are added to generate a signal S343.
Is delayed by the delay element 326 for a predetermined time,
4 is input. The signal S307 doubled by the bit shifter 307 is input to the adder 344.

In the adder 344, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and doubled signals S305, S3
The signal S343 including the signal S06 and the signal S307 are added to each other, delayed as a signal S344 by a delay element 327 for a predetermined time, and input to the adder 345. Also, the bit shifter 308
The signal S308 doubled by the above is input to the adder 345.

In the adder 345, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
07 and the signal S308 are added, delayed as a signal S345 by a delay element 328 for a predetermined time, and input to the adder 346. Also, the bit shifter 309
The signal S 309 doubled by the above is input to the adder 346.

In the adder 346, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S345 including the signal 08 and the signal S309 are added, delayed as a signal S346 by a delay element 329 for a predetermined time, and input to the adder 347. Also, the bit shifter 310
The signal S <b> 310 doubled by the above is input to the adder 347.

In the adder 347, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S346 including the signal 09 is added to the signal S310, and is added as a signal S347 to the adder 348 after being delayed for a predetermined time by the delay element 330. Also, the bit shifter 311
The signal S311 multiplied by 2 is input to the adder 348.

In the adder 348, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S347 including 10 and the signal S311 are added, delayed as a signal S348 by the delay element 331 for a predetermined time, and input to the adder 349. Also, the bit shifter 312
The signal S312 doubled by the above is input to the adder 349.

In the adder 349, the signal S3 multiplied by -2 is
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S348 including S11 and the signal S312 are added, delayed as a signal S349 by the delay element 332 for a predetermined time, and input to the adder 350. Also, the bit shifter 313
The signal S <b> 313 doubled by the above is input to the adder 350.

In the adder 350, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S 349 including S 12 and the signal S 313 are added, delayed as a signal S 350 by a delay element 333 for a predetermined time, and input to the adder 351. Also, the bit shifter 314
The signal S <b> 314 doubled by the above is input to the adder 351.

In the adder 351, the signal S3 multiplied by -2 is obtained.
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S350 including the signal 13 and the signal S314 are added, delayed as a signal S351 by the delay element 334 for a predetermined time, and input to the adder 352. Also, the bit shifter 315
The signal S <b> 315 doubled by the above is input to the adder 352.

In the adder 352, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S 351 including S 14 and the signal S 315 are added, delayed as a signal S 352 by a delay element 335 for a predetermined time, and input to the adder 353. Also, the bit shifter 316
The signal S316 multiplied by 0 is input to the adder 353.

In the adder 353, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, and the doubled signals S305 to S3
The signal S 352 including S 15 and the signal S 316 are added, delayed as a signal S 353 by a delay element 336 for a predetermined time, and input to the adder 354. Also, the bit shifter 317
The signal S317 multiplied by 0 is input to the adder 354.

In the adder 354, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, S316 and the doubled signal S3
Signals S 353 and S 317 including S <b> 05 to S <b> 315 are added, delayed as a signal S <b> 354 by a delay element 337 for a predetermined time, and input to the adder 355. The signal S 318 multiplied by −1 by the bit shifter 318 is added to an adder 355.
Is input to

In the adder 355, the signal S3 multiplied by -2
01, -1 times signal S302, 0 times signal S3
03, S304, S316, and S317, and the signal S354 and the signal S including the doubled signals S305 to S315.
318 are added, and the delay element 338 is added as a signal S355.
, And is input to the adder 356. The signal S <b> 319 multiplied by −2 by the bit shifter 319 is input to the adder 356.

In the adder 356, the signal S3 multiplied by -2
Signal S35 including 01, -1 times signals S302 and S318, 0 times signals S303, S304, S316 and S317, and 2 times signals S305 to S315.
5 and the signal S319 are added and input to the bit shifter 320 as a signal S356.

In the bit shifter 320, the signals S301 and S319 multiplied by -2 and the signal S3 multiplied by -1
02, S318, 0 times multiplied signals S303, S304,
S316, S317, and the doubled signal S305
The signal S356 including S315 is multiplied by (1/16) and output as the signal SOUT.

FIG. 11 is a block diagram of FIG.
FIG. 9 is a diagram illustrating frequency characteristics of a subsequent-stage filter unit. FIG.
As shown in FIG. 10, the post-filter unit 3A of FIG. 10 has frequency characteristics in which only one passband ripple exists and the steepness near the cutoff frequency fc is sufficient.

FIG. 12 is a diagram showing the frequency characteristics of the whole FIR filter in which the pre-stage filter unit of FIG. 8 and the post-stage filter unit of FIG. 10 are cascaded. As shown in FIG. 12, the FIR filter according to the present embodiment has a frequency characteristic obtained by combining the frequency characteristic of the former-stage filter unit of FIG. 8 and the frequency characteristic of the latter-stage filter unit of FIG. That is,
The FIR filter according to the present embodiment can obtain a signal SOUT having a flat characteristic without a ripple and a sharp characteristic near the cutoff frequency fc by combining the frequency characteristics of the two-stage filter units.

As described above, according to the present embodiment, the number of taps is set within a range where no passband ripple occurs.
The steepness near the cutoff frequency is set to a gentle value, and the FIR filter coefficient h (n) and its sum are set to powers of two.
A pre-filter unit 2A that passes a low-frequency component up to the frequency fp of the IN and outputs a signal S2 having no passband ripple and a gradual steepness near the cutoff frequency fc; S2 is set to a value that can lift a gentle part in the pass band of the signal S2 and can be corrected so that the characteristic near the cutoff frequency fc becomes steep, and the FIR filter coefficient h (n) and its sum are set to powers of two, the passband is flat without ripples,
A signal S having a sharp characteristic near the cutoff frequency fc
Since the subsequent-stage filter unit 3A that generates and outputs OUT is connected in cascade, it is not necessary to use a multiplier having a large number of gates, and the number of gates can be reduced. The reduction in the number of gates increases the degree of freedom in layout, increases the maximum operating frequency, reduces the area per chip, and thus improves the yield and the advantage.

FIG. 13 is a diagram showing the frequency characteristics of a two-stage FIR filter according to the present invention having a cutoff frequency of 3 MHz and a conventional FIR filter having a one-stage configuration and 31 taps. In FIG. 13, the curve shown by the broken line is the FI of the present application.
The frequency characteristic of the R filter is shown, and the curve shown by the solid line shows the frequency characteristic of the conventional FIR filter.

As shown in FIG. 13, the FIR according to the present invention
Although the FIR filter eliminates the multiplier by limiting the coefficient and its sum to a power of two, the number of gates is greatly reduced, but the number of gates in the first and second stages is large.
By adopting a stage configuration, a better frequency characteristic can be obtained with the same number of taps as an ideal FIR filter that has many significant digits (for example, 6 digits) of coefficients.

In other words, according to the FIR filter of the present invention, even if the number of gates is reduced by limiting the total number of coefficients and their sums to powers of two, the desired method can be achieved by the coefficient selection method and the number of stages. It is possible to obtain properties.

The FIR filter having the above characteristics is applied as a band limiting LPF of the luminance signal Y or the color difference signals Cb and Cr in the digital video encoder because of the property that the group delay is constant (that is, the signal waveform does not collapse). It is possible to

FIG. 14 is a block diagram showing a configuration example of a digital video encoder employing the FIR filter according to the present invention as an LPF.

As shown in FIG. 14, the digital video encoder 10 comprises an LPF 11 for a luminance signal Y, an LPF 12 for a color difference signal Cb, an LPF 13 for a color difference signal Cr,
It has a delay circuit 14, a modulation circuit 15, and a synthesis circuit 16.

The LPF 11 is configured as shown in FIG. 1, that is, the number of taps is set to a value such that the steepness near the cutoff frequency becomes gentle within a range where the passband ripple does not occur, and the filter coefficient h (N) and the pre-filter unit 2A whose sum is set to a power of 2
It is possible to correct the signal S2 from the pre-filter unit 2A with the number of taps so that a gentle portion in the pass band of the signal S2 can be lifted and the characteristic near the cutoff frequency fc becomes steep. It has a two-stage configuration in which a post-filter unit 3A whose value is set to a possible value and whose filter coefficient h (n) and its sum are set to a value of a power of 2 is cascaded. The frequency component is extracted, and a luminance signal Y11 having a characteristic in which the passband is flat without ripple and has a sharp characteristic near the cutoff frequency fc is output to the delay circuit 14.

The LPF 12 is configured as shown in FIG. 1, that is, the number of taps is set to a value such that the steepness near the cutoff frequency becomes gentle within a range in which no passband ripple occurs, and the filter coefficient h (N) and the pre-filter unit 2A whose sum is set to a power of 2
It is possible to correct the signal S2 from the pre-filter unit 2A with the number of taps so that a gentle portion in the pass band of the signal S2 can be lifted and the characteristic near the cutoff frequency fc becomes steep. It has a two-stage configuration in which a post-filter unit 3A whose value is set to a possible value and whose filter coefficient h (n) and its sum are set to a power of 2 is cascaded. The band component is extracted, and a color difference signal Cb12 having a characteristic in which the pass band is flat without ripple and has a sharp characteristic near the cutoff frequency fc is output to the modulation circuit 15.

The LPF 13 is configured as shown in FIG. 1, that is, the number of taps is set to a value such that the steepness near the cutoff frequency becomes gentle within a range where the passband ripple does not occur, and the filter coefficient h (N) and the pre-filter unit 2A whose sum is set to a power of 2
With respect to the signal S2 from the pre-filter unit 2, the number of taps can be corrected so that a gentle portion in the pass band of the signal S2 can be lifted and the characteristic near the cutoff frequency fc becomes steep. It has a two-stage configuration in which the post-filter unit 3A is set to a possible value, and the filter coefficient h (n) and the sum thereof are set to a power of two in cascade. The band component is extracted, and a color difference signal Cr13 having a characteristic in which the passband is flat without ripple and has a sharp characteristic near the cutoff frequency fc is output to the modulation circuit 15.

The delay circuit 14 outputs the luminance signal Y14 by delaying the luminance signal Y11 by the LPF 11 by a predetermined time, for example, the time required for the modulation processing of the modulation circuit 15.

The modulation circuit 15 receives the color difference signal Cb12 from the LPF 12 and the color difference signal Cr13 from the LPF 13 and performs a predetermined modulation process to obtain a color signal.
15 is output.

The synthesizing circuit 16 synthesizes the luminance signal Y11 from the delay circuit 14 and the chrominance signal C15 from the modulating circuit 15 and outputs a composite video signal S16.

Here, taking the LPF (FIR filter) for the luminance signal Y as an example, an example of setting the number of taps and the FIR filter coefficient, and the frequency characteristics will be described.

FIG. 15 is a diagram showing a first setting example of the number of taps of the LPF for the luminance signal Y and the FIR filter coefficient. FIG. 15 shows two setting examples when the cutoff frequency fc is 6 MHz (mode 0; MD0) and when the cutoff frequency fc is 3 MHz (mode 1; MD1).

In the example of mode 0 shown in FIG. 15, the pre-filter unit 2A sets the number of taps to a value 13 at which the steepness near the cutoff frequency becomes gentle within a range where no passband ripple occurs, and , FIR filter coefficient h
(N) and its sum are power-of-two values (0, 0, 0,
1,2,4,2,4,2,1,0,0,0 x 1/1
6) and the frequency f of the input digital signal SIN
The low-pass component up to p is passed and output as a signal S2 to the subsequent filter unit 3A.

The post-filter unit 3A is different from the signal S2 from the pre-filter unit 2A in that the number of taps does not cause any passband ripple and has a gentle frequency characteristic near the cutoff frequency. The value is set to a value 23 that can lift a gentle part in the pass band (for example, the number of ripples is 1) and can correct the characteristic in the vicinity of the cutoff frequency fc to be steep.
Further, the FIR filter coefficient h (n) and the sum thereof are represented by powers of 2 (0, 0, 0, 0, 0, 0, 0, −1, −
1,1,4,2,4,1, -1, -1,0,0,0,
0, 0, 0, 0 × 1/8), the frequency characteristic of the output signal S2 of the pre-filter unit 2A, the signal whose passband is flat without ripple, and whose characteristic is sharp near the cutoff frequency fc. SOUT is generated and output.

Further, in the example of mode 1 shown in FIG. 15, the number of taps in the pre-filter unit 2 is set to a value 13 at which the steepness near the cutoff frequency becomes gentle within a range where the passband ripple does not occur. , And the FIR filter coefficient h (n) and its sum are powers of two (0, 1, 1,
1,2,2,2,2,2,1,1,1,0 x 1/1
6) and the frequency f of the input digital signal SIN
The low-pass component up to p is passed and output as a signal S2 to the subsequent filter unit 3A.

The post-filter unit 3A is different from the signal S2 from the pre-filter unit 2A in that the number of taps does not generate a passband ripple and has a gentle frequency characteristic near a cutoff frequency. The value is set to a value 23 that can lift a gentle part in the pass band (for example, the number of ripples is 1) and can correct the characteristic in the vicinity of the cutoff frequency fc to be steep.
In addition, the FIR filter coefficient h (n) and its sum are powers of 2 (0, 0, -2, -1, 0, 0, 2, 2, 2).
2,2,2,2,2,2,2,2,2,0,0, -1,
−2, 0, 0 × 1/16), the frequency characteristic of the output signal S2 of the pre-filter unit 2A is shown as a signal SOUT having a flat characteristic without a ripple in the passband and a sharp characteristic near the cutoff frequency fc. Is generated and output.

FIGS. 16 and 17 show LPs in which the number of taps and FIR filter coefficients are set as shown in FIG.
It is a figure showing the frequency characteristic of F whole. As shown in FIGS. 16 and 17, the LPF in which the number of taps and the FIR filter coefficient are set as shown in FIG. 15 has a flat passband without any ripple by synthesizing the frequency characteristics of the two-stage filter unit. Thus, a signal SOUT having a sharp characteristic near the cutoff frequency fc can be obtained.

FIG. 18 is a diagram showing a second setting example of the number of taps of the LPF for the luminance signal Y and the FIR filter coefficient. In FIG. 18, the cutoff frequency fc is 6M
A setting example in the case of Hz is shown.

In the example shown in FIG. 18, the pre-filter unit 2A
Is within the range where the number of taps does not cause passband ripple,
A value 1 that makes the characteristics leading to the stop band STB gentle.
3 and the FIR filter coefficient h (n) and its sum are powers of 2 (0, 0, 0, 2, 4, 8,
(4, 8, 4, 2, 0, 0, 0 × 1/32), passes the low-frequency component of the input digital signal SIN up to the frequency fp, and outputs it as a signal S2 to the post-filter unit 3A.

The rear-stage filter unit 3A has a number of taps in which the pass-band ripple does not occur and the front-stage filter unit 2A has a frequency characteristic in which the steepness near the cutoff frequency is gentle.
From the signal S2, a gentle portion in the pass band of the signal S2 can be raised (for example, the number of ripples is 1), and the characteristic near the cutoff frequency fc can be corrected to be steep. Is set to 23, and the FIR filter coefficient h (n) and its sum are
Power of 2 values (0, 0, 0, 0, 0, 0, 0, -1,
-1,1,4,2,4,1, -1, -1,0,0,0,
0, 0, 0, 0 × 1/8), and as described above, the frequency characteristic of the output signal S2 of the pre-filter unit 2A is flat with no ripple and a sharp cutoff frequency fc. A signal SOUT having characteristics is generated and output.

FIGS. 19 and 20 show LPs in which the number of taps and the FIR filter coefficient are set as shown in FIG.
It is a figure showing the frequency characteristic of F whole. As shown in FIGS. 19 and 20, the LPF in which the number of taps and the FIR filter coefficient are set as shown in FIG. 18 has a flat passband without ripples by synthesizing the frequency characteristics of the two-stage filter unit. Thus, a signal SOUT having a sharp characteristic near the cutoff frequency fc can be obtained.

Note that the FIR filter coefficients and their sum are 2
16 and 19 showing the frequency characteristics of an LPF having a cut-off frequency fc of 6 MHz for the luminance signal Y, the frequency characteristic around 27 MHz rises like a mountain. . However, the gain is -20dB
In the vicinity, and when an actual image was confirmed on the verification FPGA board, no abnormality was found, so it can be determined that there is no problem.

Next, the operation of FIG. 14 will be described. The input luminance signal Y has its low-frequency component extracted by an LPF 11, and is output to a delay circuit 14 as a luminance signal Y11 having a characteristic in which a pass band is flat without ripples and whose cutoff frequency fc is steep. You. The input chrominance signal Cb has its low-frequency component extracted by the LPF 12, and the passband has no ripple and is flat, and the cutoff frequency f
It is output to the modulation circuit 15 as a color difference signal Cb12 having a sharp characteristic near c. Similarly, the input chrominance signal Cr has its low-frequency component extracted by the LPF 13, and the passband has no ripple and is flat, and the cutoff frequency fc
The vicinity is output to the modulation circuit 15 as a color difference signal Cr13 having a steep characteristic.

In the delay circuit 14, the luminance signal Y11 from the LPF 11 is delayed by, for example, the time required for the modulation processing of the modulation circuit 15, and is converted into a luminance signal Y14.
Is output to The modulation circuit 15 performs a predetermined modulation process on the color difference signal Cb12 by the LPF 12 and the color difference signal Cr13 by the LPF 13. As a result, the color signal S15
Is generated and output to the synthesis circuit 16. Then, in the synthesizing circuit 16, the luminance signal Y11 by the delay circuit 14 is output.
And the color signal C15 by the modulation circuit 15 are synthesized,
It is output as a composite video signal S16.

According to the digital video encoder, the LPF 11 for the luminance signal, the LPF 12 for the chrominance signal Cb, and the LPF 13 for the chrominance signal Cr have the same tap number as long as the passband ripple does not occur. The FIR filter coefficient h (n) and its sum are set to values of powers of 2, and low-frequency components of the input digital signal SIN up to the frequency fp are passed, and the passband ripple is set. The former filter section 2A which outputs a signal S2 having a gentle steepness in the vicinity of the cutoff frequency fc and the portion where the number of taps is gentler in the pass band of the signal S2 than the signal S2 from the previous filter section 2 Is set to a value that can be corrected so that the characteristic near the cutoff frequency fc becomes steep. , And, FIR filter coefficients h
(N) and the sum thereof are set to powers of two, the pass band is flat without ripples, and the post-filter unit 3A which generates and outputs a signal SOUT having a characteristic that the cutoff frequency fc has a steep characteristic. Are cascaded, it is not necessary to use a multiplier having a large number of gates, and the total number of gates can be reduced. The reduction in the number of gates increases the degree of freedom in layout, increases the maximum operating frequency, reduces the area per chip, and thus improves the yield and the advantage.

[0095]

As described above, according to the present invention,
It is possible to provide a digital filter that can reduce the number of gates, increase the degree of freedom in layout, increase the maximum operating frequency, reduce the area per chip, and improve the yield.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an FIR filter according to the present invention.

FIG. 2 is a diagram for explaining a frequency characteristic and a passband ripple of an FIR filter.

FIG. 3 is a diagram illustrating a setting example of the number of taps and an FIR filter coefficient of a pre-stage filter unit and a post-stage filter unit according to the present invention.

FIG. 4 is a diagram showing a relationship between the number of taps of an FIR filter and frequency characteristics.

FIG. 5 is a diagram illustrating frequency characteristics of an FIR filter when the number of taps is 11;

FIG. 6 is a diagram illustrating a frequency characteristic of the FIR filter when the number of taps is 17;

FIG. 7 is a diagram illustrating frequency characteristics of an FIR filter when the number of taps is 51.

FIG. 8 is a circuit diagram showing a specific configuration example of a pre-filter unit having 11 taps according to the embodiment.

FIG. 9 is a diagram illustrating frequency characteristics of a pre-filter unit in FIG. 8;

FIG. 10 is a circuit diagram showing a specific configuration example of a post-stage filter unit having 19 taps according to the embodiment.

FIG. 11 is a diagram illustrating frequency characteristics of a post-filter unit of FIG. 10;

12 is a diagram showing the frequency characteristics of the entire FIR filter in which the pre-stage filter unit of FIG. 8 and the post-stage filter unit of FIG. 10 are cascaded.

FIG. 13 shows a cutoff frequency of 3 MHz according to the present invention;
It is a figure which shows the frequency characteristic of the FIR filter of a stage structure, and the conventional FIR filter of the tap number 31 with a 1 stage structure.

FIG. 14 is a block diagram illustrating a configuration example of a digital video encoder that employs an FIR filter according to the present invention as an LPF.

FIG. 15 shows the number of taps of the LPF for luminance signal Y and FI.
FIG. 7 is a diagram illustrating a first setting example of an R filter coefficient.

16 is a diagram illustrating frequency characteristics of an LPF in which the number of taps and the FIR filter coefficient are set as illustrated in FIG.

17 is a diagram illustrating a frequency characteristic of an LPF in which the number of taps and the FIR filter coefficient are set as illustrated in FIG.

FIG. 18 shows the number of taps of the LPF for luminance signal Y and FI.
FIG. 9 is a diagram illustrating a second setting example of an R filter coefficient.

19 is a diagram illustrating a frequency characteristic of the LPF in which the number of taps and the FIR filter coefficient are set as illustrated in FIG. 18;

FIG. 20 is a diagram illustrating a frequency characteristic of an LPF in which the number of taps and the FIR filter coefficient are set as illustrated in FIG. 18;

FIG. 21 is a diagram illustrating a configuration example of a conventional FIR filter.

[Explanation of symbols]

1A: FIR filter, 2A: pre-filter unit, 201
~ 212 ... bit shifter, 213 ~ 222 ... delay element,
223-232: Adder, 3A: Post-filter unit, 30
1 to 320... Bit shifters, 321 to 338... Delay elements, 339 to 356.

Claims (16)

[Claims] An impulse response is represented by a finite time length,
The impulse response is a filter coefficient, and includes a plurality of coefficient assigning means for assigning a predetermined filter coefficient to an input signal in parallel, and an adding means for adding a plurality of signals to which the filter coefficient is assigned. A digital filter, comprising: a digital filter, wherein a sum of the filter coefficient and the filter coefficient is set to a value of a power of two, and output means for outputting the added signal by multiplying the sum of the filter coefficient by one. 2. The digital filter according to claim 1, wherein said plurality of coefficient applying means and said output means include a bit shifter. 3. The impulse response is represented by a finite time length,
The impulse response is a filter coefficient, a digital filter having a linear phase characteristic with a finite number of taps, and the number of taps is such that the steepness near the cutoff frequency is smooth within a range where no passband ripple occurs. At least one first filter unit whose filter coefficient and the sum thereof are set to a value of a power of 2; and the number of taps is equal to that of the first filter unit. At least one set to a value that can have a frequency characteristic that can offset and lift the gentle part in the passband of the frequency characteristic and can be corrected so that the characteristic near the cutoff frequency becomes steep. A digital filter, comprising: a second filter unit; and wherein the first filter unit and the second filter unit are cascaded. 4. At least one of the first filter unit and the second filter unit is provided with a plurality of coefficient assigning means for assigning a predetermined filter coefficient to an input signal in parallel, and a filter coefficient is given. 4. The digital filter according to claim 3, further comprising: an adding unit that adds a plurality of signals; and an output unit that outputs the signal added by the adding unit by multiplying the sum of filter coefficients by one. 5. The digital filter according to claim 4, wherein said plurality of coefficient applying means and said output means include a bit shifter. 6. The impulse response is represented by a finite time length,
A digital filter in which the impulse response is a filter coefficient and has a linear phase characteristic with a finite number of taps, and the number of taps is such that the steepness near the cutoff frequency is smooth within a range where no passband ripple occurs. The first filter unit that allows the low frequency component of the input digital signal to pass through is set to a value that can have the following frequency characteristics, and the filter coefficient and the sum thereof are set to a power of two. The frequency characteristic of the output signal of the first filter unit can be corrected by canceling out a gentle portion in a pass band in the frequency characteristic of the output signal and raising the characteristic near the cutoff frequency. It is set to a value that can be held, the passband is flat with no ripple, and a signal is generated and output with a characteristic that is sharp near the cutoff frequency. Digital filter and a second filter portion. 7. At least one of the first filter unit and the second filter unit is provided with a plurality of coefficient applying means for applying a predetermined filter coefficient to an input signal in parallel, and a filter coefficient is provided. 7. The digital filter according to claim 6, further comprising: an adding unit that adds a plurality of signals; and an output unit that outputs the signal added by the adding unit by multiplying the sum of filter coefficients by one. 8. The digital filter according to claim 7, wherein said plurality of coefficient applying means and said output means include a bit shifter. 9. A luminance signal filter for extracting a low-frequency component of a luminance signal, and a color-difference signal filter for extracting a low-frequency component of a color-difference signal. A digital video encoder that generates a video signal based on a color difference signal obtained by a filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length, and the impulse response is a filter. A plurality of coefficient assigning means for assigning a predetermined filter coefficient in parallel to the input signal, and an adding means for adding a plurality of signals to which the filter coefficient is assigned, wherein the filter coefficient The sum of the filter coefficients is set to a value of a power of 2, and the added signal is multiplied by one times the sum of the filter coefficients. Digital video encoder including a digital filter having an output means for force. 10. The digital video encoder according to claim 9, wherein said plurality of coefficient assigning means and said output means include a bit shifter. 11. A luminance signal filter for extracting a low-frequency component of a luminance signal, and a color-difference signal filter for extracting a low-frequency component of a chrominance signal. A digital video encoder that generates a video signal based on a color difference signal obtained by a filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length, and the impulse response is a filter. It is a filter that has a coefficient and has a linear phase characteristic with a finite number of taps, and the tap number can have a frequency characteristic in which the steepness near the cutoff frequency becomes gentle as long as the passband ripple does not occur At least one of the filter coefficients and the sum thereof set to a value of a power of two. And the number of taps can compensate for the smoothed portion in the pass band of the frequency characteristic of the first filter unit and lift it up, and correct the characteristic so that the characteristic near the cutoff frequency becomes steep. At least one second filter unit set to a value capable of having a frequency characteristic that is possible, and a digital filter including a digital filter in which the first filter unit and the second filter unit are cascaded. Video encoder. 12. At least one of the first filter section and the second filter section is provided with a plurality of coefficient applying means for applying a predetermined filter coefficient to an input signal in parallel, and a filter coefficient is provided. 12. The digital video encoder according to claim 11, further comprising: an adding unit that adds a plurality of signals; and an output unit that outputs the signal added by the adding unit by multiplying the sum of filter coefficients by one. 13. The digital video encoder according to claim 12, wherein said plurality of coefficient assigning means and said output means include a bit shifter. 14. A luminance signal filter for extracting a low-frequency component of a luminance signal, and a color-difference signal filter for extracting a low-frequency component of a color-difference signal. A digital video encoder that generates a video signal based on a color difference signal obtained by a filter, wherein at least one of the luminance signal filter and the color difference signal filter has an impulse response represented by a finite time length, and the impulse response is a filter. It is a filter that has a coefficient and has a linear phase characteristic with a finite number of taps, and the tap number can have a frequency characteristic in which the steepness near the cutoff frequency becomes gentle as long as the passband ripple does not occur Value, and the filter coefficient and its sum are set to powers of two, A first filter portion for passing a low frequency component,
The number of taps can cancel out and lift a gentle part in the pass band in the frequency characteristic of the output signal of the first filter unit, and can correct the characteristic in the vicinity of the cutoff frequency so that it becomes steep. Including a digital filter having a second filter section for generating and outputting a signal having a characteristic in which the passband is flat without ripple and has a sharp characteristic near a cutoff frequency. Video encoder. 15. At least one of the first filter unit and the second filter unit is provided with a plurality of coefficient applying means for applying a predetermined filter coefficient to an input signal in parallel, and a filter coefficient is provided. 15. The digital video encoder according to claim 14, further comprising: an adding unit that adds a plurality of signals; and an output unit that outputs the signal added by the adding unit by multiplying the sum of filter coefficients by one. 16. The digital video encoder according to claim 15, wherein said plurality of coefficient assigning means and said output means include a bit shifter.