JP2527019B2 - Non-cyclic interpolation filter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a non-cyclic interpolation filter circuit that raises an output signal of a digital filter to L times the sampling frequency of an input signal.

(Prior Art) Conventionally, when an L-fold interpolation filter is realized by using an acyclic filter, for example, as shown in FIG. 5, a configuration in which an L-times interpolator 510 is connected to the input of the acyclic interpolation filter 500 is used. It is used.

The L-fold interpolator 510 inserts and outputs (L-1) zero-value signals per filter input signal at a frequency L times the filter input signal frequency. The number of coefficients of the acyclic filter 500 is N (integer), and the filter coefficients are h (0), h
(1), ..., H (N−1), and the input signal is (N−1) delay elements 520− connected in series to the input terminal.
, 520- (N-1) are moved according to the sampling pulse of the input signal, and multipliers 530-0, 530
, ..., 530- (N-1), the input delay signal moving through the delay elements 520-1, 520-2, ... 520- (N-1) is multiplied by the filter coefficient for each sampling clock. The multi-input adder 540 includes multipliers 530-0, 530-1, ... 530- (N-
An L-fold interpolation filter is realized by obtaining the sum of the output signals of 1) and outputting the output signal of the acyclic filter.

(Problems to be Solved by the Invention) However, since the non-recursive filter also operates on a zero-value signal, there is a drawback in that many arithmetic units are required and the circuit scale becomes large.

An object of the present invention is to eliminate such drawbacks of the prior art, reduce unnecessary calculation by omitting unnecessary calculation while maintaining the function of a digital filter, and use a large number of multipliers to obtain necessary multipliers. The purpose of the present invention is to provide an acyclic interpolation filter suitable for use in an LSI with a reduced circuit scale by reducing the number of.

(Means for Solving the Problem) In the present invention, the sampling frequency of the output signal is an integer with respect to the sampling frequency of the input signal (this is L).
In a non-cyclic interpolation filter having an L-fold interpolation function of doubling, an register that holds a filter input signal for a sampling period of the input signal, a multiplier that multiplies the output signal of the register by L filter coefficients, and The output signal of the multiplier and the output signal of the arithmetic circuit of the second stage, which will be described later, are added to form the arithmetic circuit of the first stage configured by an adder, and the output signal of the register and L filter coefficients A first multiplier comprising a multiplier for multiplying, an adder for adding the output signal of the multiplier and the output signal of the arithmetic circuit of the next stage, and an L delay device for receiving the output signal of the adder as input 2nd, 3rd, ..., (K-1) th arithmetic circuits,
A non-comprising non-comprising arithmetic circuit of the Kth stage composed of a multiplier for multiplying the output signal of the register by L filter coefficients, and an L delay device which receives the output signal of the multiplier and delays and outputs it for L cycles. It is a cyclic interpolation filter.

The present invention is the non-cyclic interpolation filter, wherein the L delay device comprises L registers connected to the input terminals and a selector that selects one from the outputs of the registers and uses it as an output signal.

(Operation) FIG. 5 shows an L (integer) times acyclic interpolation filter. Here, the number of coefficients of the acyclic filter 500 is N
(Integer), the filter coefficient is h (0), h (10, ..., h (N-
In the case of 1), (k−1) L ≦ NK <L (k is an integer) (1), N = KL (2) is newly set, and h (N) = h (N + 1) = ... If h (KL-1) = 0 (3) is expanded, the acyclic filter after expansion is equivalent to the original acyclic filter. Therefore, in the following description, N is an integer multiple of L.

When the sampling period of the output signal is T, the input / output relational expression of the non-recursive filter is expressed by Expression (4) when the input and output at time mT are w (mT) and y (mT), respectively.

The relational expression of the input and output of the L times interpolator is that the input and output at time mT are x and
If (mT) and w (mT) are given, it is expressed by the equation (5).

The input / output relationship of the non-cyclic interpolation filter is expressed by equations (4) and (5).
Can be represented by Furthermore, equations (2) and (4)
From (5), even if the term that w (mT) = 0 is omitted, it does not affect the result. Therefore, if omitted, the input / output relationship of the acyclic interpolation filter is expressed by equation (6).

(However, m% L represents the remainder when m is divided by L.) For simplicity, an example of Expression (6) is shown. If N = 12 and L = 4, then K = 3, so the input / output relationship is as follows.

Since the result of multiplying the delay data of the input signal by the filter coefficient is equivalent to the result of multiplying the input signal by the filter coefficient with a similar delay, the non-cyclic interpolation filter This can be realized by relaxing the K pieces of data by delaying the product of the filter coefficients extracted at L intervals by an integer multiple of LT time. Furthermore, one input signal is L
Multiplying each filter coefficient and the result of multiplying the input signal and the filter coefficient by one cycle each are included in the output signal, so that the multiplier operating in the sampling cycle of the output signal is set to the filter coefficient. Since it is possible to switch and multiplex L times, the number of multipliers required is K.

From the above, the non-cyclic interpolation filter of the present invention is
A register that holds the input signal for the sampling period of the input signal, a multiplier that sequentially switches and multiplies the output signal of the register and L filter coefficients, and the output signal of the multiplier and the output signal of the arithmetic circuit in the subsequent stage are added. And the output signal of the adder is the output signal
It is realized by connecting K arithmetic circuits each configured by an L delay device that delays and outputs the delayed signals. As a result, the number of multipliers can be reduced to about 1 / L as compared with the conventional method.

(Embodiment) FIG. 1 is an embodiment for realizing the present invention. The filter input signal input to the filter input terminal 100 is
It is held in register 160 during the period of the input signal. The multipliers 120-1, 120-2, ..., 120-K multiply the output signal of the register 160 by the filter coefficient at the cycle of the output signal. Register 1
When the output of 60 is updated, the cycle is set to 0, and each cycle of the output signal is set to cycle 1, cycle 2, ..., Cycle (L-1), which is input to the multipliers 120-1, 120-2, ..., 120-K. The filter coefficients of the filter are as shown in FIG. Adder 130-1,130-2, ..., 1
30-K is the output signal of the multiplier and the L delay device 150-2, ..., 150-
Add the K output signals. L delay device 150-2, ..., 150-K
, Receives the output signals of the adders 130-1, 130-2, ..., 130-K and outputs them after delaying for L cycles. The output signal of the adder 130-1 becomes the output signal of the acyclic interpolation filter.

FIG. 2 shows an embodiment for realizing the L delay device in FIG. The input signal is output from the input terminal 200 in the order of the output signal in sequence. The registers 220-1, 220-2, ...
It is transferred to L, delayed by K cycles, and output from the output terminal 210. The L delay device shown in FIG. 2 is composed of L registers, so that the circuit scale can be reduced.

FIG. 3 shows another embodiment for realizing the L delay device in FIG. The input signal is a register 320-1, 320 that reads the input signal from the input terminal 300 at a cycle L times as long as the output signal.
-2, ..., 320-L are sequentially input to the register, and the signal held in the register is read out by the selector 330 after L delay and output terminal 3
It is output from 10. The L delay device shown in FIG. 3 has only one register and a selector operating simultaneously, so that the power consumption can be reduced.

(Effect of the Invention) According to the L-times acyclic interpolation filter configuration of the present invention, L
One multiplier, one adder, and one filter coefficient
Since it can be realized by an L delay device, the number of multipliers and adders can be reduced to nearly 1 / L of the conventional method, and the circuit configuration can be simplified.

As described above, according to the present invention, it is possible to easily downsize and simplify the cyclic interpolation filter, and the effect is extremely large.

[Brief description of drawings]

1 is a block diagram showing the configuration of the non-cyclic interpolation filter of the present invention, FIG. 2 is a block diagram showing the configuration of the L delay device of the present invention, and FIG. 3 is a block showing the configuration of the L delay device of the present invention. 4 and 5 are diagrams showing the filter coefficient input to the multiplier for each cycle, and FIG. 5 is a block diagram showing the configuration of a conventional non-cyclic interpolation filter. In the figure, 100 is a filter input terminal, 110 is a filter output terminal, 120-1, 120-2, ..., 120-K are multipliers, 130-1, 1
30-2, ... are adders, 14-1,140-2, ..., 140-K are coefficient registers, 150-2, ..., 150-K are L delay units, 160 is a register, 200 is an input terminal, 210 is an output Terminal, 220-1, 220-2,
..., 220-L is a register, 300 input terminals, 310 is an L input 1 output selector, 500 is an acyclic filter, 510 is an L-fold interpolator, 520-1,520-2 ..., 520- (N-1) is a delay Bowl, 530
-0,530-1, ..., 520- (N-1) is a multiplier, 540 is an adder, 550 is a filter input terminal, and 560 is a filter output terminal.

Claims (2)

(57) [Claims] 1. A sampling frequency of an output signal with respect to a sampling frequency of an input signal is an integer (this is L).
In a non-cyclic interpolation filter having doubled L-fold interpolation capability, a register that holds a filter input signal for a sampling period of the input signal, a multiplier that multiplies the register output signal and L filter coefficients, and the multiplication Of the output signal of the register and the output signal of the second-stage arithmetic circuit described later to form a filter output signal, and the output signal of the register and L filter coefficients A second configuration comprising a multiplier for multiplying, an adder for adding the output signal of the multiplier and the output signal of the arithmetic circuit at the next stage, and an L delay device for inputting the output signal of the adder and delaying the output by L cycles for output. , Third stage, ..., (K-1) th stage arithmetic circuit, a multiplier for multiplying the output signal of the register by L filter coefficients, and the L cycle of the output signal of the multiplier. Output L Nonrecursive interpolation filter, characterized in that it is constituted from the arithmetic circuit of the K-stage comprised of device. 2. The L delay device according to claim 1 is composed of L registers connected to input terminals and a selector for selecting one from the outputs of the registers as an output signal. An acyclic interpolation filter characterized by the following.