JPS61113314A - Sample value thinning-out digital filter - Google Patents

Sample value thinning-out digital filter

Info

Publication number
JPS61113314A
JPS61113314A JP59235409A JP23540984A JPS61113314A JP S61113314 A JPS61113314 A JP S61113314A JP 59235409 A JP59235409 A JP 59235409A JP 23540984 A JP23540984 A JP 23540984A JP S61113314 A JPS61113314 A JP S61113314A
Authority
JP
Japan
Prior art keywords
discrete signal
output
signal sequence
filter
digital filter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59235409A
Other languages
Japanese (ja)
Inventor
Botaro Hirosaki
廣崎　膨太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59235409A priority Critical patent/JPS61113314A/en
Priority to US06/795,147 priority patent/US4893265A/en
Priority to DE8585114190T priority patent/DE3578868D1/en
Priority to EP85114190A priority patent/EP0180989B1/en
Publication of JPS61113314A publication Critical patent/JPS61113314A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0283—Filters characterised by the filter structure
    • H03H17/0292—Time multiplexed filters; Time sharing filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/0664—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2218/00—Indexing scheme relating to details of digital filters
    • H03H2218/08—Resource sharing

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE:To simplify the circuit by using a register section comprising registers and adders in common for upper and lower sub-filters so as to combine efficiently a 1/2 sample value thinning-out processing and a 2-channel multiplex processing. CONSTITUTION:The 1st and 2nd discrete signal series of sampling frequency 1/T from terminals 101,102 are fed respectively to selectors 107,108 acted complementarily. Then the discrete signal series selected by the selectors 107,108 are fed respectively to multipliers 110-112 and 120-121. The output of each multiplier is given respectively registers 130-134 and adders 141-145. Then the output of the adder 145 is fed to a multiplex circuit 150 and a 1/2 thinning- out output to the 1st and 2nd discrete signal series is obtained from the output. Since the register section comprising the registers 130-134 and the adders 141-145 is used in common for the upper/lower sub-filters, the circuit is simpli fied.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は入力離散信号系列の標本化周波数を１／２に変
換するサンプル値間引きテイジタルフィルターに関する
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a sample value thinning digital filter that converts the sampling frequency of an input discrete signal sequence to 1/2.

（従来技術とその問題点） 標本化周波数変換は種々のメディアかディジタル化され
つつある現在、益々重要な技術となりつつある。たとえ
ば、最近種々の機器が開発されつつあるディジタルオー
ディオの分野では原アナログ信号を１６ビツト程度のデ
ィジタル信号に変換する必要があるが、この変換を行な
うに際して原アナロク信号を定められた標本化周波数ｆ
ｓにて標本化する必要がある。ここで、もし原アナログ
信号のスペクトラムがｆ　ｓ　／　２以内に帯域制限さ
れていないと、前記標本化Ｉこよっていわゆる折返し雑
音が発生し、信号の品質を劣化させることになる。(Prior art and its problems) Sampling frequency conversion is becoming an increasingly important technology as various media are being digitized. For example, in the field of digital audio, where various devices are being developed recently, it is necessary to convert the original analog signal to a digital signal of approximately 16 bits.
It is necessary to sample at s. Here, if the spectrum of the original analog signal is not band-limited to within f s /2, the sampling I will generate so-called aliasing noise, which will deteriorate the quality of the signal.

従って、標本化に先立って原アナログ信号をカットオフ
周波数ｆＳ／２以下のローパスフィルターに通さなけれ
ばならないが、通常、オーディオ信号に対しては７０〜
８０　ｄＢという極めて高い歪率が要求され、この規格
を満たすためには前記ローパスフィルターのロールオフ
特性を急造なものにすると共にこれによって生ずる群遅
延歪を等化しなければならない。しかしながら、もし原
アナログ信号を標本化周波数２ｆＳにて標本化するもの
とすれば、前記ローパスフィルターはディジタルフィル
ターにて実現できることになり、群遅延歪を発生するこ
となく急蹟なロールオフ特性を持たせることが可能にな
る。更に、こうして得られたディジタルフィルターの出
力を２サンプルにつき１サンプルづつ取り出せば標本化
周波数ｆｓの所望の離散信号系列が得られることになる
。Therefore, prior to sampling, the original analog signal must be passed through a low-pass filter with a cutoff frequency of fS/2 or less, but normally for audio signals
An extremely high distortion rate of 80 dB is required, and in order to meet this standard, the roll-off characteristics of the low-pass filter must be made urgent and the group delay distortion caused by this must be equalized. However, if the original analog signal is sampled at a sampling frequency of 2fS, the low-pass filter can be realized by a digital filter, which has a steep roll-off characteristic without generating group delay distortion. It becomes possible to Furthermore, by extracting one out of every two samples from the output of the digital filter thus obtained, a desired discrete signal sequence of sampling frequency fs can be obtained.

従来、この種のサンプル値間引きディジタルフィルター
に関しては多くの研究がなされており、特に有限インパ
ルス応答形（以下これをＦＩＲと略す）ディジタルフィ
ルターを適用すれば、その次数をＮ−１とした時、１／
２間引きをするための単位時間当の所要演算量かＮ’／
２で済むことが知られている。更に、ＦＩＲテイジタル
フィルターとしていわゆる係数対称なフィルターを用い
ることにすれば所要演算量がＮ／４となり非常に能率の
良い信号処理系が実現される。しかしながら、このサン
プル値間引きディジタルフィルターを用いて２チャンネ
ル分の多重処理を行なうことを考えると、フィルターの
タップ係数は１組用意するだけでよいのに対し、レジス
ターは各チャンネル各各に対応したものを用意しなけれ
ばならず装置の複雑化を招いていた。Conventionally, many studies have been conducted on this type of sample value thinning digital filter, and in particular, if a finite impulse response type (hereinafter abbreviated as FIR) digital filter is applied, when its order is set to N-1, 1/
2 Required amount of calculation per unit time for thinning out or N'/
It is known that 2 is enough. Furthermore, if a so-called coefficient-symmetrical filter is used as the FIR digital filter, the required amount of calculation becomes N/4, and a very efficient signal processing system can be realized. However, considering that multiplex processing for two channels is performed using this sample value thinning digital filter, only one set of tap coefficients for the filter needs to be prepared, whereas a register corresponding to each channel is required. had to be prepared, leading to the complexity of the equipment.

（発明の目的） 本発明は前記の如き従来の欠点を除去するサンプル値間
引きディジタルフィルターを提供するものであり、その
目的は２チャンネル多重処理と１／２サンプル値間引処
理とを効率良く結合することζこめる。(Object of the Invention) The present invention provides a sample value decimation digital filter that eliminates the above-mentioned conventional drawbacks, and its purpose is to efficiently combine two-channel multiplex processing and 1/2 sample value decimation process. I'm going to do a lot of things.

（発明の構成） 即ち、本発明はクロック周波数１／Ｔにて動作する有限
インパルス応答形ディジタルフィルタを２個のサブフィ
ルタに並列分解したディジタルフィルタであって、標本
化周波数１／Ｔの第１の離散信号系列と標本化周波数１
／Ｔの第２の離散信号系列とを入力としＴ秒毎に該第１
の離散信号系列と該第２の離散信号系列とを交互に選択
する第１のセレクターと、該第１のセレクターとは相補
的な動作ｆこて前記第２の離散信号系列と前記第１の離
散信号系列とを交互に選択する第２のセレクターと、該
第１のセレクターの出力として得られる第３の離散信号
系列か供給されクロック速度１／Ｔにて動作する第１の
サブフィルタと、前記第２のセレクターの出力として得
られる第４の離散信号系列か供給されクロック速度１／
Ｔ６ごて動作する第２のサブフィルタと、切替速度１／
Ｔにて動作する多重分離回路とより成り、特に前記第１
のサブフィルタおよび前記第２のサブフィルタが共に転
置形の構成となっており各々のレジスタ部が共通化され
その出力が前記多重分離回路に供給されていることを特
徴とするサンプル値間引きディジタルフィルターを提供
するものである。(Structure of the Invention) That is, the present invention is a digital filter in which a finite impulse response type digital filter operating at a clock frequency of 1/T is decomposed in parallel into two sub-filters, the first sub-filter having a sampling frequency of 1/T. discrete signal sequence and sampling frequency 1
/T second discrete signal sequence, and every T seconds, the first
a first selector that alternately selects the discrete signal series and the second discrete signal series; and the first selector operates in a complementary manner. a second selector that alternately selects a discrete signal series, and a first sub-filter that is supplied with a third discrete signal series obtained as an output of the first selector and operates at a clock speed of 1/T; A fourth discrete signal sequence obtained as the output of the second selector is supplied with a clock speed of 1/
A second sub-filter that operates as a T6 iron, and a switching speed of 1/
and a demultiplexing circuit operating at T, in particular, the first
A sample value thinning digital filter characterized in that both the sub-filter and the second sub-filter have a transposed configuration, each having a common register section, and an output thereof being supplied to the multiplexing/demultiplexing circuit. It provides:

（発明の原理） 以下本発明の詳細な説明する。いま、入力の標本化周波
数を１／Ｔとし、ｅｘｐ　ｆ−ｊωＴｌをＺで表わし、
いわゆるＺ変換表示にて２つの入力離散信号系列をＸＩ
　（ｚ　）　、Ｘｌ　（ｚ）と表わす。この時、前記の
１７２間引き処理を行なうためにはまずＸｌ（ｚンＸ２
（Ｚ）の各々をカットオフ周波数が高々１／４Ｔである
ようなディジタルフィルタＨ（Ｚ）に通し、しかる後ζ
こ各々の出力を１サンプルづつ間引けばよい。いま、（
Ａ（Ｚ）Ｃおよび［：Ａ（Ｚ））。が一般に離散信号系
列Ａ（Ｚ）の偶数番目のサンプルおよび奇数番目のサン
プルを取り出す演算を各々表わすものとすれば、前記１
／２間引き処理を２チヤンネル多重化して得られる出力
Ｙ　（Ｚ）は、Ｙ　（ｚ）−ＣＸｔ（ｚ）Ｈ（ｚ））ｚ
＋　ＣＸｔ（ｚ）Ｈ（ｚ））。(Principle of the Invention) The present invention will be explained in detail below. Now, let the input sampling frequency be 1/T, and express exp f−jωTl by Z,
Two input discrete signal sequences are expressed as XI in a so-called Z-transform representation.
(z) and Xl (z). At this time, in order to perform the 172 thinning process described above, first
(Z) is passed through a digital filter H(Z) whose cutoff frequency is at most 1/4T, and then ζ
Each output can be thinned out by one sample. now,(
A(Z)C and [:A(Z)). generally represent operations for extracting even-numbered samples and odd-numbered samples of the discrete signal sequence A(Z), then 1.
The output Y (Z) obtained by multiplexing /2 thinning processing with two channels is Y (z)-CXt(z)H(z))z
+CXt(z)H(z)).

と表現される。ここで、ディジタルフィルタＨ（Ｚ）は
（Ｎ−１）次のＦＩＲフィルタであるものとして、 Ｈ（ｚ）−ａｏ＋ａ、　Ｚ−”＋ａ、　ｚ−”＋・−・
−＋ａＮ−、ｚ　Ｑ１′−’）とすれば、これを次のよ
うにして２つのサフフィルタに分解できる。It is expressed as Here, assuming that the digital filter H(Z) is an (N-1) order FIR filter, H(z)-ao+a, Z-"+a, z-"+・-・
-+aN-, z Q1'-'), this can be decomposed into two suff filters as follows.

即ち、 Ｈ（ｚ）＝Ｈ＋　（ｚ”）　＋Ｚ−’Ｈ，（Ｚ　”）　
　　　　　　（３）ただし、 Ｈｔ　　（ｚ　”）　”ａ。＋ａｆｉＺ″″″＋・・−
・十ａ　Ｎ−２ｚ”″（Ｎ−”）（４）Ｈ２（ｚ　”）
　淘ａ１＋ａ、ｚ−１＋−−−−−＋　ａＮ−１ｚ−（
Ｎ−リ　（５）（１）式および（３）式より、多重化出
力Ｙ　（ｚ）は、Ｙ（Ｚ）−（（ｘ、（ｚ））ｚ＋　（
Ｘｔ（Ｚ））　、　）Ｈｌ　（Ｚ　”）、　　　　　　
　゛（（Ｘｔ（Ｚ））Ｅ＋（ＸＩ（ｚ））ｏ）ｚ−’Ｈ
ｚ（ｚ”）　　（ｅ）と表わされる。ここで（４）式お
よび（５）式で与えられるＨｌ（Ｚ”）およびＨ２（ｚ
２）ヲ各々Ｈ，（Ｚ”）　ｍａ、＋Ｚ−”Ｈ，１（Ｚ”
）Ｈ２（Ｚ　２）　−ａｔ　＋　ｚ−２ＨｔＩ（Ｚ　２
）と表わし、（Ｘｌ（ｚ）　）　”　（Ｘｔ（ｚ））　
ｏをＳ、（Ｚ）。That is, H(z)=H+ (z") +Z-'H, (Z")
(3) However, Ht (z ”) ”a. +afiZ″″″＋・・−
・10a N-2z”″(N-”) (4) H2(z ”)
Tao a1+a, z-1+----+ aN-1z-(
N-li (5) From equations (1) and (3), the multiplexed output Y (z) is Y(Z) - ((x, (z))z+ (
Xt(Z)), )Hl(Z”),
゛((Xt(Z))E+(XI(z))o)z−'H
z(z") (e).Here, Hl(Z") and H2(z") given by equations (4) and (5)
2) wo each H, (Z") ma, +Z-"H,1(Z"
)H2(Z 2) -at + z-2HtI(Z 2
) and (Xl(z) ) ” (Xt(z))
o to S, (Z).

（Ｌ　（Ｚ））　Ｅ＋　（ＸＩ　（Ｚ））、を５ｌ（Ｚ
）と表わすコトニスれば、 （６）式は、 Ｙ（Ｚ）−Ｓ、　（Ｚ）　（ａ、＋２−”Ｈ，、（Ｚ”
）　）＋８１（ｚ）ｚ−”　（ａ、＋ｚ”″”Ｈｔｘ　
（ｚ’）　）７５ｔ（ｚ）ａｏ”Ｚ−’　（８２（ｚ）
ａ、＋ｚ−’田２．（ｚ２）＋Ｚ””Ｈｔ１　　（’ン
）　）　　　　　　　　　　　　　　　　（７１と変形
され、その構成は第２図に示すものとなる。即ち、第２
図は、本発明の原理を示すためのブロック図であって、
端子２０１および端子２０２には前記の５ｔ（Ｚ）詔よ
びＳｔ　（Ｚ）が各々入力され、端子２０３からはＹ（
Ｚ）が出力される。参照番号２０４詔よび２０５は前記
ディジタルフィルターＨｔ　ｘ（ｚ　２）およびＨ□（
ｚ２）を−々表わして怠り、参照番−ｊ！２０６および
２０７は各々ａｏおよびａ、を掛は合わせる乗算　　　
　　　！器である。また、参照番号２０８，２０９，２
１０は単位遅延時間Ｔ秒のレジスターであって、参照番
号２１１゜２１２．２１３は全て加算器を表わしている
。(L (Z)) E+ (XI (Z)), 5l(Z
), then equation (6) is: Y(Z)-S, (Z) (a, +2-"H,, (Z")
) )+81(z)z-” (a,+z”””Htx
(z') )75t(z)ao"Z-' (82(z)
a, +z-' 田2. (z2)+Z""Ht1 ('n) )
The figure is a block diagram for illustrating the principle of the present invention,
The above-mentioned 5t(Z) edict and St(Z) are input to the terminals 201 and 202, respectively, and Y(
Z) is output. Reference numbers 204 and 205 refer to the digital filters Ht x (z 2) and H□ (
z2) was omitted and the reference number was -j! 206 and 207 are the multiplications of ao and a, respectively.
! It is a vessel. Also, reference numbers 208, 209, 2
10 is a register for unit delay time T seconds, and reference numbers 211, 212, and 213 all represent adders.

（７）式において、Ｈａｔ　（Ｚ”）　、ＨＨ（Ｚ”）
を更に分解していくと結局第１図に示すような本発明に
よるサンプル値間引きディジタルフィルターが得られる
ことになる。In equation (7), Hat (Z"), HH (Z")
By further decomposing, a sample value thinning digital filter according to the present invention as shown in FIG. 1 is finally obtained.

（実施例） 本発明によるサンプル値間引きディジタルフィルターの
具体的実施例を第１図に示す。ここでは簡単のためフィ
ルター次数を５次としている。図において、端子１０１
および１０２を介して標本化周波数１／Ｔなる第１の入
力離散信号系列Ｘ、　（Ｚ）および第２の入力離散信号
系列Ｘｔ　（Ｚ）が各々入力される。参照番号１０７は
第１のセレクターであって前記Ｘ、　（Ｚ）の偶数番目
サンプルとＸｔ　（Ｚ）の奇数番目サンプルとを選択多
重化することによって多重化系列５ｔ（Ｚ）を生成し乗
算器１１０，１１１，１１２に供給する。(Example) A specific example of the sample value thinning digital filter according to the present invention is shown in FIG. Here, for simplicity, the filter order is set to 5th order. In the figure, terminal 101
and 102, a first input discrete signal sequence X, (Z) and a second input discrete signal sequence X, (Z) having a sampling frequency of 1/T are input, respectively. Reference numeral 107 is a first selector which generates a multiplexed sequence 5t(Z) by selectively multiplexing the even-numbered samples of X, (Z) and the odd-numbered samples of Xt (Z). 110, 111, and 112.

また、参照番号１０８は第２のセレクターであり、前記
第１のセレクターと相補的な動作によりＸｔ（Ｚ）の奇
数番目のサンプルとＸｔ（Ｚ）の偶数番目のサンプルと
を選択多重化することによって多重化系列Ｓ。Further, reference number 108 is a second selector, which selectively multiplexes odd-numbered samples of Xt(Z) and even-numbered samples of Xt(Z) by an operation complementary to the first selector. The multiplexed sequence S.

（Ｚ）を生成し乗算器１２０，１２１，１２２に供給す
る。参照番号１３０乃至１３４はｌサンプル期間、即ち
、Ｔ秒の単位遅延を有するレジスターであって、レジス
ター１３０は乗算器１２２の出力を蓄積し、レジスター
１３１は加算器１４１を介して得られるレジスター１３
０の出力と乗算器１１２の出力との和を蓄積し、レジス
ター１３２は加算器１４２を介して得られるレジスター
１３１の出力と乗算器１２１の出力との和を蓄積し、レ
ジスター１３３は加算器１４３を介して得られるレジス
ター１３２の出力と乗算器１１１の出力との和を蓄積し
、レジスター１３４は加算器１４４を介して得られるレ
ジスター１３３の出力と乗算器１２０の出力との和を蓄
積する。また、レジスター１３４の出力は加算器１４５
を介して乗算器１１０の出力と加算されその結果得られ
る信号は多重分離回路１５０に入力される。多重分離回
路１５０は第１の入力離散信号系列Ｘ、　（Ｚ）に対す
る１／２サンプル値間引き出力（ｘｔ　（Ｚ）　Ｈ（Ｚ
））　ｇを端子１０睦介して出力すると共に、第２の入
力離散信号系列Ｘ２（ｚ）に対する１／２サンプル値間
引き出力（Ｘｚ　（Ｚ）Ｈ（Ｚ））。(Z) is generated and supplied to multipliers 120, 121, and 122. Reference numerals 130 to 134 are registers having a unit delay of l sample period, that is, T seconds, where register 130 stores the output of multiplier 122 and register 131 stores the output of register 13 obtained through adder 141.
0 and the output of the multiplier 112, the register 132 accumulates the sum of the output of the register 131 obtained via the adder 142 and the output of the multiplier 121, and the register 133 accumulates the sum of the output of the register 131 obtained via the adder 142 and the output of the multiplier The sum of the output of register 132 obtained via adder 144 and the output of multiplier 111 is accumulated, and the register 134 accumulates the sum of the output of register 133 and the output of multiplier 120 obtained via adder 144. Furthermore, the output of the register 134 is output to an adder 145.
The resulting signal is added to the output of multiplier 110 via , and the resulting signal is input to demultiplexing circuit 150 . The demultiplexer circuit 150 outputs a 1/2 sample value thinning output (xt (Z) H(Z) for the first input discrete signal sequence X, (Z).
)) Outputs g through the terminal 10 and decimates the second input discrete signal sequence X2(z) by 1/2 sample value (Xz (Z)H(Z)).

を端子１０５を介して出力する。第１図の構成から判る
ようＩこ本発ＦｆＪｌこなるサンプル値間引きディジタ
ルフィルターを用いれば、レジスター１３０，１３１゜
・−・・−、１３４および加算器１４１．・・・・・・
、１４５より成るレジスタ一部を上下のサブフィルター
間で共通化できるため回路か簡易化される。is output via terminal 105. As can be seen from the configuration of FIG. 1, if a sample value decimation digital filter of FfJl is used, registers 130, 131°, 134 and adder 141.・・・・・・
, 145 can be shared between the upper and lower subfilters, thereby simplifying the circuit.

なお、第１図において上下のサブフィルターが各々係数
対称、即ち、ａＯ”ａ４　＋　ａｌ　”ａ５であれば、
本発明によるサンプル値間引きディジタルフィルターは
第１図の乗算器１１２，１２２が不要となり第３図のよ
うに簡易化される。ここで、第１図と第３図において同
一の参照番号は同一の機能をもつ構成要素である。In addition, if the upper and lower sub-filters in FIG. 1 have symmetrical coefficients, that is, aO"a4 + al"a5, then
The sample value thinning digital filter according to the present invention eliminates the need for the multipliers 112 and 122 shown in FIG. 1, and is simplified as shown in FIG. 3. Here, the same reference numerals in FIG. 1 and FIG. 3 indicate components having the same function.

（発明の効果） 以上述べた如く、本発明によれば、１／２サンプル値間
引き信号処理と２チャンネル多重処理とが効率的に一体
化され回路構成の簡易化が図れる。(Effects of the Invention) As described above, according to the present invention, 1/2 sample value thinning signal processing and 2-channel multiplexing processing are efficiently integrated, and the circuit configuration can be simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるサンプル値間引きディジタルフィ
ルターの具体的実施例を示す構成図、第２図は本発明の
詳細な説明するためのフロ・ｙり図、第３図は第１図の
構成図において特に係数対称性が存する場合の簡略構成
法を示したフロ・ンク図である。 図において、１０７，１０８・・・・・・セレクター、
１１０，１１１゜１１２．１２０，１２１，１２２・・
−・乗算器、１３０，１３１．ｉ　３２゜１３３．１３
４・・・・・・レジスター、１４１Ｊ４２，１４３Ｊ４
４，１４５・・・・・・加算器、１５０・・−・・多重
分離回路である。 闇人弁理士内原　晋FIG. 1 is a block diagram showing a specific embodiment of the sample value thinning digital filter according to the present invention, FIG. 2 is a flow diagram for explaining the present invention in detail, and FIG. 3 is the configuration of FIG. 1. FIG. 3 is a front diagram showing a simplified construction method especially when there is coefficient symmetry in the diagram. In the figure, 107, 108... selector,
110,111゜112.120,121,122...
- Multiplier, 130, 131. i 32°133.13
4...Register, 141J42, 143J4
4,145... Adder, 150... Demultiplexing circuit. Dark Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] クロック周波数１／Ｔにて動作する有限インパルス応答
形ディジタルフィルタを２個のサブフィルタに並列分解
したディジタルフィルタであって標本化周波数１／Ｔの
第１の離散信号系列と標本化周波数１／Ｔの第２の離散
信号系列とを入力としＴ秒毎に該第１の離散信号系列と
該第２の離散信号系列とを交互に選択する第１のセレク
ターと該第１のセレクターとは相補的な動作にて前記第
２の離散信号系列と前記第１の離散信号系列とを交互に
選択する第２のセレクターと、該第１のセレクターの出
力として得られる第３の離散信号系列が供給されクロッ
ク速度１／Ｔにて動作する第１のサブフィルタと、前記
第２のセレクターの出力として得られる第４の離散信号
系列が供給されクロック速度１／Ｔにて動作する第２の
サブフィルタと、切替速度１／Ｔにて動作する多重分離
回路とより成り、特に前記第１のサブフィルタおよび前
記第２のサブフィルタが共に転置形の構成となっており
各々のレジスタ部が共通化されその出力が前記多重分離
回路に供給されていることを特徴とするサンプル値間引
きディジタルフィルター。A digital filter in which a finite impulse response type digital filter operating at a clock frequency of 1/T is decomposed in parallel into two sub-filters, the first discrete signal sequence having a sampling frequency of 1/T and the sampling frequency of 1/T. The first selector is complementary to a first selector that receives a second discrete signal sequence as input and alternately selects the first discrete signal sequence and the second discrete signal sequence every T seconds. a second selector that alternately selects the second discrete signal sequence and the first discrete signal sequence in an operation; and a third discrete signal sequence obtained as an output of the first selector. a first sub-filter that operates at a clock speed of 1/T; and a second sub-filter that is supplied with a fourth discrete signal sequence obtained as the output of the second selector and operates at a clock speed of 1/T. , and a demultiplexing circuit that operates at a switching speed of 1/T. In particular, both the first sub-filter and the second sub-filter have a transposed configuration, and each register section is shared. A sample value decimation digital filter characterized in that an output is supplied to the demultiplexing circuit.
JP59235409A 1984-11-08 1984-11-08 Sample value thinning-out digital filter Pending JPS61113314A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59235409A JPS61113314A (en) 1984-11-08 1984-11-08 Sample value thinning-out digital filter
US06/795,147 US4893265A (en) 1984-11-08 1985-11-05 Rate conversion digital filter
DE8585114190T DE3578868D1 (en) 1984-11-08 1985-11-07 DIGITAL FILTER TO CHANGE THE SCAN FREQUENCY.
EP85114190A EP0180989B1 (en) 1984-11-08 1985-11-07 Rate conversion digital filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59235409A JPS61113314A (en) 1984-11-08 1984-11-08 Sample value thinning-out digital filter

Publications (1)

Publication Number Publication Date
JPS61113314A true JPS61113314A (en) 1986-05-31

Family

ID=16985663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59235409A Pending JPS61113314A (en) 1984-11-08 1984-11-08 Sample value thinning-out digital filter

Country Status (4)

Country Link
US (1) US4893265A (en)
EP (1) EP0180989B1 (en)
JP (1) JPS61113314A (en)
DE (1) DE3578868D1 (en)

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JPH02171016A (en) * 1988-12-23 1990-07-02 Nec Corp Acyclic type interpolation filter

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US5548542A (en) * 1992-08-14 1996-08-20 Harris Corporation Half-band filter and method
US5515402A (en) * 1992-08-14 1996-05-07 Harris Corporation Quadrature filter with real conversion
US5339263A (en) * 1993-01-28 1994-08-16 Rockwell International Corporation Combined decimation/interpolation filter for ADC and DAC
US5367476A (en) * 1993-03-16 1994-11-22 Dsc Communications Corporation Finite impulse response digital filter
US5381357A (en) * 1993-05-28 1995-01-10 Grumman Corporation Complex adaptive fir filter
DE19742599B4 (en) 1997-09-26 2006-06-14 Micronas Gmbh Filter for time multiplex filtering of multiple data sequences and operating methods therefor
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JPH02171016A (en) * 1988-12-23 1990-07-02 Nec Corp Acyclic type interpolation filter

Also Published As

Publication number Publication date
EP0180989A3 (en) 1986-11-26
DE3578868D1 (en) 1990-08-30
EP0180989B1 (en) 1990-07-25
US4893265A (en) 1990-01-09
EP0180989A2 (en) 1986-05-14

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