JP5557339B2 - Decimation filter and decimation processing method - Google Patents

Description

The present invention relates to a decimation process when an input signal sampled at a certain frequency is converted to a lower frequency, and in particular, to perform a decimation process with a different decimation ratio 1/2 ⁿ for each carrier on a multicarrier signal. About.

  In the field of digital high-speed wireless communication systems in recent years, improvement in frequency band utilization rate and higher data communication rate are required. In order to meet this demand, highly efficient multiplexing is widely used. In these multiplexing systems, a signal transmitting / receiving unit performs a process of multiplexing a plurality of carrier signals.

  In this multiplexing process, a signal sampled at a predetermined sampling frequency may be converted into a signal sampled at a different sampling frequency.

  This frequency conversion process is generally called sampling frequency conversion or sampling frequency conversion.

  In this regard, when converting an input signal into a signal having a lower sampling frequency, down sampling is performed by thinning out the input signal. However, if the down-sampled signal contains a frequency component higher than half the sampling frequency (Nyquist frequency), aliasing distortion (aliasing component) occurs.

  Therefore, generally, before performing the above-described thinning-out, a predetermined filtering process is performed to limit the signal frequency band to the Nyquist frequency or lower. A filter used in this filtering process is called a decimation filter or a thinning filter.

  An example of such a decimation filter is described in Patent Document 1. The technique described in Patent Document 1 describes a configuration in which a plurality of decimation filters equal to the number of channels are provided when signals are multiplexed. In the technique described in Patent Document 1, decimation processing is realized by switching and inputting a sequence of input samples to the plurality of decimation filters.

Japanese National Patent Publication No. 8-502868

  As described above, by using the technique described in Patent Document 1, it is possible to perform decimation processing even on input signals of a plurality of carriers.

  However, these general techniques have had certain problems. That is a problem that when decimation is performed as multiple processing of a plurality of carrier signals, a decimation filter is required for the number of carriers. That is, the general technique has a problem that the circuit scale increases.

  Accordingly, an object of the present invention is to provide a decimation filter and a decimation processing method capable of performing decimation processing on a plurality of carrier signals with one decimation filter circuit and suppressing an increase in circuit scale.

According to the first aspect of the present invention, in a decimation filter that performs a decimation process with a decimation ratio 1/2 ⁿ (n is a natural number that differs for each carrier) for each carrier that is a multiplexed carrier signal. Is received as a time-division multiplexed carrier signal having the same sampling frequency, a shift register that outputs the carrier signal after delay adjustment, and a filter coefficient used for the decimation processing are stored, and the filter coefficient is sequentially output. The coefficient memory, the carrier signal output from the shift register, and the filter coefficient output from the coefficient memory are multiplied, and the multiplication result is output, and the output of the multiplier is integrated for each carrier signal. , an accumulator for outputting the integration result, the arithmetic unit having With few, the number of the carrier m, if the minimum decimation ratio 1/2 ⁱ and maximum decimation ratio was ^1/2 k (m, i and k are natural numbers respectively), the number of the arithmetic unit ^{2 ( k−i), the} number of shift registers included in each of the arithmetic devices is m × 2 ⁱ , and the number of filter coefficients stored in the coefficient memory included in each of the arithmetic devices is m × 1/2. a ^k number fraction, to each of the computing device, the coefficient of each carrier is assigned ^the 2 ⁿ min each coefficient of said assigned carriers is set for each carrier to each of the coefficient memories, a plurality of the arithmetic unit decimation filter and performing the decimation processing for each carrier in the set is provided.

According to the second aspect of the present invention, the decimation filter performs decimation processing on a multiplexed carrier signal and performs decimation processing with a decimation ratio of 1/2 ⁿ (n is a natural number different for each carrier) for each carrier. In the processing method, a step of receiving a plurality of carrier signals as time-division multiplexed carrier signals having the same sampling frequency, delay-adjusting the carrier signals and outputting them, storing filter coefficients used for the decimation processing, and storing the filter coefficients Sequentially multiplying the output carrier signal by the output filter coefficient and outputting the multiplication result, integrating the output in the multiplication step for each carrier signal, and integrating the result before an arithmetic unit and a step of outputting Decimation filter has a plurality, a number of carriers m, if the minimum decimation ratio 1/2 ⁱ and maximum decimation ratio was ^1/2 k (m, i and k are natural numbers respectively),
The number of arithmetic units is 2 ^{(k−i), the} number of shift registers included in each arithmetic unit is m × 2 ⁱ , and the filter coefficients of the coefficient memory included in each arithmetic unit are stored. The number is m × 1 / ^2k , and each of the arithmetic devices is assigned ²ⁿ coefficients for each carrier , and the assigned carrier coefficient is assigned to each coefficient memory for each carrier. It is set, decimation processing method and performing the decimation processing for each carrier by a plurality of said arithmetic unit to set is provided.

  According to the present invention, when performing decimation processing of a plurality of carrier signals, a filter coefficient corresponding to the decimation ratio of each carrier signal is prepared, and signal processing is performed in a time division manner by the multiplication device. The decimation filter circuit can perform decimation processing on a plurality of carrier signals to suppress an increase in circuit scale.

It is a block diagram showing the basic composition of the embodiment of the present invention. It is a flowchart showing the basic operation | movement of embodiment of this invention. It is a conceptual diagram showing the input / output of the serial-parallel converter in embodiment of this invention. It is a block diagram showing the basic composition of the example of the present invention. It is a figure which shows the storage method of the coefficient memory in the arithmetic unit in the Example of this invention. It is a time chart of the input / output of the arithmetic unit multiplier in the light embodiment of this invention. It is a time chart from the accumulator output in the arithmetic unit in an Example of this invention to an adder. It is a time chart figure of the format converter in the Example of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a basic configuration of an embodiment of the present invention.

  Referring to FIG. 1, a decimation filter 100 according to an embodiment of the present invention includes a parallel-serial converter 10, an arithmetic device 20, an adder 30, and a format converter 40.

  In addition, the arithmetic unit 20 includes a shift register 21, a coefficient memory 22, a multiplier 23, and an accumulator 26. The accumulator 26 further includes an adder 24 and a memory buffer 25. The functions of these parts will be described first. In addition, the operation of this embodiment will be described with reference to the flowchart of FIG.

  The parallel-serial converter 10 time-division multiplexes a plurality of carrier signals at the same sampling frequency, and outputs them as one signal to the shift register 21 (step S101). One time-division multiplexed signal is appropriately referred to as a “multiple carrier signal” in the following description. Note that the number of carrier signals input to the parallel-serial converter 10 is not particularly limited, and any number of carrier signals can be input. In FIG. 1, S1, S2, and Sm (m is a natural number) are illustrated as carrier signals.

  Similarly, there is a preferable number as the number of the arithmetic devices 20, but there is no limit on the upper limit of the number, and any number of arithmetic devices 20 can be prepared. In the figure, as the arithmetic device 20, an arithmetic device 20-1, an arithmetic device 20-2, and an arithmetic device 20-k (k is a natural number) are illustrated.

  The shift register 21 adjusts the delay of the multicarrier signal input from the parallel-serial converter 10 so as to correlate with the filter coefficient multiplied by the multiplier 23 and outputs the signal to the multiplier 23 (step S102). Here, the number of shift registers is determined according to the number of carrier signals and the minimum decimation ratio in the carrier signals.

  In the coefficient memory 22, filter coefficients corresponding to the number of carriers and the maximum decimation ratio in the carrier signal are prepared and stored. Then, the coefficient memory 22 sequentially outputs the filter count stored therein to the multiplier 23 (step S103).

  The multiplier 23 multiplies the carrier signal input from the shift register 21 and the filter coefficient sequentially output from the coefficient memory 22. The multiplied carrier signal is output to the accumulator 26 as the output of the multiplier 23 (step S104).

  The accumulator 26 performs integration for each input carrier signal using the adder 24 and the memory buffer 25 (step S105). This integration is performed for the number of times that matches the minimum decimation ratio that minimizes the number of integration (No in step S106).

  When the integration is performed for the number of times corresponding to the minimum decimation ratio that minimizes the number of integration (Yes in step S106), the result is output to the adder 30 in order for each carrier signal (step S107). Thereafter, the output carrier signal memory is cleared, and the next integration is resumed.

  The adder 30 adds all the output results of all the arithmetic devices 20 for each carrier signal, and outputs the result to the format converter 40 (step S108).

  The format converter 40 converts the carrier signal input from the adder 30 into a signal format suitable for the subsequent apparatus and outputs the signal format (step S109).

  Next, processing in each unit in this embodiment will be described in detail with reference to the drawings.

  FIG. 3 shows the operation of the parallel-serial converter 10 that outputs a plurality of carrier signals as one multiplexed signal having the same sampling frequency.

When the number of carrier signals to be subjected to decimation processing is m, a plurality of carrier signals S _{1 to} S _m having a sampling frequency f are input to the parallel-serial converter 10 and time division multiplexing is performed in the order of S _{1 to} S _m. It is output as a processed serial signal of sampling frequency f.

  Next, the decimation processing operation will be described using mathematical expressions.

The signal processing of the decimation filter configured with the number of taps h and performing de-sampling with a decimation ratio of ½ ⁿ (n is a natural number) is D1, D2,... Dh and then, the filter coefficients _{C 1,} C 2, When · · · _{C h,} the output signal _Z 0 of the sampling frequency _{^{fs / 2 n, Z 1,}} ··· can be expressed by the following equation (1).

Z _n = D _{1 + 2 ^ n} * C ₁ + D _{2 + 2 ^ n} * C ₂ + D _{3 + 2n} * C ₃ + D _{4 + 2 ^ n} * C ₄ + D _{5 + 2 ^ n} * C ₅ + ... + D _{h-1 + 2 ^ n} * C _h-1 + D _{h + 2 ^ n} * C _h
. . . Formula (1)

When a decimation process for down-sampling a carrier signal with a sampling frequency fs with a decimation ratio of 1/2 ⁿ is performed, a signal with a sampling frequency fs / 2 ⁿ is output, and therefore the decimation filter is 1 / (fs / 2 ⁿ ). One decimation process will be completed within the time indicated by. For this reason, the input signal of the decimation filter is shifted by ²ⁿ each time one process is completed.

  For example, output signals Z0, Z1, Z2,... In the case of a decimation filter with a decimation ratio of 1/2 are obtained from the equation (1). In this case, it is as follows. From this, it can be seen that each time one process is completed and the output signal Zn is output, the input signal is shifted by two.

Z ₀ = D ₁ * C ₁ + D ₂ * C ₂ + D ₃ * C ₃ + D ₄ * C ₄ + D ₅ * C ₅ + D ₆ * C ₆ + ... + D _h-1 * C _{h -1} + D _h * C _h
Z ₁ = D ₃ * C ₁ + D ₄ * C ₂ + D ₅ * C ₃ + D ₆ * C ₄ + D ₇ * C ₅ + D ₈ * C ₆ + ... + D _{h + 1} * C _{h -1} + D _{h + 2} * C _h
Z ₂ = D ₅ * C ₁ + D ₆ * C ₂ + D ₇ * C ₃ + D ₈ * C ₄ + D ₉ * C ₅ + D ₁₀ * C ₅ + ... + D _{h + 3} * C _{h -1} + D _{h + 4} * C _h
...
Similarly, output signals Z0, Z1, Z2,... In the case of a decimation filter with a decimation ratio of 1/4 are obtained from the equation (1). In this case, it is as follows. From this, it can be seen that each time one process is completed and the output signal Zn is output, the input signals are shifted by four.

Z ₀ = D ₁ * C ₁ + D ₂ * C ₂ + D ₃ * C ₃ + D ₄ * C ₄ + D ₅ * C ₅ + D ₆ * C ₆ + ... + D _h-1 * C _{h -1} + D _h * C _h
Z ₁ = D ₅ * C ₁ + D ₆ * C ₂ + D ₇ * C ₃ + D ₈ * C ₄ + D ₉ * C ₅ + D ₁₀ * C ₆ + ... + D _{h + 3} * C _{h -1} + D _{h + 4} * C _h
Z ₂ = D ₉ * C ₁ + D ₁₀ * C ₂ + D ₁₁ * C ₃ + D ₁₂ * C ₄ + D ₁₃ * C ₅ + D ₁₄ * C ₅ + ... + D _{h + 7} * C _{h -1} + D _{h + 8} * C _h
...
As described above, in the case of a decimation filter with a decimation ratio of ½ ⁿ , every time processing is completed and the output signal Zn is output, the input signal is shifted by 2 ⁿ .

  In order to realize this processing, filter coefficients are set in the coefficient memory 22 in accordance with the number of carrier signals and the decimation ratio of each carrier, and decimation processing is performed using a plurality of arithmetic devices 20.

When decimation processing is performed to downsample a carrier signal having a sampling frequency fs to a decimation ratio of ½ ⁿ , 2 ⁿ carrier signals are multiplied by 2 ⁿ filter coefficients on a one-to-one basis from equation (1). To accumulate. Thereby, the decimation process can be performed by down-sampling the carrier signal having the sampling frequency fs to the sampling frequency fs / ²ⁿ . As a result, the decimation filter finishes one decimation process within the time of 1 / (fs / 2 ⁿ ). Therefore, each arithmetic unit 20 needs to finish one decimation process within this time. Therefore, one calculation unit 20, and the 2 ⁿ shift registers operating at the sampling frequency fs of the input signal has a 2 ⁿ pieces of filter coefficients, in the 2 ⁿ input signals the operating frequency fs and the filter coefficient multiplication Then, the result is integrated. As a result, the decimation process with a decimation ratio of 1/2 ⁿ is performed within a time of 1 / (fs / 2 ⁿ ).

  The decimation filter 100 according to the present embodiment multiplexes a plurality of carrier signals with different decimation ratios. However, since the sampling frequency of the multicarrier signals is the same, the time taken for one decimation process differs for each decimation ratio. On the other hand, since the number of shift registers in the arithmetic unit 20 is fixed regardless of the decimation ratio, only one decimation ratio can be decimated by a single arithmetic unit. . Therefore, the number of shift registers of one arithmetic unit 20 is set to a minimum decimation ratio that minimizes the time of one decimation process, and a plurality of arithmetic operations are performed for decimation processes with other decimation ratios larger than the minimum decimation ratio. The apparatus 20 is set as one set.

From the above, a multi-carrier signal with a sampling frequency fs and the number of carriers m has a minimum decimation ratio of 1/2 ⁿ , a maximum decimation ratio of 1/2 ^k , and any other decimation ratio of 1/2 ^l , (n, The configuration in which decimation processing is performed with different decimation ratios where l and k are natural numbers n <l <k) is as follows.

The number of registers included in the shift register of each arithmetic unit 20 is m × 2 ^{n in} order to match the number m of carriers to be processed and the minimum decimation ratio in which the single decimation processing time is shortest. On the other hand, since the decimation ratio 1/2 ^l is 1/2 ^l filter coefficients necessary for one decimation process, an m × 2 ^l shift register 21 is required, so 2 ^l / 2 ⁿ = 2 Decimation processing is performed with ^(l−n) arithmetic devices 20 as a set.

Since the decimation processing that maximizes the number of arithmetic devices in one set is the case ^where the maximum decimation ratio is 1/2 ^k , the number of filter coefficients stored in the coefficient memory 22 of each arithmetic device 20 is the maximum decimation ratio 1 /. 2 ^k is the product of the number of data 2 ^k and the number of carriers m for which one decimation process is performed in one set of the arithmetic unit 20, which is m × ^{½ k} . In addition, since the sampling frequency of the input signal of each carrier to be decimated is the same, the minimum decimation ratio 1/2 ^k is 2 ^{n (k−n)} times while the filter coefficient stored in the coefficient memory goes around once. The decimation process is performed once for the maximum decimation ratio 1/2 ^{k and} once for any other decimation ratio 1/2 ^{l (k−1)} times.

Each arithmetic unit 20, the coefficient of each carrier, the number of registers m × 2n shift register 21 in the arithmetic unit 20 assigned to ^the 2 ⁿ each correspond divided by the number of the carrier number m, for each carrier in the coefficient memory Set to Storing the number of the coefficient memory, because m × 2 ^k pieces of, 2 ^(k-n) times of decimation processing can be performed factor enters both the carrier.

However, 2 (k−n) times of coefficients are used only for the minimum decimation ratio in which the number of shift registers is combined so that one arithmetic unit 20 can perform decimation processing for one time (one data). . Other decimation ratios of 1/2 ^l can be performed only 2 ^(k-1) times of decimation processing within the same time, and coefficients other than this time are not used for decimation processing. Therefore, filter coefficients that are not used are replaced with “0”. Thereby, in the output of the accumulator 26 and the output of the adder 24 of the arithmetic unit 20, the arithmetic result not used for the decimation process becomes “0”, and an extra circuit becomes unnecessary.

  The coefficient memory is stored in accordance with the input order, data format, and decimation ratio of multiple carriers input to the arithmetic unit 20.

  When the filter coefficients stored in one arithmetic device 20 are determined, the number of necessary arithmetic devices 20 is determined according to the filter coefficients necessary for each decimation process, but the number of arithmetic devices 20 according to the maximum decimation ratio is increased. Is likely to be. In general, if the sampling frequency, the calculation speed, and the filter coefficient of the input signal are the same, the larger the decimation ratio, the larger the calculation device 20 is. However, the configuration in this embodiment does not change that. For this reason, there are cases where the arithmetic unit 20 having a smaller decimation ratio is larger than the filter coefficient. In this case, the filter coefficient is stored as “0” in the coefficient memory of the extra arithmetic unit.

Each carrier signal and the filter coefficient are multiplied by a multiplier 23 and input to an accumulator 26 in the arithmetic unit 20. The accumulator 26 uses the shift register 21 or the memory buffer 25 to perform cumulative calculation for each input carrier signal. Cumulative calculation needs to produce a result for each decimation process, so the time of one decimation process is the shortest, and the total decimation process is ²ⁿ times in accordance with the minimum decimation ratio of 1/2 ^n. Then, the integration result is output to the adder 24 in order for each carrier signal, and then the output memory for the carrier is cleared and the next cumulative calculation is resumed. The adder 30 fully adds the input output results of all the arithmetic devices 20 for each carrier signal. The signal resulting from the full addition is a carrier output that has been subjected to decimation processing. Each decimated carrier signal is input to the format converter 40. The format converter 40 converts the time-division multiplexed carrier signal into a number of bits and a signal format suitable for the subsequent apparatus and outputs the converted signal.

[Example]
Subsequently, FIG. 4 shows a configuration in the case of three-carrier multiplexing as a specific embodiment of the present invention.

  In FIG. 4, the same components as those in the embodiment shown in FIG. In this embodiment, three carriers, ie, a first carrier, a second carrier, and a third carrier are multiplexed. Here, the decimation ratio of each carrier is a decimation ratio of 1/2 for the first carrier, a decimation ratio of 1/4 for the second carrier, and a decimation ratio of 1/8 for the third carrier. Further, in the embodiment of the present application, since three carriers are multiplexed, the first buffer memory 28-1, the second carrier memory 28-2, and the third carrier memory 28-3 are illustrated in the memory buffer 25. . These carrier memories correspond to the respective carriers.

  In this embodiment, the number of registers in the shift register 21 of the arithmetic unit 20 is 3 × 2 = 6 from the number of carriers 3 and the minimum decimation ratio ½ with the shortest decimation processing time. Therefore, in FIG. 4, six registers 26 are shown in the shift register 21.

On the other hand, since 3 × 8 = 24 registers are required for the decimation process with the maximum decimation ratio of 1/8, the processing is performed with four arithmetic devices 20 having six registers as one set. Therefore, in FIG. 4, the arithmetic device 20 is changed to the arithmetic device 20-1, the arithmetic device 20-2,
Four arithmetic units 20-3 and 20-4 are shown.

  Further, the number of coefficients stored in the coefficient memory 22 of each arithmetic unit 20 is the product of the number of data 8 and the number of carriers 3 for which the maximum decimation ratio 1/8 is subjected to one decimation process in one set of arithmetic units 20. 24 pieces are prepared.

  First, the carrier signals of the first carrier, the second carrier, and the third carrier input to the serial / parallel converter 10 are the same sampling frequency in the order of the first carrier, the second carrier, and the third carrier. Is time-division multiplexed and output to the shift register 21.

  Here, the storage of the coefficient memory of the arithmetic unit 20 is shown in FIG.

  Since the first carrier has a decimation ratio of ½, two filter coefficients are used for two carrier signals in one data decimation process. Since the second carrier has a decimation ratio of ¼, four filter coefficients are similarly used. Since the third carrier has a decimation ratio of 1/8, eight filter coefficients are similarly used. Further, since the sampling frequency of the input signal of each carrier is the same, the decimation process is performed twice for the second carrier and once for the third carrier while the first carrier performs the decimation process four times. Is called.

  Based on this, the coefficient memory is stored as follows. Since the number of registers of the shift register 21 of one arithmetic unit 20 is 6, two filter coefficients per carrier are set in the coefficient memory in the order of carriers. As a result, the first carrier that uses two filter coefficients in one decimation process can perform the decimation process for one data with one arithmetic device. However, since the second carrier uses four filter coefficients in one decimation process, the decimation process for one data cannot be performed by one arithmetic device, and two data are combined as two arithmetic devices. Perform decimation processing. The same applies to the third carrier, and decimation processing for one data is performed as a set of four arithmetic devices. In addition, since the number of coefficient memories stored is 24, filter coefficients are repeated four times for each carrier. However, the coefficient for four times is used only for the first carrier having a minimum decimation ratio of ½ that combines the number of registers so that one decimation process can be performed by one arithmetic unit 20. Since the carrier other than the first carrier can perform only one decimation process for the decimation ratio 1/4 and the decimation ratio 1/8 for the decimation ratio 1/8 within the same time, the filter coefficient for each process cannot be performed. Is not used and is replaced with “0”.

  FIG. 6 shows an input / output time chart of the multiplier 23 of the four sets of the arithmetic unit 20. What is shown is 24 data for one cycle of the coefficient memory, and thereafter this is repeated while the data is shifted. The configuration is shown in FIG.

  Each arithmetic unit 20 includes carrier signals that are time-division multiplexed at the same sampling frequency in the order of the first carrier (C1D **), the second carrier (C2D **), and the third carrier (C3D **). Is entered. Since the shift register 21 of each arithmetic device is composed of six registers, there is a delay of six data between the arithmetic devices. This delay difference is a delay of 2 data × 3 carriers resulting from the fact that the arithmetic unit 20 is configured by one unit of decimation processing with a decimation ratio of 1/2, and the filter coefficient and the carrier set in the coefficient memory The correlation is consistent. As a result, the first carrier is four times with two data sets of processing times “1 and 4”, “7 and 10”, “13 and 16”, and “19 and 22”, and the second carrier is Decimation processing for two times of processing data “2 and 5” and “14 and 17” twice, and for the third carrier, two times of processing time “3 and 6” as a set Multiplier data is output. This coincides with the number of decimation processes performed with the filter coefficient stored in the coefficient memory of each carrier. Data other than this time is output as “0” because it is not used for the decimation process.

  Subsequently, FIG. 7 shows a time chart from the output of the accumulator 26 of the four sets of the arithmetic unit 20 to the addition by the adder 30, the format conversion by the format converter 40, and the output. The configuration is shown in FIG.

  The accumulator 26 of each arithmetic unit 20 stores the output data of the multiplier 23 in the memory for each carrier, and when the multiplication data of the next carrier is output from the multiplier 23, it adds the data stored in the memory. Then, the integration is performed by repeating the operation of storing in the memory again.

  When this is performed a predetermined number of times, the data is output to the adder 30, and at the same time, the memory buffer 25 is cleared and the next integration is performed.

  In this embodiment, since the arithmetic unit 20 has three carrier inputs and is configured in units of one decimation process with a decimation ratio of 1/2, the memory buffer 25 has a carrier for three carriers as described above. A memory 28 is prepared. In this embodiment, every time the output data of the multiplier 23 is accumulated twice, it is output to the adder 30 to clear the memory and perform the next addition. The accumulator 26 accumulates the two data sets output from the multiplier 23 of each carrier shown in FIG. 6 for each carrier, outputs the result to the adder 30, and clears the memory buffer 25. Perform the following integration. Each carrier outputs the integration result of 4 times to the adder 30 during 24 data that the coefficient memory makes one round, but the decimation process with a decimation ratio of 1/4 is performed twice, and the decimation process with a decimation ratio of 1/8 is performed. A significant value is output only once, otherwise “0” is output. This is because the filter coefficient is set to “0” for data that is not used for the decimation processing of each carrier, and the integration result is “0”. Thus, in this embodiment, unnecessary data can be processed without providing an extra circuit.

  Thereafter, the output added by the adder 30 becomes output data for which the decimation processing is completed. The output data added by the adder 30 is input to the format converter 40, and the number of bits and the signal format are formed according to the subsequent apparatus and output.

  7 and 8, serial / parallel conversion is performed, the carriers are separated, and the carriers are output in accordance with the third carrier having a decimation ratio of 1/8.

  Although the above-described embodiment is a preferred embodiment of the present invention, the scope of the present invention is not limited only to the above-described embodiment, and various modifications are made without departing from the gist of the present invention. Implementation in the form is possible.

In the embodiments and examples of the present invention described above, when decimation processing of a plurality of carrier signals is performed, an arbitrary 1/2 ⁿ decimation processing is performed for each carrier with respect to the plurality of carrier signals by one decimation filter circuit. There is an effect that it is possible to perform. Accordingly, the embodiments and examples of the invention have an effect that it is possible to suppress an increase in circuit scale.

  The reason is that a filter coefficient corresponding to the decimation ratio of each carrier signal is prepared and signal processing is performed in a time division manner by a multiplier.

  Next, the above-described embodiment of the present invention will be summarized.

  The embodiment of the present invention is a parallel-serial converter that outputs a plurality of carrier signals as a time-division multiplexed carrier signal having the same sampling frequency, an accumulator having a function of integrating a multiplier and a multiplier output for each carrier signal, and a decimation process. A coefficient memory for storing filter coefficients to be used, and a shift register for matching a filter coefficient multiplied by a multiplier with a correlation delay of a carrier signal are included. Also included are a plurality of arithmetic devices, an adder for adding the output results of all the arithmetic devices, and a format converter for converting the output of the adder into a signal format suitable for the subsequent device and outputting the signal format. The multiplexed carrier signal is input to the shift register, delayed in order to match the timing with the filter coefficient for each carrier multiplied by the multiplier, and output to the multiplier. The multiplier multiplies the carrier signal and the filter coefficient used for the decimation process for each carrier signal output from the coefficient memory, and accumulates the result for each carrier in the accumulator. The accumulator output results of all the arithmetic units are added by an adder and output as a format converter, and are converted into a signal format suitable for the subsequent apparatus and output.

  The above is the outline of the embodiment of the present invention.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary Note 1) In a decimation filter that performs decimation processing with a decimation ratio 1/2 ⁿ (n is a natural number that differs for each carrier) for each carrier that is a multiplexed carrier signal,
A shift register that accepts a plurality of carrier signals as time-division multiplexed carrier signals having the same sampling frequency, and outputs the carrier signals after delay adjustment;
A coefficient memory for storing filter coefficients used for the decimation processing and sequentially outputting the filter coefficients;
A multiplier that multiplies the carrier signal output from the shift register by the filter coefficient output from the coefficient memory and outputs the multiplication result;
An accumulator that integrates the output of the multiplier for each carrier signal and outputs an accumulation result;
A plurality of arithmetic units having
When the number of carriers is m, the minimum decimation ratio is 1/2 ^i, and the maximum decimation ratio is 1/2 ^k (m, i, and k are natural numbers, respectively)
The number of arithmetic units is 2 ^{(k−i), the} number of shift registers included in each arithmetic unit is m × 2 ⁱ , and the filter coefficients of the coefficient memory included in each arithmetic unit are stored. The number is m × 1 / ^2k , and each of the arithmetic devices is assigned ²ⁿ coefficients for each carrier , and the assigned carrier coefficient is assigned to each coefficient memory for each carrier. is set, decimation filter and performing the decimation processing for each carrier by a plurality of said arithmetic unit to set.

(Appendix 2) In the decimation filter described in Appendix 1,
A decimation filter, wherein a filter coefficient not used in decimation processing due to a difference in decimation ratio for each carrier signal is replaced with “0” .

(Supplementary Note 3) In the decimation filter according to Supplementary Note 1 or 2,
A decimation filter characterized in that all of the plurality of arithmetic devices perform the same processing operation at one frequency.

(Appendix 4 ) In the decimation filter according to any one of appendices 1 to 3 ,
A parallel-serial converter that receives a plurality of carrier signals and outputs the input plurality of carrier signals to the shift register as a time-division multiplexed carrier signal having the same sampling frequency;
An adder for adding the output results of the plurality of arithmetic units and outputting the addition results;
A format converter for converting the output of the adder into a predetermined signal format and outputting the conversion result;
A decimation filter further comprising:

(Supplementary Note 5 ) In a decimation processing method in which a decimation filter performs decimation processing on a multiplexed carrier signal and performs decimation processing with a decimation ratio of 1/2 ⁿ (n is a natural number different for each carrier) .
Receiving a plurality of carrier signals as time-division multiplex carrier signals having the same sampling frequency, outputting the carrier signals after delay adjustment; and
Storing filter coefficients used for the decimation processing, and sequentially outputting the filter coefficients;
A multiplication step of multiplying the output carrier signal by the output filter coefficient and outputting the multiplication result;
Integrating the output in the multiplication step for each carrier signal, and outputting the integration result;
The decimation filter includes a plurality of arithmetic devices having
When the number of carriers is m, the minimum decimation ratio is 1/2 ^i, and the maximum decimation ratio is 1/2 ^k (m, i, and k are natural numbers, respectively)
The number of arithmetic units is 2 ^{(k−i), the} number of shift registers included in each arithmetic unit is m × 2 ⁱ , and the filter coefficients of the coefficient memory included in each arithmetic unit are stored. The number is m × 1 / ^2k , and each of the arithmetic devices is assigned ²ⁿ coefficients for each carrier , and the assigned carrier coefficient is assigned to each coefficient memory for each carrier. the set, decimation processing method and performing the decimation processing for each carrier by a plurality of said arithmetic unit to set.

  The present invention is suitable as a decimation filter for all devices that perform sampling frequency conversion.

10 parallel-serial converters 20-1, 20-2, 20-3, 20-4, 20-k arithmetic unit 21 shift register 22 coefficient memory 23 multiplier 24 adder 25 memory buffer 26 accumulator 27 register 28-1 first Carrier memory 28-2 second carrier memory 28-3 third carrier memory 30 adder 40 format converter 100 decimation filter

Claims (5)

In a decimation filter that performs decimation processing with a decimation ratio of 1/2 ⁿ (n is a natural number that differs for each carrier) that is different for each carrier for a multiplexed carrier signal,
A shift register that accepts a plurality of carrier signals as time-division multiplexed carrier signals having the same sampling frequency, and outputs the carrier signals after delay adjustment;
A coefficient memory for storing filter coefficients used for the decimation processing and sequentially outputting the filter coefficients;
A multiplier that multiplies the carrier signal output from the shift register by the filter coefficient output from the coefficient memory and outputs the multiplication result;
An accumulator that integrates the output of the multiplier for each carrier signal and outputs an accumulation result;
A plurality of arithmetic units having
When the number of carriers is m, the minimum decimation ratio is 1/2 ^i, and the maximum decimation ratio is 1/2 ^k (m, i, and k are natural numbers, respectively)
The number of arithmetic units is 2 ^{(k−i), the} number of shift registers included in each arithmetic unit is m × 2 ⁱ , and the filter coefficients of the coefficient memory included in each arithmetic unit are stored. The number is m × 1 / ^2k , and each of the arithmetic devices is assigned ²ⁿ coefficients for each carrier , and the assigned carrier coefficient is assigned to each coefficient memory for each carrier. is set, decimation filter and performing the decimation processing for each carrier by a plurality of said arithmetic unit to set. The decimation filter according to claim 1.
A decimation filter, wherein a filter coefficient not used in decimation processing due to a difference in decimation ratio for each carrier signal is replaced with “0” . The decimation filter according to claim 1 or 2,
A decimation filter characterized in that all of the plurality of arithmetic devices perform the same processing operation at one frequency. The decimation filter according to any one of claims 1 to 3 ,
A parallel-serial converter that receives a plurality of carrier signals and outputs the input plurality of carrier signals to the shift register as a time-division multiplexed carrier signal having the same sampling frequency;
An adder for adding the output results of the plurality of arithmetic units and outputting the addition results;
A format converter for converting the output of the adder into a predetermined signal format and outputting the conversion result;
A decimation filter further comprising: In a decimation processing method in which a decimation filter performs decimation processing on a multiplexed carrier signal and has a decimation ratio of ½ ⁿ (n is a natural number different for each carrier) for each carrier .
Receiving a plurality of carrier signals as time-division multiplex carrier signals having the same sampling frequency, outputting the carrier signals after delay adjustment; and
Storing filter coefficients used for the decimation processing, and sequentially outputting the filter coefficients;
A multiplication step of multiplying the output carrier signal by the output filter coefficient and outputting the multiplication result;
Integrating the output in the multiplication step for each carrier signal, and outputting the integration result;
The decimation filter includes a plurality of arithmetic devices having
When the number of carriers is m, the minimum decimation ratio is 1/2 ^i, and the maximum decimation ratio is 1/2 ^k (m, i, and k are natural numbers, respectively)
The number of arithmetic units is 2 ^{(k−i), the} number of shift registers included in each arithmetic unit is m × 2 ⁱ , and the filter coefficients of the coefficient memory included in each arithmetic unit are stored. The number is m × 1 / ^2k , and each of the arithmetic devices is assigned ²ⁿ coefficients for each carrier , and the assigned carrier coefficient is assigned to each coefficient memory for each carrier. the set, decimation processing method and performing the decimation processing for each carrier by a plurality of said arithmetic unit to set.

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