JPS63314014A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To obtain a linear phase FIR type digital filter circuit for decimation capable of multiplying two data to be multiplied by the same coefficient after adding them, by providing a bidirectional shift register. CONSTITUTION:The shift register 11 provided with (n-1) stages outputs input data after delaying by (n-1) stages, and the shift register 12 provided with (n) stages outputs the input data after delaying by two stages, and a register 13 provided with one stage outputs an input after delaying by one stage. The bidirectional shift register 14 outputs plural inputted data in reverse sequence of inputting, and selectors 15a and 15b select and output one of two input data. In such a way, since the linear phase FIR type digital filter circuit for the decimation can multiply 17 the two data to be multiplied by the same coefficient after adding them in advance and the number of times of multiplication can be reduced to 1/2, it is possible to double the operating speed of a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an FIR type digital filter circuit that performs decimation of a digital filter.

Conventional technology When constructing a linear phase FIR type digital filter with center-symmetric coefficients of 2n taps, the same coefficients are multiplied by 2
If two pieces of data are added in advance and then multiplied, the number of multiplications can be halved to n times. A digital filter circuit to which this principle is applied will be explained with reference to FIG. 5 showing its configuration and FIG. 6 showing the data flow.

In FIG. 5, 11 is an (n-1) stage shift register, 12 is a 1-stage shift register, 13 is a 1-stage register, 15a, 1
5b is a selector, 16 is an adder, 17 is a multiplier, 18 is a coefficient memory, and 19 is an accumulator. shift register 11
．． The adder 16 adds two pieces of data that are multiplied by the same coefficient to the n pieces of data each output from the multiplier 12, and the multiplier 17 multiplies the data by a filter coefficient, and the n multiplication results are output from the multiplier. is configured to be cumulatively added by an accumulator 19, forming a 2n-tad linear phase FIR type digital filter circuit.

Regarding the circuit shown in FIG. 5, the data flow when n=8 is shown in FIG. Here, from the input, shift register 11.
Up to 12 outputs are shown. The numbers shown in FIG. 6 represent data, and the larger number is new data. (A)
Here, new data 16 is input to the shift register 11 by the selector 15a, and output 9 of the shift register 11 is input to the shift register 12 by the selector 15b. One clock later, these inputs are taken into shift registers 11.12, and at the same time, shift registers 11.12 are connected in a loop by selectors 15a and 15b. This situation is shown in (B). Thereafter, this loop is maintained for six clocks. The situation 7 clocks after (A) is shown in (C). (C
), the selector 15a is activated again as shown in (D).

15b switches to the same connection as in (A).

As is clear from the figure, the two pieces of data output from the shift registers 11 and 12 are centrally symmetrical in all eight ways from (A) to (C). Therefore, in the case of center-symmetric filter coefficients, these two data can be added and then multiplied by the filter coefficient, and the number of multiplications can be eight times (=n).

Now, when performing decimation on the output of a filter, if you use a digital filter that can take out the output at the same frequency as the input data, it is wasteful to calculate the unused output (, This poses a problem when high-speed operation of the circuit is required.Therefore, a digital filter for decimation that performs calculations in accordance with the cycle of output data has been conventionally used.Part 7 describes a digital filter circuit that realizes this principle. The configuration is shown in the figure, and the data flow is shown in FIG. 8, and will be explained.

In FIG. 7, 11 is an (n-1) stage shift register;
15a is a selector, 17 is a multiplier, 18 is a coefficient memory,
19 is an accumulator.

Here, the circuit shown in FIG. 7 multiplies n pieces of data output from the shift register 11 by a filter coefficient in a multiplier 17, and transfers the n pieces of multiplication results output from the multiplier to an accumulator 19. The configuration is such that cumulative addition is performed at n-tap FIR type digital filter circuit.

Regarding the circuit shown in FIG. 7, the data flow when n=8 is shown in FIG. Here, from the input to the output of the shift register 11 is shown. The numbers shown in Figure 8 represent the data,
The larger number is new data. In (A), new data 8 is input to the shift register 11 by the selector 15a. One clock later, this input is taken into the shift register 11, and at the same time, the selector 1
5a, the shift register 11 is connected in a loop. This situation is shown in (B). After that, this loop is maintained for two clocks and shifts as shown in (C) and (D). (One clock after (D), (E)
As shown in (A), the selector 15a again switches to the same connection as in (A), and new data 9 is transferred to shift register 1.
1 is input. After one more clock, this input is taken into the shift register 11, and the shift register 11 is connected in a loop. In this way, new data is repeatedly fetched every four clock cycles.

Here, looking at the outputs from (A) to (H), all 8 data (=n) from data 1 to data 8 are output, and if this is considered as one cycle, 2 data Only one filter output can be calculated for the input, and 2
:1 decimation filter circuit is realized.

Problems to be Solved by the Invention However, the configuration shown in FIG. 7 is a linear phase FIR type digital filter in which two data to be multiplied by the same coefficient can be calculated in advance and then multiplied, as shown in FIG. Furthermore, in the configuration shown in FIG. 5, there was a problem that the outputs of the shift registers 11 and 12 would not be center-symmetric if decimation as shown in FIG. 7 was performed.

The present invention solves the above-mentioned conventional problems, and provides a linear phase FIR type digital filter circuit for decimation, which can perform multiplication after adding in advance two data to be multiplied by the same coefficient. With the goal.

Means for Solving the Problems In order to achieve this object, the present invention includes a first register circuit that stores input data and outputs it in a predetermined order, and an output of the first register circuit as input. a bidirectional shift register, a second register circuit that stores data output from the bidirectional shift register and outputs it in a predetermined order, an adder that adds the outputs of the first and second register circuits, and a filter. It stores coefficients (coefficient memory), a multiplier that multiplies the output of the adder by the output of the coefficient memory, and an accumulator that cumulatively adds the outputs of the multiplier.

Operation With the configuration described above, the present invention is a linear phase FIR type digital filter for decimation.
It is possible to perform multiplication after adding two pieces of data in advance.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a digital filter circuit according to the present invention. In FIG. 1, 11 is an (n-1) stage shift register, which inputs input data (n-1) in synchronization with the clock.
-1) Output with stage delay. Reference numeral 12 denotes a nine-stage shift register, which delays input data by n stages in synchronization with the clock and outputs the delayed data. Reference numeral 13 denotes a one-stage register, which delays the input by one stage in synchronization with the clock and outputs the delayed result. Reference numeral 14 denotes a bidirectional shift register, which can output a plurality of input data in the reverse order of input.

15a and 15b are selectors, which select and output one data out of two input data. 16 is an adder, 17 is a multiplier, 18 is a coefficient memory, and 19 is an accumulator.

FIG. 2 shows one embodiment of the bidirectional shift register 14.

In FIG. 2, 21a to 21n are registers, which output and hold inputs in synchronization with a clock. 22a-2
2n and 22x are selectors, and one of the two input data
Select and output data.

Next, the operation shown in FIG. 2 will be explained. Selector 22a~
When 22n and 22x select the upper input data, the registers 21a to 21n are connected in order from top to bottom, and the output of the lowest register 2In is output. Here, if the selectors 22a to 22n and 22x are switched to select lower data when data equal to the number of registers is input, the input data will be connected in order from the bottom to the top. Output can be performed in the reverse order of input. In this way, data for each register is output in reverse order.

FIG. 3 shows the flow of data in the circuit of FIG. 1 when n=8. Here, from the input, shift register 11.
Up to 12 outputs are shown. Further, for ease of viewing, the shift registers 11 and 12 are shown vertically in half. Note that the bidirectional shift register 14 is excluded. The numbers shown in FIG. 3 represent data, and the larger number is new data. In (A), new data 17 is input to the shift register 11 by the selector 15a, and the output 1 of the bidirectional shift register 14 is input by the selector 15b.
1 is input to the shift register 12. One clock later, these inputs are taken into shift registers 11.12, and at the same time, shift registers 11.12 are connected in a loop by selectors 15a and 15b. This situation is shown in (B). After that, this loop is maintained for two clocks and shifts as shown in (C) and (D). (One clock after (D), (E)
As shown in (A), the selector 15a again switches to the same connection as in (A), new data 18 is input to the shift register 11, and the selector 15b inputs the output 10 of the bidirectional shift register 14 to the shift register 12. After one more clock, these inputs are taken into the shift register 11.12 as shown in (F), and the shift registers 11.12 are connected in a loop.

From then on, this loop is maintained for two clocks, (
G) and (H). In this way, new data is repeatedly fetched every four clock cycles. The situation one clock after (H) is shown in (I), and the situation four clocks later is shown in (J).

Here, if we pay attention to the input of the shift register 12, rl
l, 10.13.12...'', and 2
They are arranged in reverse order based on the data cycle. This data, for example '13J and '12J, is the output of the shift register 11 for (B) and (F) arranged in reverse order, so this data is taken into the bidirectional shift register 14 and the two data It is sufficient to output the data in reverse order in one cycle.

FIG. 4 shows the timing of the above operation. Fourth
In the figure, ■ is the clock of the shift register 11.12, ■ is the select signal that switches the selector, ■ is the clock of the bidirectional shift register 14, and ■ is the bidirectional shift register 14.
This is a shift direction signal for switching the selector 22. Note that ■ and ■ operate the registers at the rising edge.

Now, as is clear from FIG. 3, the two pieces of data output from the shift registers 11 and 12 are centrally symmetrical in all eight ways from (A) to (H). Therefore, in the case of center-symmetric filter coefficients, these two data can be added and then multiplied by the filter coefficient, and the number of multiplications can be eight times (=n).

Note that the shift register used in this embodiment can also be realized using a first-in first-out (F I FO) element. Furthermore, although a shift register and a selector are used as the register circuit, and a register and a selector are used as the bidirectional shift register, a random access memory may also be used. In short, it is sufficient if the shift operation as shown in FIG. 3 is performed.

Effects of the Invention As described above, the present invention is a linear phase FIR type digital filter for decimation.
It is possible to perform multiplication after adding two pieces of data in advance, and because the number of multiplications can be halved, the operating speed of the circuit can be halved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the digital filter circuit according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the bidirectional shift register of FIG. 1, and FIG. 3 is an embodiment of the digital filter circuit shown in FIG. 1. 4 is a timing chart showing the operation of the embodiment shown in FIG. 1, FIG. 5 is a block diagram showing a conventional digital filter circuit, and FIG. 6 is a flow chart showing the data flow in FIG. 5. FIG. 7 is a block diagram showing a conventional digital filter circuit, and FIG. 8 is a flow chart showing the data flow in FIG. 11...(n-1) stage shift register, 12.
...0 stage shift register, 13...1 stage register, 14...bidirectional shift register, 1
5a, 15b...Selector, 16...
Adder, 17... Multiplier, 18... Coefficient memory, 19 Old... Accumulator. Name of agent Patent attorney Toshio Nakao 1 person 11 = (n
-1-in, 1ζ-hi shift register register 12-=n-stage shift register 73-=1-stage shift register I4--scan shift register 15α-1 data selector 15b--1γ-data ℃ left- 1113 FIG. 1 17-Multiplier 18-Fold number memory t'? -Figure 2 21-1. Nsk 2? -11 data t rector i: Leftai fusaku 1 Fig. 3 Fig. 3 Fig. 3 Fig. 5 wE6 Fig. 7 Fig. 8

Claims (1)

[Claims] a first register circuit that stores input data and outputs it in a predetermined order; a bidirectional shift register that receives the output of the first register circuit; and a bidirectional shift register that stores data output from the bidirectional shift register. , a second register circuit that outputs outputs in a predetermined order, an adder that adds the outputs of the first and second register circuits, a coefficient memory that stores filter coefficients, and an output of the adder and the coefficients. a multiplier that multiplies the output of the memory; and an accumulator that cumulatively adds the output of the multiplier; the input of the first register circuit is used as an input, and the output of the accumulator is used as an output; A digital filter circuit characterized in that it performs thinning by outputting one piece of data for a plurality of data inputs.