JPH03145322A - Fir filter - Google Patents

Abstract

PURPOSE:To execute the high-speed arithmetic processing with a simple constitution using one coefficient ROM by performing the multistage operation with one coefficient data read from the coefficient ROM. CONSTITUTION:Coefficient data read out from a coefficient ROM 1 at the update rate of input data is inputted to one input terminal of a multiplier 3, and input data delayed by a delay circuit where (m-1)-number of delay elements 8 which have the same delay time as the update rate of input data and hold N(=n/m)-number of input data are connected in series is inputted to the other input terminal. Consequently, multistage operation is performed by one coefficient data read from the coefficient ROM 1. Thus, an FIR filter having the multistage constitution is obtained which performs the high-speed arithmetic processing with the simple constitution using one coefficient ROM 1.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an I"I R filter,
The details are related to high-speed data processing.

<Prior Art> FIG. 3 is a diagram showing an example of a conventional FIR filter. A plurality of m coefficient ROMs (four in this embodiment)
1 stores coefficient data of n taps so that predetermined delayed coefficient data is read out in accordance with the same address data outputted from the address counter 2.

The coefficient data stored in the coefficient ROM1 is read out to one input terminal of the corresponding multiplier 3.

Input data is applied to the other input terminal of these multipliers 3. The output data of the multipliers 3 is applied to one input terminal of the respective adders 4. 7Io
;The output data of the u-unit 4 is stored in the corresponding register 5. The output data of the register 5 is applied to the other input terminal of the adder 4 via the changeover switch 6 and also to the selector 7.

In such a configuration, the switching switch at each stage is switched until the operation of n taps is completed by the adder 41! I! The operation results of each tap are sequentially updated and stored in each register 5. When n-tap calculations are completed, they are connected to the selector 7 side, and the calculation results of each stage are transferred to the selector 7.
It will be output via.

FIG. 4 is a block diagram showing another example of a conventional FIR filter, in which parts equivalent to those in FIG. 3 are given the same reference numerals.

In FIG. 4, the coefficient ROM 1, the multiplier 3, and the adder 4 are used as only one system, and the register 5 that stores the output data of the adder 4 has a plurality of m stages (four stages in FIG. 4). There is.

In such a configuration, reading coefficient data from the coefficient ROM 1, multiplication in the multiplier 3 and addition operation in the adder 4 are performed by m times (
In FIG. 4, it is assumed that input data is updated to one term of DI, D2, . . . at a speed of 4@). On the other hand, the coefficient ROM1 has addresses a (start), b [=n/4), c (=2) when the manual data is Dl.
The coefficient data stored in df=3n/4) and df=3n/4) are sequentially read out to the multiplier 3, and the multiplied n results are sequentially stored in the four-stage register 5.

When the input data is updated to D2, the read addresses a to d of the coefficient RQ M 1 are each advanced by one address. Note that the changeover switch 6 is connected to the adder 4 side. That is, the input data D2 is stored in the four stages of registers 5.
The tmJL value of the multiplication 'A' of the coefficient data of the read address advanced by one address and the result of multiplying the previous input data D is sequentially stored. Below, f
Similar operations are performed until reaching the final address where W+1 is assigned to each of the on-sale addresses a to d of the thread count ROMI. And each read address a
The changeover switch 6 is connected to the output side at the time when ~d reaches its respective final address.

As a result, the final calculation results are sequentially output from the four stages of registers 5.

<Problems to be Solved by the Invention> However, although the configuration shown in FIG. 3 can perform high-speed calculation processing, m coefficient ROMs and calculation systems are required depending on the number of stages (m), resulting in problems in terms of mounting space and cost. There is a problem. Furthermore, the coefficient ROM must store coefficient data to which a delay time has been added in advance so that coefficient data delayed by a predetermined time is output for the same address data.4 On the other hand, the configuration shown in FIG. In this case, since there is only one coefficient ROM and arithmetic processing system, it is more advantageous in terms of implementation smoothness and cost than in Fig. 3, but the calculation speed is higher than that in Figure 3.
There is a limit to speeding up because it is limited by the access time of the OM, and there is a drawback that the calculation processing time increases as the number of stages increases.

The present invention has focused on these points, and its purpose is to tl'- a multistage FIR filter that performs high-speed calculation processing with a simple configuration using one coefficient RO''A. be.

Means for Solving the Problem> The first invention that achieves the above object is to
An FIR filter that performs stage calculations has a coefficient ROM in which n-tap coefficient data is stored and from which the coefficient data of each tap is sequentially read out according to the input data update rate, and a delay time equal to the input data update rate. , N(
= n/m) input data Wj or delay circuits connected in series, and one input terminal receives input data or output data of each delay element of this delay circuit, and the other a multiplier to which coefficient data read from the coefficient ROM is added to its input terminal; and an adder to which the output data of this multiplier is applied to one input terminal and its own output data via a register to the other input terminal. It is characterized by having m arithmetic units consisting of:

The second invention is an FIR filter that performs m-stage calculations with n taps, and includes a coefficient ROM in which coefficient data of n taps is stored and coefficient data of each tap is sequentially read out in accordance with a clock; It has a delay time equal to the update rate and N(
a delay circuit in which m-1 delay elements are connected in series to hold =n/m) input data; a signal selection means for selecting input data or output data of each delay element of the delay circuit; a multiplier to which the output data of the signal selection means is applied to one input terminal and the coefficient data read from the coefficient ROM is added to the other input terminal; and the output data of this multiplier is applied to one input terminal. an adder; and an m-stage register that sequentially stores the output data of the adder in synchronization with the data selection of the signal selection means and adds the output data of the final stage to the other input terminal of the adder. It is characterized by being composed of 1 to .

In both inventions, coefficient data read out from the coefficient ROM at the update rate of the input data is input to one input terminal of the multiplier, and the delay time equal to the update rate of the input data is input to the other input terminal of the multiplier. Input data delayed by a delay circuit in which m-1 delay elements holding N (=n/m) pieces of input data are connected in series is input.

As a result, multi-stage calculations can be performed by reading the coefficient getter once from the coefficient ROM, and high-speed calculations can be realized with one coefficient ROM.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention, and parts equivalent to those in FIG. 3 are given the same reference numerals. In the figure, 8 is a delay element that delays input data, has a delay time equal to the update rate of input data, and N (=
In this embodiment, an example is shown in which three delay elements 8 are connected in series. As such a delay element 8, a shift register is used, for example. Coefficient data read from a common coefficient ROMI is applied to one input terminal of each multiplier 3,
Input data or output data of each delay element 8 is applied to the other input terminal. Reference numeral 9 denotes a register into which data stored in the register 5 is stored via a changeover switch 6, and its output data is applied to a selector 7.

In such a configuration, for example, the number of taps n is 192,
If the number of calculation stages m is 4, then 48 pieces of input data will be stored in the delay element 8 of each stage.For example, if the t-th input data is input to the delay element of the first stage, The t-th input data is added to the first-stage multiplier, and the t-th input data is added to the second-stage multiplier.
(-48) input data in front of the gate is added, 2·N (=96) input data in front of the t-th input data is added to the third-stage multiplier, and the input data in front of the fourth stage is added to the multiplier in the fourth stage. In addition to the t-th input data, 3·N(-144) input data will be added.

On the other hand, the vertical address counter 2 for reading coefficient data from the coefficient ROM 1 is incremented by l-in synchronization with the input data update X11.

As a result, if the address of the 1-thread number ROMI at the time when the t-th input data is input to the first-stage multiplier is 0, then the address of I+ when the t-th input data is input to the second-stage multiplier is 0. vl, the address of ROM 1 becomes N,
The third step! : The address of coefficient ROM1 at the time when the t-th manual data is inputted is 2·N, and t
The address of the coefficient P-OMl at the time when the t-th human input data is input to the first stage multiplier 314 is 3·N,
Substantially the same calculation result as when changing the 7° address of the coefficient ROMI can be obtained. When the calculation result is stored in the register 5, the switch switch 1 is connected to the register 9 side, and the calculation result stored in the register 5 is transferred and stored in the register 9. After the calculation result is transferred and stored in the register 9, the changeover switch 6 is connected to the adder 4 side again.

With this configuration, only one coefficient ROM is required, which saves mounting space and reduces component cost.
~ can be lowered. Since the arithmetic processing is executed in parallel in the n1 series, high-speed arithmetic operations similar to those shown in FIG. 3 can be obtained.

FIG. 2 is a block diagram (not shown) of an embodiment of the second invention, and the input data of each delay element 8 is shown in FIG. Alternatively, the output data is applied to one input terminal of the multiplier 3 via the selector 10 used as signal selection means. The coefficient data read from the coefficient ROM 1 to the input terminal of the multiplier 3 is updated while performing m operations 35-tt on the input data or output data of each delay element 8 at a certain point in time. It is maintained without any problems. Note that the arithmetic processing after the multiplier 3 is the same as that shown in FIG. 1, and the explanation thereof will be omitted.

According to such a configuration, the coefficient R is smaller than that in the configuration shown in FIG.
Access time conditions for OM1 can be relaxed. That is, in FIG. 4, when the number of calculation stages is m, the coefficient ROM
The access time of 1 must be 1/m times the update cycle of input data, and as the number of calculation stages increases, it becomes necessary to have something that can be accessed at high speed. However,
According to the configuration shown in FIG.
A cheaper ROM can be used than in the case of 1A.

<Effects of the Invention> As explained above, according to the present invention, one coefficient RO
A multi-stage F'IR filter that performs high-speed arithmetic processing can be realized with a simple configuration using M.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the first invention;
FIG. 3 is a block diagram showing an embodiment of the second invention, FIG. 3 is a block diagram showing an example of a conventional device, and FIG. 4 is a Florafre 1 showing another example of the conventional device. 1...Coefficient ROM, 2...Address counter, 3.
... Multiplier, 4 ... Adder, 5 ... Register, 6.
...Switching diagram 2

Claims (2)

[Claims] (1) In an FIR filter that performs m-stage calculations with n taps, there is a coefficient ROM in which coefficient data of n taps is stored and coefficient data of each tap is sequentially read out according to the input data update rate, and input data update. with a delay time equal to the rate and N(
A delay circuit has m-1 delay elements connected in series and holds input data of =n/m), and input data or output data of each delay element of this delay circuit is applied to one input terminal, and the other a multiplier to which coefficient data read from the coefficient ROM is added to the input terminal of the multiplier; and an adder to which the output data of this multiplier is added to one input terminal and its own output data is added via a register to the other input terminal. An FIR filter comprising: m arithmetic units each consisting of an FIR filter. (2) In an FIR filter that performs m-stage calculations with n taps, there is a coefficient ROM in which n tap coefficient data is stored and the coefficient data of each tap is sequentially read out in response to a clock, and a delay equal to the input data update rate. time, N(
a delay circuit in which m-1 delay elements are connected in series and hold =n/m) input data; a signal selection means for selecting input data or output data of each delay element of the delay circuit; a multiplier to which the output data of the signal selection means is applied to the input terminal of the multiplier, and the coefficient data read from the coefficient ROM read from the coefficient ROM to the other input terminal of the multiplier; and an adder to which the output data of the multiplier is applied to one input terminal of the multiplier. and,
an arithmetic unit consisting of an m-stage register that sequentially stores the output data of this adder in synchronization with the data selection of the signal selection means and adds the output data of the final stage to the other input terminal of the adder; An FIR filter characterized by: