JPH07273600A - Digital filter - Google Patents

Abstract

PURPOSE:To reduce a coefficient revision time considerably without increase in the scale by providing a data generator comprising an adder, a delay circuit and a coefficient register to each tap in the digital filter employing a RAM for the multiplication. CONSTITUTION:Data generators 10a to 10d or the like of the same configuration are provided to taps of the digital filter and data information from an input terminal 1 and coefficient information from the generators 10a to 10d are multiplied by corresponding RAMs 5a to 5d and filtered information is outputted from an output terminal 3. A coefficient signal from a coefficient data input terminal 2 is stored in a register 11 based on a control signal from control input terminals 4A, 4B and accumulated by a delay circuit 14 and an adder circuit 15 to provide an output of the coefficient information and the coefficient is revised in parallel in each tap thereby reducing the coefficient calculation time considerably. As a result, the processing time is 896 clocks (=265+64) in the case of an 8-bit input for 640 tap provision, and then the small sized and high speed filter is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for performing high speed operation, and more particularly, the multiplication among filter operations is RA.
The present invention relates to a digital filter that uses M (Ramdom Access Memory).

[0002]

2. Description of the Related Art Generally, (1) when a multiplier is used as a constituent element of a calculation portion of a digital filter, (2) a ROM (Read Only Memory)
y), and (3) RAM (Rando
When using m Access Memory), three types of components are known.

Comparing the characteristics of these three constituent elements by focusing on the operating speed of the digital filter and the chip area of the semiconductor chip formed on the semiconductor chip, the operating speed of each constituent element is From the aspect, it is possible to realize almost the same performance, but the occupied area of the digital filter on the semiconductor chip is the largest in the ROM configuration, then in the multiplier configuration, and in the RAM configuration order.

For example, if a (8.times.8) multiplier is constructed by ROM, all multiplication results must be written and stored, so that 2 16 = 65536 bit word data is required and output is 16 bits. Therefore, multiply by 16 to obtain 65536 + 16 = 1084576 bits and about 1M.
Bit memory is needed.

When a RAM is used instead of a ROM, the output is the same 1 bit, but since the content data can be rewritten according to the coefficient, only 8 inputs are needed and 8 of 2
Power = 256 words, which is multiplied by 16 and 256 x 16 = 4096
Just a bit. The integration degree of the ROM is generally four times or more that of the RAM, but it is clear that the ROM is much larger than the RAM because the number of bits is 256 times.

Further, a digital filter using a multiplier can be realized in a relatively small area in the case of a simple parallel adder in which the adders are arranged on the matrix by the number of bits, but for the sake of speeding up. Requires the adoption of the Booth's algorithm, carry save adder, and pipeline operation, and the circuit becomes complicated, the number of elements increases, and the circuit area tends to increase.

FIR of 4 taps using 4 RAMs
Referring to FIG. 7, which shows an example of a concrete configuration example of a first conventional digital filter which constitutes a (finite impulse response) type filter, the first conventional digital circuit using this RAM is beforehand It is necessary to store the result of multiplying the input data by the coefficient (hereinafter abbreviated as coefficient calculation data) at the address corresponding to the input data.

When setting the coefficient calculation data, the first
In the conventional digital filter data selector 79, the coefficient calculation data input from the coefficient calculation data input 72 is converted into R according to the control signal input from the control signal input terminal 74.
One of the four RAMs of the AM75 is selected and supplied, and stored in correspondence with the address supplied from the address decoder 78.

Next, during the filter operation of the first digital filter, the address decoder 78 converts predetermined digital data input from the data input terminal 71 into an address and supplies it to the RAM 75 consisting of four RAMs. . The RAM 75 outputs the coefficient calculation data already stored corresponding to the input address, and the delay circuit (22
a to 22c), the adder (2
3a to 23c) to perform a filter operation by adding and output from the data output terminal 73.

With such a configuration, it is possible to provide a small-sized and high-speed digital filter in which the coefficient of the digital filter can be easily changed.

However, although the first conventional digital filter can form a high-speed digital filter having a small circuit area by using the RAM as described above, a large amount of data is stored before the filter operation. Since it needs to be stored in the RAM, there is a drawback that it takes time to change the coefficient.

For example, when each of the coefficient and the input of the above-mentioned digital filter is 8 bits and the output is 16 bits, 4096 bits of coefficient operation data are required for one tap, and 16384 bits of data are required for 4 taps. Become. This is a system that requires a large number of taps, such as a ghost reducer system,
A filter of up to 640 taps is needed, in this case 4
In a system that requires a huge amount of data of 096 bits × 640 = 262,440 bits, this cannot be ignored.

Further, if all of this data is serially transferred, 262,440 clocks are required to change the coefficients, and even if 16-bit parallel transfer is performed, 163,840 clocks are required. Also, this transfer rate is very dependent on the performance of the external CPU.

A second conventional digital filter that has improved this drawback and shortened the data transfer time is disclosed in, for example, Japanese Patent Laid-Open No. 4-222111. This second
FIG. 8 shows the configuration of a digital filter of the related art.

The digital filter of the second conventional example constitutes a 4-tap FIR filter by using four RAMs similarly to the digital filter of the first conventional example shown in FIG.

The second conventional digital filter has a multiplier 93 which internally generates coefficient calculation data without externally loading the coefficient calculation data.

Next, the operation of the second conventional digital filter will be described with reference to FIG.

Referring to FIG. 8, first, the coefficient data input from the coefficient data input terminal 82 and stored in the register 91 is multiplied by the internal address generated by the counter 92 and the multiplier 9.
Multiplied by 3. The multiplication signal is stored in the RAM selected from the RAM 85 by the data selector 86 in accordance with the control signal input from the control signal terminal 84, corresponding to the internal address given via the address decoder 88.

The operation relating to the filter calculation will be described with reference to FIG.
The description is omitted because it is the same as the digital filter of the first conventional example shown in FIG.

As described above, since the coefficient calculation data is internally generated, the data load in the digital filter of the second conventional example is required only for the coefficient. Therefore, the number of tap bits is 8 bits × 4 taps = 32. It is a bit.

[0021]

However, this conventional digital filter requires 256 calculations to store the coefficient calculation data in each tap, and as a result,
4 taps require 32 + 256 × 4 = 1056 clocks. Furthermore, in the case of 640 taps, the coefficient loading is 640
Clock required, coefficient calculation 640 × 256 = 1638
A total of 164480 clocks of 40 clocks are required.

That is, although it is effective in reducing the dependence on the external CPU, there still remains a problem that it takes time to change the coefficient as a whole.

Therefore, an object of the present invention is to provide a digital filter which can reduce the time for changing the coefficient and can operate at high speed.

[0024]

Means for Solving the Problems A digital filter according to the present invention comprises storage means for storing a coefficient signal composed of a digital signal which is a coefficient of the digital filter at an internal address corresponding to an internal address signal corresponding to the coefficient signal. An internal address generating means for generating the internal address; and an address selecting means for selecting the internal address signal at the time of setting the coefficient signal and selecting an input signal at the time of the filter calculation and giving it to the storage means. In a digital filter performed using the digital signal stored in the storage means, data generation including coefficient signal holding means for receiving and holding the coefficient signal for each tap and cumulative addition means for sequentially cumulatively adding the coefficient signals Means for setting the coefficient signal by the cumulative addition means. Is configured to store a cumulative addition signal without an address corresponding to the internal address signal of said memory means.

Further, the taps of the digital filter of the present invention may be configured to receive a common signal of the coefficient signals.

Furthermore, the data generating means of the digital filter of the present invention controls the signal holding means for holding the coefficient signal by a first control signal and the output of the signal holding means by a second control signal. It is also possible to adopt a configuration that includes a delay unit configured to perform the above, and the cumulative addition unit that adds the output of the signal holding unit and the output of the delay unit.

Furthermore, the signal holding means of the digital filter of the present invention includes a register circuit controlled by the system clock of the first control signal, and the delay means is controlled by the second control signal of the register circuit. It is also possible to include a delay circuit that delays the output, and the cumulative addition means may include an adder.

Another digital filter of the present invention is a storage means for storing a coefficient signal composed of a digital signal which is a coefficient of the digital filter at an internal address corresponding to an internal address signal corresponding to the coefficient signal, and the internal means. An internal address generating means for generating an address and an address selecting means for selecting the internal address signal at the time of setting the coefficient signal and selecting an input signal at the time of the filter calculation and supplying the input signal to the storage means are provided. In a digital filter which uses the digital signal stored in, a data generating means including a coefficient signal holding means for receiving and holding the coefficient signal for each tap, and a cumulative addition means for sequentially cumulatively adding the coefficient signals, , A first controlled by the second control signal
And a second selecting means, wherein when the coefficient signal is set, the cumulative addition signal generated by the tracking addition means is stored in an address of the storage means corresponding to the internal address signal, and at the time of the filter calculation, the cumulative addition signal is stored. The data adder is configured to add the digital signals stored in the storage means.

Further, each of the taps of another digital filter of the present invention may be configured to receive a common signal of the coefficient signals.

Still further, the data adder of another digital filter of the present invention comprises a register controlled by a first control signal for holding the coefficient signal, and an output of the storage means or an output of the register as a second output. Of the control signal, a cascade input terminal supplied with an external signal, a second selector that selects the first selector and the external signal with the second control signal, and A configuration including a delay circuit that delays the output of the second selector, an adder that adds the output of the delay circuit and the output of the first selector, and a cascade output terminal that outputs the output of the adder to the outside. Can also be

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a digital filter of an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital filter according to a first embodiment of the present invention. The same components as those of the conventional digital filter shown in FIGS. 3 and 4 are designated by the same reference numerals.

Referring to FIG. 1, the digital filter according to the first embodiment of the present invention is provided with an input terminal 1 which receives an input signal composed of a digital signal and a coefficient data which is a coefficient of the digital filter. The input terminal (2a to 2d) for receiving the control signal, the control signal terminals 4A and 4B for receiving and supplying the control signal, and the coefficient data input from the input terminal 2 are held by the system clock input from the control signal terminal 4A. Control signal terminal 4
Four data generators (10a to 10a) that perform cumulative addition of coefficient data held by a control signal input to B as the address increases by one in synchronization with the system clock.
d), a counter 12 that generates an address that increments the address by 1 in synchronization with the system clock, and four RAMs (5a to 5d) that store the coefficient data cumulatively added by the data generators (10a to 10d). When the coefficient data is set, an arbitrary storage address of the RAM (5a to 5d) that receives the signal of the counter 12 and stores the coefficient signal data is generated, or the input signal is received during the filter calculation and the coefficient signal data is stored. An address decoder 8 for generating an arbitrary storage address of each RAM (5a-5d), a delay circuit (22a-22c) for delaying an output of each RAM (5a-5d) storing an input signal and coefficient data for a predetermined period,
An adder (23a) for adding the signals delayed by the delay circuits (22a to 22c) and the signals read from each of the RAM 5b, RAM 5c and RAM 5d.
23c) and an output terminal 3 which receives the output of the adder 23c.

Further, data generators (10a-10d)
Referring to FIG. 2 showing a specific configuration example of the first embodiment of the present invention,
The data generator 10 of the digital filter of the embodiment of
A coefficient register 11 for holding coefficient data input from the coefficient signal input terminal 2, a delay circuit 14 for delaying the coefficient data held in the coefficient register 11, an output signal of this delay circuit 14 and a coefficient by the next system clock. An adder 15 for accumulating the coefficient data held in the register 11,
The output terminal 17 outputs the output of the adder 15.

The digital filter of the first embodiment is designed to shorten the coefficient changing time by basically providing each tap with a data generator consisting of an adder and a delay circuit.

Next, the operation of the digital filter of this embodiment will be described.

Referring again to FIG. 1, when setting the coefficient data of the digital filter of the first embodiment of the present invention, the coefficient data input from the coefficient data input terminals (2a to 2d) is input from the control signal terminal 4A. It is stored in a coefficient register inside the data generator 10 according to the generated control signal.
The data generator (10a to 10d) for each tap of the digital filter of the first embodiment generates coefficient calculation data, and the coefficient calculation data is stored in the RAM (5a to 5d) according to the internal address generated by the counter 12. ).

Next, referring again to FIG. 2 showing a concrete configuration example of the data generator 10, the coefficient data input from the coefficient signal input terminal 2 of the data generator 10 is stored in the coefficient register 11 and In synchronism with the clock, as the address increases by one by the adder 15, they are cumulatively added and become coefficient calculation data.

For example, when the coefficient is 5 and the input is 1, the coefficient operation data is 5, and when the input is 2, the coefficient operation data is 10. Therefore, when the input x is increased by one. At the same time, the coefficient calculation data Kx corresponding to the input x can be obtained by adding a coefficient to the coefficient calculation data K (x-1) immediately before the input x. The coefficient calculation data thus obtained is synchronized with the counter 11 and corresponds to the address generated by the address decoder 8 in the RAM.
(5a to 5d) are sequentially stored.

The filter calculation of the digital filter of the first embodiment is the same as the filter calculation of the conventional digital filter, and therefore its detailed description will be omitted.

The digital filter of the first embodiment of the present invention requires the same number of clocks as the digital filter of the conventional example for generating coefficient data for each tap, but data operations can be performed in parallel. With 256 clocks, data can be loaded into all taps, dramatically increasing the speed.

Further, since the data generator 10 can be composed of an adder, a register and a delay circuit respectively, it is possible to suppress an increase in the scale of the circuit.

Next, a digital filter according to the second embodiment of the present invention will be described.

Referring to FIG. 3, in the digital filter of the second embodiment, instead of the four input terminals (2a to 2d) of the digital filter of the first embodiment, the coefficient data of the coefficient of the digital filter is stored. The data generators (20a to 20d) having one input terminal 2 for receiving the supply, and commonly connecting the input terminals 2 to input the coefficient data are the data generators of the digital filter of the first embodiment ( 10
The components are the same as those of the digital filter of the first embodiment except that they are replaced in place of a to 10d), and the same components are designated by the same reference numerals.

When setting the coefficient data of the digital filter of the second embodiment, first, the coefficient data Ka input from the input terminal 2 is held in the coefficient register 11a of the data generator 20a, and then the coefficient of the data generator 20b. The system clock is 4 clocks so that the coefficient data Kb is held in the register 11b, the coefficient data Kc is held in the coefficient register 11c of the data generator 20c, and finally the coefficient data Kd is held in the coefficient register 11d of the data generator 20d. It is possible to hold the coefficient data by operating the division.

The other operations are the same as the operations of the digital filter of the first embodiment, and detailed description thereof will be omitted.

In the digital filter of the second embodiment, four input terminals (2a to 2d) are reduced to one input terminal 2, and four connecting lines to the data generators (20a to 20d) are further connected. Since the number can be one, there is an effect that the configuration can be simplified.

Next, a digital filter according to the third embodiment of the present invention will be described.

Referring to FIG. 4, the digital filter of the third embodiment has an input terminal (2a) to which coefficient data, which is a digital filter coefficient, is supplied at the time of coefficient setting.
2d), coefficient data is input, and the coefficient data is cumulatively added by the control signals from the control signal terminals 4A and 4B, respectively.
d), and the RAM (5
a to 5d), the cumulative addition coefficient data stored in the RAM 5b and RAM 5 are delayed by a predetermined period.
The data adders (24a to 24d) for adding the signals read out from the respective c and the RAM 5d are replaced by the data generators (10a to 10d) of the digital filter of the first embodiment.
d) and the delay circuits (22a to 22c) and the adders (23a to 23c), respectively, except that the digital filter has the same configuration as that of the digital filter of the first embodiment and the same components are designated by the same reference numerals. Are shown in the figure.

Referring to FIG. 5, the data adder 24 of the digital filter of the third embodiment has the selectors 35 and 36, the RAM data input terminal 32, the cascade input terminal 31, and the cascade output of the data generator 10 shown in FIG. Each of the terminals 33 is added. By controlling each of the selectors 35 and 36 by the control signal input from the control signal terminal 4B, the adder 15
The digital filter of the first embodiment is provided by making it possible to select one of the input signals of the RAM data input and the coefficient register and the input signal of the delay circuit 14 between the cascade input and the adder output data. Data generator 10
And delay circuits (22a to 22d) and adder (23
a to 23d), the circuit can be reduced in size.

Next, the operation of the digital filter according to the third embodiment of the present invention will be described.

At the time of setting the coefficient, the coefficient data input from the coefficient data input terminal 2 is stored in the coefficient register according to the control signal input from the control signal terminal 4A, as in the digital filter of the first embodiment. The data adders (24a to 24d) perform cumulative addition of coefficients for each tap and store the addition signal in the RAMs (5a to 5d) according to the internal address generated by the counter 12.

In addition, RAM (5a-5
The data output from (d) is added to the data (24a to 24).
In d), the data is calculated and output from the data output terminal 3.

Next, a digital filter according to the fourth embodiment of the present invention will be described.

Referring to FIG. 6, in the digital filter of the fourth embodiment, coefficient data which is the coefficient of the digital filter is used instead of the four input terminals (2a to 2d) of the digital filter of the third embodiment. Of the third embodiment except that the input terminal 2 is commonly connected to the input terminal 2 and coefficient data is input to the data generators (24a to 24d). The same components as those of the filter are designated by the same reference numerals.

When setting the coefficient data of the digital filter of the fourth embodiment, first the coefficient data Ka input from the input terminal 2 is held in the coefficient register 11a of the data generator 24a, and then the coefficient of the data generator 24b. The system clock is 4 clocks so that the coefficient data Kb is held in the register 11b, the coefficient data Kc is held in the coefficient register 11c of the data generator 24c, and finally the coefficient data Kd is held in the coefficient register 11d of the data generator 24d. The coefficient data is held by operating for a minute.

The other operations are the same as the operations of the digital filter of the third embodiment, and detailed description thereof will be omitted.

In the digital filter of the fourth embodiment, four input terminals (2a to 2d) are reduced to one input terminal 2, and four connection lines to the data generators (24a to 24d) are connected. Since the number can be one, there is an effect that the configuration can be simplified in addition to the simplified configuration of the digital filter of the second embodiment.

[0059]

As described above, according to the present invention, multiplication is performed by R
Regarding a digital filter that uses AM (Ramdom Access Memory), each tap is equipped with a data generator consisting of an adder, a delay circuit, and a coefficient register to suppress the increase in circuit scale and dramatically reduce the coefficient change time. A digital filter that enables this can be realized.

In the case of the 4-tap filter, the time until the filter calculation becomes possible according to the present invention is about 1 / 4,640.
In the case of the tap filter, there is an effect that each can be shortened to about 1/180.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a data generator of the digital filter shown in FIG.

FIG. 3 is a block diagram showing a configuration of a digital filter according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a digital filter according to a third exemplary embodiment of the present invention.

5 is a block diagram showing a specific configuration of a data adder of the digital filter shown in FIG.

FIG. 6 is a block diagram showing a configuration of a digital filter according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a first conventional digital filter.

FIG. 8 is a block diagram showing a configuration of a second conventional digital filter.

[Explanation of symbols]

 1 data input terminal 2 coefficient data input 3 data output 4, 4A, 4B control signal input terminal 5 coefficient RAM 6, 9 data selector 7, 10 data generator 8, 78 address decoder 11 coefficient register 12 counter 13 multiplier 14, 22a to 22c Delay circuit 15, 23a to 23c Adder 17 Coefficient calculation data output terminal 18 Coefficient calculation data input terminal 24, 24a to 24d Data adder 31 Cascade input terminal 32 RAM data input terminal 33 Cascade output terminal 35, 36 Selector

Claims (7)

[Claims] 1. A storage unit for storing a coefficient signal composed of a digital signal which is a coefficient of a digital filter in an internal address corresponding to an internal address signal corresponding to the coefficient signal, and an internal address generation unit for generating the internal address. An address selecting means for selecting the internal address signal when setting the coefficient signal and selecting an input signal for applying filter operation to the storage means, and using the digital signal stored in the storage means for the filter operation. A digital filter including: coefficient signal holding means for receiving and holding the coefficient signal for each tap, and data generating means including cumulative addition means for sequentially cumulatively adding the coefficient signals, and when setting the coefficient signal, The cumulative addition signal generated by the cumulative addition means is stored in the internal address of the storage means. A digital filter characterized by being stored at an address corresponding to a dress signal. 2. The digital filter according to claim 1, wherein each tap receives a common signal of the coefficient signals. 3. The data generating means, the signal holding means for holding the coefficient signal by a first control signal, a delay means for controlling the output of the signal holding means by a second control signal, and 3. The digital filter according to claim 1 or 2, further comprising: the cumulative addition means for adding the output of the signal holding means and the output of the delay means. 4. The signal holding means includes a register circuit controlled by the system clock of the first control signal, and the delay means includes a delay circuit for delaying the output of the register circuit according to the second control signal. 5. The digital filter according to claim 1, wherein said cumulative addition means includes an adder. 5. A storage means for storing a coefficient signal composed of a digital signal which is a coefficient of a digital filter in an internal address corresponding to an internal address signal corresponding to the coefficient signal, and an internal address generating means for generating the internal address. An address selection unit that selects the internal address signal when setting the coefficient signal and selects an input signal when performing a filter calculation and supplies the input signal to the storage unit, and uses the digital signal stored in the storage unit for the filter calculation. In the digital filter, the data generating means including coefficient signal holding means for receiving and holding the coefficient signal for each tap and cumulative addition means for sequentially cumulatively adding the coefficient signals, and control by the second control signal. The first and second selecting means, and when setting the coefficient signal, A data adder for storing the cumulative addition signal generated by the cumulative addition means at an address corresponding to the internal address signal of the storage means, and adding the digital signals stored in the storage means at the time of the filter calculation. A digital filter having. 6. The digital filter according to claim 5, wherein each tap receives a common signal of the coefficient signals. 7. The data adder is a register which is controlled by a first control signal and holds the coefficient signal, and a first control signal which selects an output of the storage means or an output of the register by a second control signal. A selector, a cascade input terminal supplied with an external signal, a second selector for selecting the first selector and the external signal with the second control signal, and a delay for delaying the output of the second selector Circuit,
6. An adder for adding the output of the delay circuit and the output of the first selector, and a cascade output terminal for outputting the output of the adder to the outside.
Or the digital filter according to item 6.