JPS58147223A - Digital filter - Google Patents

Abstract

PURPOSE:To vary filter characteristics freely, by finding an arithmetic system and the repetition frequency and coefficient of the arithmetic and then storing them in a memory when the filter characteristics are varied. CONSTITUTION:The filter characteristics are inputted from an input part 4. According to the data on the filter characteristics, a processor 9 selects optimum design algorithm to calculate filter parameters such as the arithmetic system and the repetition frequency and coefficient data of the arithmetic. Those filter parameters are written in the memory in a digital filter. The rewriting in the memory is carried out freely, so the filter with free characteristics is obtained. The processor 9 allows flexible control and the flow of data is changed freely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a filter that can change the frequency band and pass characteristics of a signal extracted from a large sword signal depending on the purpose, in a wide range of signal processing fields such as audio signal processing, image signal processing, and communication fields. .

Conventionally, as this type of filter, so-called analog filters such as passive filters or active filters using LcR elements have been generally employed, and it has been difficult to change filter characteristics and realize good cutoff performance. Digital filters have also been adopted to solve these problems, but even in these digital filters it has been difficult to construct flexible arithmetic circuits and control circuits that can freely change filter characteristics.

The present invention has been devised to overcome the problems of these conventional filters, and its purpose is to use a digital filter! - To provide a digital filter that allows control to be freely changed in the filter 1 and that can realize filter characteristics suitable for a wide variety of uses. Also,
From the parameters representing the cutoff frequency, cutoff time characteristics, and stopband characteristics that express the characteristics of the filter, we have the ability to calculate digital filter parameters that approximate these characteristics as much as possible, creating one independent universal Provide filters.

Next, embodiments of the digital filter according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block circuit diagram showing a schematic configuration of a digital filter of the present invention. In Fig. 1, ■ is a data input terminal, 2 is a product-sum operation section, 3 is a filter characteristic long terminal, 4 is a filter characteristic input section, 5 is a filter parameter calculation section, 6 is a sequence control section, and 7 is a data output terminal. are shown respectively. In this digital filter, the cutoff frequency is determined by a console panel (not shown) or an external control device to express the filter characteristics.

Filter characteristic data of the cut-off time characteristic 9 withdrawal band characteristic and stop band characteristic is stored in the filter parameter calculation unit 5 via the filter characteristic input unit 4. Filter parameter calculation unit 5
In order to construct a digital filter that approximates the set filter characteristics as closely as possible, we will explain the calculation method of the sum-of-products operation performed in the digital filter, the number of times the sum-of-products operation is repeated, and the coefficient de-value used for the sum-of-products operation. Calculate. These filter parameters are controlled by the sequence controller 6
By the timing operation, the coefficient data is transferred to the product-sum calculation unit 2, and the calculation method and number of repetitions of the product-sum calculation are transferred to the sequence control unit 6. The sum-of-products calculation section 2 repeatedly performs sum-of-products calculations on the digital data input from the data input terminal 1 under the control of the sequence control section 6, and outputs the calculation results to the data output terminal 7. The sequence control unit 6 controls the order of calculations, the order of storing intermediate results, and the order of reading coefficient data in the product-sum calculation unit 2.

Next, details of each component of the digital filter of the present invention having the above configuration and its operation will be explained.

FIG. 2 is a block circuit diagram showing details of the filter parameter calculating section 5. As shown in FIG. That is, in the filter parameter calculation unit 5, data input from the filter characteristic input unit 4 is stored in a rewritable filter characteristic data memory 8. Then, the filter parameter calculation processor 9 selects from the program stored in the program memory 10 the optimal design algorithm for realizing the filter characteristics expressed by these data in a digital filter, and selects the calculation method for the sum-of-products operation. , the number of repetitions of the product-sum calculation and the filter parameters of coefficient data used in the product-sum calculation.

FIG. 3 is a block circuit diagram showing details of the product-sum calculation section 2. As shown in FIG. However, in FIG. 2, the product-sum operation requires a multiplier 11, an adder 12, and a register 13 for temporary storage of the result.
Toyoshi is executed.

In addition, there is also a rewritable coefficient memory 14 that stores coefficient data transferred from the filter parameter calculation section 5 for storing input data to these calculation units, and a rewritable coefficient memory 14 that is used for delaying input data or intermediate calculation results. A rewritable delay memory 15 is provided. Note that these memories 14 and 15 each include address circuits 16 and 17 that execute reading and writing, and the sequence control unit 6 controls the order and timing of reading and writing. Furthermore, in order to change the calculation method of the product-sum operation, a selector 18 is connected to one of the input terminals of the adder 12, and a selector 18 is connected to the input terminal of the delay memory 15.
Connect 9. However, the selector 18 selects between the input data from the data input terminal 1 and the intermediate operation result from the register 13, and the selector 19 delays the input data from the data input terminal 1 or selects between the input data from the data input terminal 1 and the intermediate operation result from the register 13. Make a choice whether to delay or not. In this case, which data is selected by each selector 18, 19 and at what timing is largely controlled by the sequence control unit 6. The final result of the calculation is transferred from the register 13 to the data output terminal 7 as output data.

Next, two typical examples of the product-sum calculation method in the product-sum calculation unit 2 shown in FIG. 3, a cyclic calculation method and an acyclic calculation method, will be described.

(1) Cyclic Arithmetic Method A digital filter is generally constructed by cascading pie-quad circuits based on the following equation.

However, H(Z): transfer function α1. α2. β1. β2: Filter coefficient 2.2. Delay Now, input data series is xl, output data series is yl
Then, the operation of the unit filter expressed by the above equation (1) is divided into the following equations (2) and (3) and processed as follows.
2) W1=xl-β,w,-1-β2w,-2 ・
(3) These calculations can be performed using the calculation steps shown in the table below.

First, when new data is input from data input terminal 1, selector 18 selects this data in step 1,
The input data of the multiplier 11 is the coefficient β1 necessary for the first stage piquad circuit read from the coefficient data memory 14, and W, -1 stored in the delay memory 15 in the previous calculation.
becomes. The adder 12 adds this multiplication result to the data selected by the selector 18, and this result appears at the output of the register 13 at the start pulse of step 2. In step 2, the selector 18 selects the output of the register 13,
The multiplier 11 and the adder 12 perform the operations shown in the figure above in the same manner as in step 1. In this calculation method, the selector 19 always selects the output of the register 13. After completing one cycle of operations from step 1 to step 5, the calculation of one stage of the piquad circuit is completed, and the calculation of the next stage begins. In this case, the same operations as described above are repeated from step 1 to step 5, except that the second stage coefficient is read from the coefficient data memory 14. However, the output of the register 13 is selected by the selector 18 as the input of the adder 12 in step 1 of the second and subsequent stages. These operations are repeated a specified number of times, that is, in multiple stages, and the result output from the register 13 at the fifth step of the final stage is output from the data output terminal 7. (2) Acyclic arithmetic method digital filter operation is expressed by the following formula.

In this calculation method, selector 18 is always register 1
The selector 19 always selects the data from the data input terminal 1. First, when data is input from data input terminal 1, this data is transferred to delay memory 1.
5, it is stored in a position aligned with past data in order. At the same time, clear the contents of register 13 and set it to 0.
Thereafter, from the coefficient data memory 14 and the delay memory 15, the address circuits 16 and 17 input the equation (
4) The data is read out according to the data order indicated by the calculation formula, multiplied by the multiplier 11, and this result is added to the cumulative value of the multiplication result output from the register 13 by the adder 12. This operation is repeated for the number of times, i.e. By repeating the filter order number of times, the output of the register 13, which is the result of the calculation, is outputted from the data output terminal 7.

The calculation method of the product-sum calculation section shown in FIG. 3 has been explained above. According to the circuit configuration shown in FIG. 3, when a new digital filter calculation method is adopted, the program of the sequence control section 6 needs to be changed. This can be easily dealt with. Therefore, the above explanation regarding the product-sum operation is just one example, and it goes without saying that various design changes can be made. FIG. 4 is a block circuit diagram of the sequence control section 6. That is, in the sequence control unit 6, the calculation method and the repetition number data of the product-sum calculation transferred from the filter parameter calculation unit 5 are stored in the calculation method memory 20 and the repetition number memory 21, respectively. Then, the sequence control processor 22 selects, from among the programs stored in the program memory 23 in advance, a program that specifies the order of calculations that must be currently executed in the product-sum calculation unit 2 according to the data in the calculation method memory 20. configured. Therefore, according to this selected program, the sequence control processor 22 causes the product-sum calculation unit 2 to
Controls read and write addresses of address circuits 16 and 17 and data selection of selectors 18 and 19;
These sequence control processes are repeatedly executed the number of times stored in the repetition number memory 17.

As is clear from the embodiments described above, according to the present invention,
By providing a sequence control unit that has a function of calculating filter parameters and employs a flexible processor, it is possible to configure a product-sum calculation unit that can freely change the data flow under software control. A digital filter whose filter characteristics can be easily changed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a schematic configuration of a digital filter according to the present invention, FIG. 2 is a block circuit diagram showing details of the filter parameter calculation section shown in FIG. 1, and FIG. A block circuit diagram showing details of the sum operation section,
FIG. 4 is a block circuit diagram showing details of the sequence control section shown in FIG. 1. 1...Data input terminal 2...Sum of products calculation unit 3...
- Filter characteristic input terminal 4...Filter characteristic input section 5...Filter parameter calculation section 6...Sequence control section 7...Data output terminal 8
... Filter characteristic data memory 9 ... Filter parameter calculation processor 10 ...
Program memory 11... Multiplier 12... Adder 13... Register 14... Coefficient data memory 15... Delay memory 16.17... Address circuit 18.19... Selector 20. ...Arithmetic method memory 21...Repetition number memory 22...Sequence control processor 23...Program memory patent applicant Japan Radio Co., Ltd.

Claims (1)

[Claims] (1) In a digital filter that realizes a P-wave effect by repeatedly performing a product-sum operation, the cut-off layer wave number, cut-off time characteristic, and stop band characteristics that express the filter characteristics are means for inputting from the outside, and means for calculating a calculation method for a sum-of-products operation, a number of repetitions of the sum-of-products operation, and coefficient data used for the sum-of-products operation from the filter characteristics;
arithmetic means for rewritably storing the coefficient data, performing a product-sum operation based on the stored data, and temporarily storing the result; and rewritably storing the calculation method and number of repetitions of the product-sum operation. 1. A digital filter having changeable filter characteristics, further comprising means for controlling the calculation means based on the stored data. (2. In the digital filter according to claim 1, the means for calculating data related to the product-sum operation from the filter characteristics includes a memory for storing the filter characteristics in a rewritable manner and a program comprising a predetermined design algorithm. A digital filter comprising a memory for storing data and a processor for reading data and programs stored in each of the memories and calculating data related to a product-sum operation. (3) In the digital filter according to claim 1, , the calculation means is a digital filter comprising a memory for storing coefficient data, a multiplier and an adder for performing a product-sum operation, and a register for temporarily storing the calculation result. (4) Claim 1 In the digital filter described in 1., the means for controlling the arithmetic means includes a memory that stores the arithmetic method and the number of repetitions of the product-sum arithmetic operation, a memory that stores a program that instructs the order of arithmetic operations, and a memory that stores the program that instructs the order of the arithmetic operations. 1. A digital filter comprising a processor that reads out data and a program and performs sequence control of arithmetic means.