JPS60114020A - Digital filter circuit - Google Patents

Abstract

PURPOSE:To prevent the number of circuit components from being increased by multiplying a sample data series subject to time division and outputted and a filter coefficient, adding the time division multiplication data so as to add the time division adding data in combination. CONSTITUTION:Adders 141-144 add outputs respectively from a delay element 132 and a moving contact 181, delay elements 132 and 136, delay elements 131 and 137, and a moving contact 171 and a delay element 134. Multipliers 151- 154 multiply each output of the adders 141-144 and filter coefficients J1-J4 from terminals 101-104 of a coefficient memory circuit 10. The outputs of the multiliers 151 and 152 are added by an adder 145 and the outputs of the multipliers 153 and 154 are added by an adder 146 respectively. Moreover, outputs of the adders 145, 146 are added by an adder 147. The output of the adder 147 is given directly to an adder 148, the output of the adder 148 is given to the adder 149 and the output of the adder 149 is given to a delay element 1312 respectively, and the adders 148, 149 and delay elements 1310, 1311 constitute an adding coupling circuit 20 adding and combining the time division data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an acyclic digital filter circuit that adds a calculated data sequence to the Nyquist interval midpoint of a sample data sequence output at a Nyquist interval in order to multiply the sampling frequency.

The transfer function of the acyclic digital filter is expressed by the following formula (%) (1) However, h (N-1) is the tap weight constant, and tII
TZ=e,,b,=2trfST=l/fs (fs is the sampling frequency). Also, in equation (1), the impulse response of the filter is h (n) = h (N-1-n)...
・・・・・・・・・Song...(21(n-0,1,2
, . . . ) By selecting the multiplication coefficients of the multipliers symmetrically with respect to the center so as to satisfy the following equation, it is possible to give the acyclic digital filter a linear phase characteristic. In addition, the acyclic digital filter always guarantees stability, has small errors when implemented using a processor with a finite word length, and has features such as no risk of limit→) cycles occurring.

FIG. 1 shows an example of a conventional circuit for filtering, for example, a sample data sequence of digital audio with a channel multiplicity of 2, R, and channels using an acyclic digital filter having the linear phase characteristic described above. .

The data word length of 1 (ratio) or R channel parallel→j-combined data sequence inputted simultaneously to the input terminal 11.1□ is converted by the multiplexer 2,
From the output, L゛, R with the sampling period Q and the period of the monthly force.
The serial sample data series of - 2 and 3 are output alternately.

The output terminal of the multiplexer 21 is connected to the input terminal of the delay element 31 of the delay circuit 3, and the output terminal of this delay element 3 is connected to the input terminal of the next stage delay element (2), and also to the output terminal of the delay element 32. 14 is connected to the input terminal of delay element 3. Delay elements 33 to 331 are similarly connected in cascade.Here, delay elements 3. to 3,1 each have 32 pins i. It is composed of a shift register or the like having a storage capacity, and the shift clock frequency of each delay element of the delay circuit 3 is set to be twice the sampling link frequency of the parallel sample data series.

Adder 41 includes delay element 31 . and the output of delay element 31°, and similarly, each adder 42 to 4+11 adds the output of delay element 314 to 31 and the output of delay element 3□7 to 3so.
and the output of the adder 4□, the multiplexer 21
and the output of delay floor ''': F3 s+ are added, respectively.

Multipliers 5I-56. l is adder 4. ~41. The output of l and the filter coefficients having different values output from the output terminals 61 to 6111 of the coefficient memory circuit 6 are multiplied by xk, . The adder 71 is the multiplier 5. output and multiplier 52
and the output of Similarly, the outputs of multipliers 53 to 5.6 are added every two by adders 72 to 78.

Adder 8□ adds the output of adder 719 and the output of adder 72. Similarly, the adders 82-84 are the adders 7°~
78 outputs are added every two. Adder 8. and 8. The outputs of adders 83 and 84 are added together by adder 9I, the outputs of adders 83 and 84 are added together by PL calculator 9□, and the outputs of adders 91 and 92 are added together by adder 10I.

With the above circuit configuration, the adder 10. outputs the calculated data sequence at the midpoint of the Nyquist interval of the sample data sequence. This output is input to the input terminal of delay element 332, and its output is sent to fixed terminal 113 of switch 11. Also, the delay element 38. The output of is sent directly to the fixed terminal 11□.

Therefore, the fixed terminal 112 to which sample data is sent out, and the fixed terminal 11 to which calculated data is sent out. and switch 1
1 movable terminal 11. By switching alternately at L, 11 . parallel sample data series are output, and multiplication of the sampling frequency is realized.

However, the operation data series J from the adder 101 is the same as that of the two-loaf extension element 31. Since the sample data series are output almost simultaneously, the calculated data series is delayed by the delay element 332 and output at the midpoint of the Nyquist interval of the sample data.

However, in order to obtain the desired frequency and amplitude characteristics in the above-mentioned acyclic digital filter circuit, the order of the filter [N in equation (1)] must be considerably high, and therefore the delay element , multipliers and adders, etc., has the disadvantage of increasing the number of filter components.

The present invention provides a linear phase acyclic digital filter circuit that eliminates the above-mentioned drawbacks, and one embodiment thereof will be described in detail below with reference to the drawings.

FIG. 2 shows a linear phase acyclic digital filter circuit having a function similar to that of FIG. Multiplexer 121
is its input terminal 11. , 112 has a Nyquist interval of 3
The parallel sample data series inputted within a time of /4 is converted into a serial sample data series, and outputted to one fixed terminal 172 of the switch 17 within a time of 174 of the Nyquist interval. Here, multiplexer 12,
The switch 17 and the switch 17 are respectively subjected to conversion control and switching control at timings to be described later, and their operations are repeated every eight cycles of the shift clock. The cape terminal 171 is connected to the delay element 13.
The output terminal of delay element 131 is connected to the input terminal of delay element 1.
32 input terminals, and the delay element 1
3□～13. are connected in cascade. Delay element 13. The output terminal of is connected to the other fixed terminal 173 of switch'+17.

Movable terminal 18. is connected to the input terminal of delay element 136, delay element 13. The output terminals of the delay elements 137 to 13 . are connected in cascade. Further, the delay element 13. The output terminal of is connected to the other fixed terminal 183 of the switch 18. Furthermore, the movable terminal 181 is connected to one fixed terminal 182 of the second switch 18 whose switching is controlled at timings described later.

Here, a delay element 131 composed of a shift register etc.
~135 indicates the first delay circuit 13A and the delay element 13
6-13. constitute the second delay circuit 13B, respectively, and the delay elements 131 to 134 and 136 to 131
3° and 13. The memory capacities of the delay elements shown in FIG. 1 are four times, one time, and three times the memory capacity of the delay element shown in FIG.

Adders 14, to 144 are delay elements 13. and movable terminal 18
□, delay elements 13□ and 136, delay element 13. and 1;3
7 and movable terminal 17. and the output from delay element 138 are added. Multipliers 151-154 are adders 141-154.
, and the output terminals 101 to 10 of the coefficient memory circuit 10
Multiply 101 to 1 each by 1 filter coefficient, .about.J4. .

The coefficients J and ~ are 1 to 1 for the 16 types of coefficients simultaneously output by the coefficient memory circuit 6 in FIG. The coefficients shown in Table 1 are repeatedly output.That is, the coefficient J is output as the coefficient 1 (16, kI
ll s k12, "+2,""'4.1 (changes like 4.

Note that the total period of the eight shift clocks matches the sampling period of sample data.

Multiplier 15. and 152 are sent to adder 14. According to
Also, the multiplier 15. and 154 are added by an adder 146, respectively. Furthermore, an adder 14. and 146 are added by an adder 147.

The output of adder 147 is directly sent to adder 14. lo) At one input terminal, there is also a delay element 13. . are connected to the other input terminals through the respective input terminals. The output of the adder 148 is connected directly to one input terminal of the adder 14° and via the delay element 13.1 to the other input terminal, respectively.
Furthermore, an adder 14. The output terminal of is connected to the input terminal of the delay element.

Here, adder 14 14. and delay element "+o, 13
．． .

constitutes an addition/combination circuit 20 that adds and combines time-division data, and delay elements 13 . . and 13,1 have a memory capacity that is one and two times larger than that of the cylindrical element shown in FIG. 1, respectively.

is the fixed end I19 of the output hatch 19 of the delay element 13I2,
Also, the movable terminal 18. of the switch 18. The outputs of are sent to their fixed terminals 192, respectively.

The signal sent from the movable terminal 19□ is output via the demultiplexer 122 from its output terminals 113 and 114 as an LlR parallel sample data series at a timing to be described later.

FIG. 3 shows the delay element 13. 139 represents the accumulated sample data series. T1~T, t: indicates an output tap from a delay element, etc., and taps Tl'l,
The data string output from T8 will be explained using Tables 2 and 3 below.

Table 2 shows pairs of taps that output sample data multiplied by the same filter coefficient from the coefficient memory circuit 10.
It shows the key/fil data output from taps T1 to T by the shift clock.

(Table 3) Table 3 shows the switches 17., . . . , which are controlled by the shift clock that shifts the data held in the delay circuits 13A and 13B.
18 shows a timing chart of on/off switching,
Switches 17 and 18 switch between times t1 and t for each shift clock.
The on/off operation shown in 8 is repeated. The sample data held in the last digit of each delay element is sent to the next stage delay element by the shift clock, and the data held inside each delay element is carried up. Furthermore, new sample data is taken into the first digit of the delay element 131.

In the above configuration, at time t, a switch occurs.

When the movable terminal 171 of the circuit 17 is connected to the fixed terminal 172, the delay element 13. The sample data L13 held by the last digit of is sent to the delay element 132, and the sample data L13 held by the last digit of
3. The sample data is carried internally, and the delay element 13. The next sample data L31 is taken into the first digit. Delay elements 132-134 also perform similar carry operations. As a result, at time t1, the delay circuit 13A
Sample data shown at time t1 in Table 2 is output from taps T1 to T4 to be multiplied. Note that the delay element 13. Sample data L held in the last digit of
14 disappears.

On the other hand, at time t1, the movable terminal 18 of the switch 18
, are connected to the fixed terminal 183, so the delay circuit 13B
The sample data is circulated within the circuit, and the sample data shown at time t1 in Table 2 is output from the taps T to T8.

Then, the next shift clock is input at time *11''2, but since switches 17 and 18 take the same state as time t1, the next sample data R31 is taken into the first digit of delay element 131. , sample data shown at time t2 in Table 3 is output from taps T1 to T4.

Note that the delay element 13. The sample data R14 held in the last digit of is lost. On the other hand, in the delay circuit 13B, sample data circulates within it in the same way as at time t.
Sample data shown at time t2 in Table 2 is output from taps T and T8.

Next, when the shift clock is input at time t, the connection state of switch 17 is changed as shown at time t3 in Table 3, and sample data is circulated between delay circuits 13A and 13B. , sample data shown at time t3 in Table 1 is output from taps T1 to T8.

Hereinafter, during the 3-cycle period of the shift clock, the switches 17 and 18 are in the same connection state as at time t3, so the tap T
Sample data shown at times 14 to t in Table 1 are output from 1 to T8, respectively.

When the next shift clock is input at time t7, the connection state of the switch 18 is changed and the delay circuit 13A is switched.
Then, the sample data is circulated, and from taps T1 to T4, the time t? of Table 1 is obtained. The sample data shown in is output. On the other hand, the sample data L, 5 held in the last digit of the delay element 134 of the delay circuit 13A is taken into the first digit of the delay element 136 of the delay circuit +3B, and the taps T, ~T
8 outputs sample data shown at time t in Table 2. Note that the sample data L held in the last digit of the delay element 139. disappears.

Then, the next shift clock is input at time t8, but since the switches 17 and 18 are in the same connection state as at time t7, the sample data is circulated in the delay circuit 13A.
Sample data shown at time t8 in Table 2 is output from taps T and -T. On the other hand, the sample data R1 held in the last digit of the delay element 134 is taken into the first digit of the delay element 136, and the sample data shown at time t2 in Table 2 is output from the taps T, ~T8. Ru. Note that the delay element 13. The sample data held in the last digit of is also lost.

As described above, 8 sample data are output from tap T, -'II''8 in response to 1 shift clock. Sample data L is output at 8 shift clocks.
31 will be output.

FIG. 4 shows a time chart for explaining the operation of the digital filter on the time axis. FIG. 4(a) shows a time chart 1 of the shift clocks, and the period of each shift clock is ⅛ of one sampling period as described above. When the shift clock is input at time t, the multiplexer 121 operates as shown in FIG. 4(1)).
Sample data L3, which is a serial sample data series, is output from the sample data L3. and outputs sample day/7 at the shift clock at time t2.

The sample data taken into each delay element is carried up sequentially at each shift clock, and as shown in FIG. is output, and at the shift clock at time t8, sample data R, .

Here, the operation of the combination adder circuit 20 will be explained based on data L of the L channel. -R31 will be used for explanation. As shown in FIG. 4(d), after the eight L channel data at time t1 are multiplied, the multiplier 15. The time-division output data Sc from the adder 147, which has been added with the time-division multiplication data output from the delay elements 13. . be taken into account. △t in the figure indicates the delay time of multiplication processing, etc. At time t3, the delay element winds up. The time division addition data Sc, which had been taken in by the delay element 13. . However, by adding the time-division addition data Sc3 of the previous adder 14□ and the adder 148, the delay element 13
The addition result sc1+sc3 is taken into the previous stage of □1.

Next, at time t, delay element 13. . The time-division addition data sc, which has been taken in by the adder 147, is output to the adder 148. At this time, the adder 148 adds the time-division addition data Sc from the adder 47 to the delay element 13I. , the addition data Sc is placed before the .

+ SC,, is taken in.

Similarly, at time t7, time-division addition data Sc, which has been taken in by delay element 131o, is output to adder 148, but at this time, adder 14. time-division addition data Sc from adder 14. As a result, the added data sc and +sc7 are taken into the stage before the delay element 1311 and output to the adder A. on the other hand,
At time t, addition data Sc+ + Scs, which had been taken in by delay element 1311, is transferred to adder 14. As shown in FIG. 4(e), from the adder 14°, the combined addition data L+5 corresponding to the operation data in FIG.
' (=Sc, + Sc, + Sc5 + 5c7
) is output to delay element 13.2.

L channel time division addition data R9, to 11. are times t2, t4.1. , 18, the L channel data is processed in the same manner as the L channel data, and the combined summation data 11+s' (
= SC2+ Sc, +! 9c6+Sc, ) is output to the delay elements 13,2.

This combined addition data L1. ', rL, , ' are the movable terminals 18 . of the switch 18 . Fixed terminal 19 of switch 19
Switch 19 is pressed between the sample data Lllll, R58, sent to □ and the next sample data L+6, R16.
As shown in FIG. 4(f), the signals are delayed by the delay element 13I by the time equal to four cycles of the shift clock minus the calculation time of the multiplier, etc., and the outputs are delayed by the delay element 13I, respectively, at the time 93, as shown in FIG. 4(f). At □, the signals are output from the fixed end quick-fire of the switch 19, respectively.

The switch 19 supplies the sample and combined summation data series Llfi, R16, Ll,', to the demultiplexer 122.
They are switched and connected to sequentially output R15', . . . .

The demultiplexer 122 is shown in FIG. 4 (gl, (11)
As shown in , sample data L31, R3, are output in parallel to the output by the shift clock at time t, and
With the shift clock of
51R1,' are output in parallel.

According to the present invention as described above, it is possible to solve the problem of an increase in the number of circuit components, which was a particular drawback when the order of a conventional acyclic digital filter was increased.
Very informative.

Note that the delay circuit of the above embodiment divides the output of the conventional delay circuit into four parts, but other
The circuits shown in FIGS. 7 and 7 divide the output of the delay circuit shown in FIG. The capacity is shown as a multiple of the storage capacity of the delay element shown in FIG.

The present invention also provides the form of the delay element, the number of circuit divisions of the delay circuit,
The storage capacity of each delay element is increased to increase the number of time-division outputs, phase characteristics, channel multiplicity, guard bits for overflow detection, extra bits to reduce rounding errors, and slight gaps in the delay circuit. The present invention is not limited to adding a circuit for detecting pits and extra bits, and various other embodiments may be adopted.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional acyclic digital filter, FIG. 2 is a circuit diagram for explaining an embodiment of the digital filter of the present invention, and FIG. 3 is a circuit diagram for explaining a delay circuit of the digital filter of the present invention. 4 are diagrams for explaining the shift clock operation of the digital filter of the present invention, and FIGS. 5 to 7 are circuit diagrams of other embodiments of the present invention. Delay element...13, ~13,2, Multiplier...151
~154, adder...14. ~149, delay circuit...
・13A, 13B.

Claims (1)

[Scope of Claims] A delay circuit that stores an input sample data sequence and outputs the sample data sequence in a time-division manner within a sampling period; a coefficient memory circuit that outputs filter coefficients in a time-division manner; a multiplier that multiplies the sample data series that is output in a time-division manner by the filter coefficient; and an adder that adds time-division multiplied data from the multiplier; A digital filter circuit comprising a combination addition circuit that combines and adds time-division addition data from the adder.