JPH05327409A - Rate conversion method and its conversion circuit - Google Patents

Abstract

PURPOSE:To provide a rate conversion method and its conversion circuit able to obtain a sufficient characteristic practically from a ROM of even a small capacity. CONSTITUTION:The conversion circuit is provided with a digital filter 13 receiving a 1st digital signal D11 to implement oversampling for a multiple of (m) (m>2 being an integral number) of a 1st sampling frequency and with an interpolation circuit 15 implementing linear interpolation with respect to an input signal. Operation by the digital filter 13 is applied to the 1st digital signal D11 at points of 1st and 2nd times having a 2nd digital signal D15 before and after inbetween timewise among point of times t1-tm being m-equal divisions of a period of the 1st digital signal D15. The result of the operation at the 1st and 2nd point of times is fed to the interpolation circuit 15, from which a 2nd digital signal D15 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data rate conversion method and a conversion circuit thereof.

[0002]

2. Description of the Related Art For example, in digital audio equipment, 48 kHz, 44.1 kHz and 32 kHz are generally used as sampling frequencies of digital audio signals.

Therefore, it may be necessary to change the sampling frequency of the digital audio signal, that is, to perform rate conversion.

As a rate conversion method, a method of conversion by linear interpolation and a method of direct conversion by selective oversampling have been considered.

That is, in the case of the method (1), the original analog audio signal is shown by the solid curve in FIG. 5B, and the clock before rate conversion (A / D conversion point) is shown in FIG.
If indicated by A, the digital audio signal before rate conversion is the data marked with a black circle in FIG. 5B. If the clock after rate conversion is shown in FIG. 5C, as shown by the broken line, a straight line connecting these marks ● is assumed, and the data marked with × is used as a rate-converted digital audio signal. Take it out.

Further, in the case of the above method, the least common multiple of the sampling frequency of the digital audio signal before rate conversion and the sampling frequency of the digital audio signal after rate conversion is set as the oversampling frequency. Then, for the over-sampling points before rate conversion that match the sampling points after conversion, actual calculation is performed to obtain a rate-converted digital audio signal.

[0007]

However, in the case of the method (1), since the linear interpolation is performed, as is apparent from FIG. 5, the level error in the digital audio signal after rate conversion may become large. Furthermore, the folding component cannot be attenuated sufficiently.

In the case of the method (1), since the oversampling frequency is the least common multiple of the sampling frequency of the digital audio signal before rate conversion and the sampling frequency of the digital audio signal after rate conversion, conversion is performed. For example, the rate combination is 44.1
At kHz and 48 kHz, the least common multiple becomes large and the oversampling multiple or frequency becomes extremely high. As a result, the number of multiplication circuits of the digital filter used for oversampling becomes extremely large, and a ROM having an enormous capacity is required as a ROM for providing the multiplication coefficient.

The present invention is intended to solve the above problems.

[0010]

Therefore, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the first digital signal D of the first sampling frequency is obtained.
In the case of rate-converting 11 into the second digital signal D15 having the second sampling frequency, the first digital signal D11 is supplied, and the digital filter 13 that performs m times oversampling of the first sampling frequency,
An interpolating circuit 15 for linearly interpolating the input signal is provided, and the second digital signal D15 is temporally sandwiched between the time points t1 to tm at which the period τ of the first digital signal D11 is equally divided into m. At the first and second time points, the operation of the digital filter 13 is performed on the first digital signal D11, and the result of the operation at the first and second time points is calculated by the interpolation circuit 15
To obtain a second digital signal D15.

[0011]

The first digital signal D11 is oversampled in the digital filter 13 by a multiple m that can obtain the required characteristics, and the oversampling sandwiches the second digital signal D15 from the front and back in terms of time. Only executed at one point. Then, the result of this oversampling is linearly interpolated by the interpolation circuit 15, and the second digital signal D15 is taken out.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a clock P21 synchronized with a digital audio signal before rate conversion is supplied to a signal forming circuit 22 through a terminal 21 to form various control signals and timing signals, and these signals will be described later. Circuit 1
2 to 16, respectively. Further, the forming circuit 22 also forms a clock P27 synchronized with the rate-converted digital audio signal, and the clock P27 is taken out to the terminal 27.

FIG. 3A shows the clock P21, and FIG. 3C shows the clock P27. The clocks P21 and P27 have a cycle of the least common multiple and their time positions coincide with each other. The time point at which the clock P21 is located is time points T1, T2, T3, ... And its period is τ.

Then, the digital audio signal D11 before rate conversion is supplied from the terminal 11 to the digital filter 13 through the input interface circuit 12. In this example, the filter 13 performs 4 times oversampling on the signal D11. For this reason,
For example, as shown in FIG. 2, the filter 13 includes five stages of delay circuits DL11 to DL15 to which the signal D11 is supplied in series, and a signal D.
11 and the delay outputs of the delay circuits DL11 to DL15 are supplied 6
The multiplication circuit MP11 to MP16 and the addition circuit SM11 to which the multiplication output is supplied form an FIR type.

Further, 14 is a coefficient ROM, which is the RO
M14 is written with multiplication coefficients used in the multiplication circuits MP11 to MP16, for example, multiplication coefficients k1 to k25 as shown in FIG. 3E, and a predetermined one of the multiplication coefficients k1 to K25 is selected and multiplied. Set to circuits MP11-MP16.

In this example, the filter 13
Since 4 times oversampling is performed, the oversampling points are time points t1 to t4 at which the period .tau. Of the clock P21 is divided into four, as shown in FIG. 3B.

Under normal circumstances, the calculation of the filter 13 is required at all time points t1 to t4 of this cycle τ, and each multiplication coefficient is set from the ROM 14 to the multiplication circuits MP11 to MP16 for each calculation. There is a need to.

However, in the present invention, FIGS.
As shown in, for example, in the period between the time points T4 and T5, since the clock P27 is located in the period between the time points t3 and t4, the filter is executed for the time points t3 and t4. Thirteen operations are executed. That is,
Generally, if the time point immediately before the clock P27 among the time points t1 to t4 is the time point tj, the operation of the filter 13 is executed only at this time point tj and the subsequent time point t (j + 1). (J is one of 1 to 4. When j = 4, j + 1
= 1).

For example, at the time t3 in the period between the time T4 and the time T5, among the multiplication coefficients k1 to K25 (FIG. 3E) written in the ROM 14, every fourth coefficient marked with a ●. k3, k7, k11, k15, k19, k23 are R
As shown in FIG. 2, the multiplication coefficients extracted from the OM 14 and extracted by the multiplication circuits MP11 to MP11 of the filter 13
It is set to MP16 and the operation is executed.

The operation output of the filter 13 is
It is supplied to the linear interpolation circuit 15. This interpolation circuit 15
As shown in FIGS. 4A to 4C (in FIG. 4, the time axis is expanded with respect to FIG. 3), the operation output of the filter 13 at the time points tj and t (j + 1) is changed to values Dj and D (j +1), a clock P is obtained from these values Dj and D (j + 1) by linear interpolation.
The value Di at the time of 27 is calculated.

Thus, from the interpolation circuit 15, every clock P27, the data D at the time of the clock P27 is obtained.
i is fetched.

Since the extracted data Di is obtained for each clock P27 after rate conversion, it is nothing but a rate-converted digital audio signal. Therefore,
This data D15 (= Di) is output as a rate-converted digital audio signal D15 to the terminal 17 through the output interface circuit 16.

In this way, the rate conversion of the digital audio signal can be performed, but generally, it is as follows.

1. Signal D11 (clock P2 before rate conversion)
1) and the signal D15 (clock P27) after the rate conversion, the period of the signal D15 in the period of the least common multiple is m · n.
(M and n are integers of 2 or more). 2. A digital filter 13 is provided for performing oversampling of the sampling frequency of the signal D11 before rate conversion by m times. 3. An interpolation circuit 15 for performing linear interpolation on the output of the filter 13 is provided. 4. Determine the time points t1 to tm at which the period τ of the signal D11 before rate conversion is divided into m equal parts. 5. Of time points t1 to tm, clock P27 after rate conversion
When the time point immediately before is defined as time point tj, this time point tj,
Only at the subsequent time point t (j + 1), the calculation of the filter 13 is executed (where j is 1 to m. When j = m, j
+ 1 = 1). The result of this calculation is the value Dj, D (j + 1)
And 6. Divide the period between time tj and time t (j + 1) into n equal parts. 7. Since one of the time points ti divided by n equals the time point of the signal D15 after rate conversion according to item 1.
The value Di at the matching time ti is set to the values Dj and D (j
+1) is calculated by linear interpolation. That is, Di = (D (j + 1) -Dj) (N / n) + Dj N: The value Di is obtained from the order of the time ti from the time tj. 8. The obtained value Di is output as the rate-converted signal D15. With the above configuration, arbitrary rate conversion can be performed.

However, in that case, if the value m is increased,
Although the amount of attenuation of the aliasing component can be increased, the capacity of the ROM 14 increases in proportion to this value m.

Therefore, in the present invention, the value m is selected to be the minimum value that allows the folding component. Then, by doing so, the capacity of the ROM 14 can be reduced to 1 / n of that in the method described above.

That is, if the value m is increased, theoretically, the rate conversion characteristic is improved, but in reality,
Since there is a limit to the characteristics of the signal D11 before rate conversion and it is meaningless to improve only the rate conversion characteristics, select a value m that is as small as necessary for the rate conversion characteristics.
Increase the value n. By doing so, the capacity of the ROM 14 can be reduced to 1 / n.

For example, when the sampling frequency is converted from 44.1 kHz to 32 kHz, m · n = 320
However, for example, m = 40, that is, the oversampling of the filter 13 is set to 40 times. Then, n = 8, and the capacity of the ROM 14 can be reduced to 1/8.

[0029]

According to the present invention, the digital filter 1
3 and the linear interpolation circuit 15 perform rate conversion, the capacity of the coefficient ROM 14 of the digital filter 13 can be reduced to 1 / n.

Since the number of multiplication coefficients required for one set of rate conversion is 1 / n, all the multiplication coefficients required for a plurality of sets of rate conversion can be prepared in the ROM 14, and a plurality of rates can be provided. A conversion circuit compatible with the conversion mode
It can be realized by a one-chip LSI.

Further, when a large value is required as the value m, the number of oversampling operations and the operation time in the filter 13 become a problem, but in the present invention, the signal D15 (clock P27) after rate conversion is applied. Since the oversampling operation only needs to be performed for the time points tj and t (j + 1) before and after the sandwiching, that is, the oversampling operation only needs to be performed twice as many as the rate-converted signal D15. The number of times is not affected by the value m, and the processing time can be afforded.

The ROM 14 has all the multiplication coefficients k1 to k25 necessary for, for example, quadruple oversampling. However, in one operation, the multiplication coefficient at the position of, for example, ● in FIG. , Every four (= m) multiplication coefficients among the multiplication coefficients k1 to k25 are set and used only in the multiplication circuits MP11 to MP16 as shown in FIG. The number of times does not change, so that the calculation time required to obtain one sample of the signal D15 is not influenced by the value m.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a system diagram showing an example of a part of FIG.

FIG. 3 is a diagram for explaining the operation of FIG.

FIG. 4 is a diagram for explaining the operation of FIG.

FIG. 5 is a diagram for explaining a conventional example.

[Explanation of symbols]

 12 input interface circuit 13 digital filter 14 coefficient ROM 15 linear interpolation circuit 16 output interface circuit 22 signal forming circuit

Claims (4)

[Claims] 1. When rate-converting a first digital signal having a first sampling frequency into a second digital signal having a second sampling frequency, the period of the first digital signal is divided into m equal parts (m). > 2), and at the time point of equally dividing into m, the first and second values sandwiching the second digital signal from the front and the rear in time.
At the point of time, the first digital signal is oversampled by m times, and the results of the oversampling at the first and second points of time are linearly interpolated to obtain the second digital signal. Rate conversion method. 2. In the case of rate-converting a first digital signal of a first sampling frequency into a second digital signal of a second sampling frequency, the first digital signal and the second digital signal When the number of cycles of the second digital signal in the cycle of the least common multiple of and is m · n (m, n is an integer of 2 or more), the time point at which the cycle of the first digital signal is divided into m equal parts At the first time point immediately before the second digital signal and the second time point subsequent to the first time point, among the time points obtained by equally dividing the m times, m times as much as the first digital signal. Oversampling is performed to obtain a time point at which the period between the first time point and the second time point is divided into n equal parts, and among these n equal parts, the time position of the second digital signal is The data at the matching time is 1 and the second
A rate conversion method in which the result of the oversampling at the point of time is obtained by linear interpolation, and the data obtained by the linear interpolation is taken out as the second digital signal. 3. A rate conversion circuit for rate-converting a first digital signal of a first sampling frequency into a second digital signal of a second sampling frequency, wherein the first digital signal is supplied and the first digital signal is supplied. A digital filter for oversampling m times the sampling frequency of 1 (m> 2 is an integer) and an interpolation circuit for linearly interpolating the input signal are provided, and the cycle of the first digital signal is m or the like. At the first and second time points at which the second digital signal is temporally sandwiched between the first and second time points during the division, the calculation of the digital filter is performed on the first digital signal to obtain the first and second time points. A rate conversion circuit configured to supply the result of the calculation at time 2 to the interpolation circuit to obtain the second digital signal. 4. A rate conversion circuit for rate-converting a first digital signal of a first sampling frequency into a second digital signal of a second sampling frequency, wherein the first digital signal and the second digital signal When the number of cycles of the second digital signal in the cycle of the least common multiple with the digital signal is m · n (m, n is an integer of 2 or more), the first digital signal is supplied and the first digital signal is supplied. Has a digital filter that performs m times oversampling of the sampling frequency and an interpolation circuit that performs linear interpolation on the input signal. In the digital filter, the cycle of the first digital signal is divided into m equal parts. Of the time points, at the first and second time points that sandwich the second digital signal from the front and back in terms of time,
M times oversampling is performed on the first digital signal, and the interpolator circuit divides the period between the first time point and the second time point into n equal parts, The data at the time when the time position coincides with the second digital signal is obtained by linearly interpolating the result of the oversampling at the first and second time points, and the data obtained by the linear interpolation is taken out as the second digital signal. Rate conversion circuit.