JP2005354354A - System provided with sampling conversion means, and digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide sampling conversion technology evading sharp increase in the circuit scale of a DV decoder by synthesizing an audio signal with a video signal without newly adding a DA conversion circuit and an AD conversion circuit. <P>SOLUTION: In a system provided with a sampling conversion means for receiving a first audio signal sampled by first sampling frequency asynchronous with a video signal, converting the first audio signal into a second audio signal of second sampling frequency synchronous with the video signal and outputting the second audio signal, the first audio signal is over-sampled by frequency corresponding to the common multiple of respective sampling frequency values of the first and second audio signals which are asynchronous in a short period but synchronous in a long period at the time of converting the sampling frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital signal processing technique and a technique that is effective when applied to sampling conversion. For example, an input audio signal sampled asynchronously with an image signal is synchronized with the image signal and has a sampling frequency different from the sampling frequency of the input audio signal. The present invention relates to a sampling conversion circuit that converts a signal of a frequency and outputs it, and a technique that is effective when used in a DV (digital video) decoder using the same.

  Many DV cameras currently on the market adopt the DV standard compatible with NTSC and PAL systems, which are the mainstream of current television broadcasting. In the DV standard, there is an unlock mode in which the image signal and the audio signal are asynchronous in addition to the lock mode in which the image signal and the audio signal are synchronized. On the other hand, when an IEEE 1394 interface is mounted on a DVD (digital video disk) recorder so that image signals and audio signals from the DV camera can be recorded, considering the connection with other systems such as a personal computer, It is desirable to record the signal and the audio signal in synchronization.

  The DVD standard has only a sampling frequency of 48 kHz, whereas the DV audio standard has three types of sampling modes of 32 kHz, 44.1 kHz, and 48 kHz. Therefore, when recording an audio signal from a DV camera on a DVD disc, the DVD recorder must support the audio signals of the above three sampling frequencies. Therefore, the present inventors have examined the provision of a sampling conversion circuit for audio signals in the DV decoder section of a DVD recorder.

  A first method of synchronizing an audio signal with an image signal is a method in which an input digital audio signal is temporarily converted back to an analog signal by a DA converter circuit, then sampled again with a clock having a desired frequency, and converted to a digital signal by an AD converter circuit. It is. The second method of synchronizing the audio signal with the image signal is to perform sampling after thinning out excess data when the number of samples in one frame is large in the unlock mode and interpolating the insufficient data when the number of samples is small. This is a conversion method. As an invention to which this method is applied, there is one described in Patent Document 1.

As another method of synchronizing the audio signal with the image signal, the audio signal is first decoded using the PLL prepared for audio, and then the second PLL synchronized with the video signal is used. An invention has been proposed in which a new synchronization is created and a sample rate processing of an audio signal is performed using this (Patent Document 2).
JP 2002-215190 A JP-A-11-317916

  In the first method, it is conceivable that the audio signal is temporarily converted back to an analog signal by using a DA converter circuit for video signal processing. When used for audio signal conversion, it is impossible to record a video signal while recording the audio signal. For this reason, a DA conversion circuit and an AD conversion circuit must be additionally provided separately from those for video, and there is a problem that the cost of the system is increased.

  On the other hand, the second method has a problem that noise is generated by thinning out or interpolating data and sound quality is deteriorated. In the third method, when a PLL is used, a filter for integrating the output of the phase comparator is required. When the DV decoder is configured as a semiconductor integrated circuit, the filter capacitor generally has a large capacitance value. Since the capacitive element is used, there is a problem that the number of external terminals and the number of parts of the chip increase, resulting in an increase in cost.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling conversion technique that can synchronize an audio signal with an image signal without newly providing a DA conversion circuit and an AD conversion circuit and avoid a significant increase in the circuit scale of a DV decoder. It is in.

  Another object of the present invention is to provide a sampling conversion technique capable of suppressing a noise level generated when converting a sampling frequency of an audio signal and improving reproduction sound quality.

  Still another object of the present invention is to provide a sampling conversion technique that eliminates the need for an external element, thereby reducing the number of external terminals, reducing the chip size, and reducing the number of components.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, sampling conversion means for receiving a first audio signal sampled at a first sampling frequency asynchronous with the image signal, converting it to a second audio signal having a second sampling frequency synchronized with the image signal, and outputting the second audio signal. In the system, the sampling frequency is converted to a common multiple of the sampling frequencies of the first audio signal and the second audio signal that are asynchronous in the short term but synchronized in the long term. The first audio signal is oversampled at a corresponding frequency.

  According to the above-described means, the audio signal can be synchronized with the image signal without newly providing a DA conversion circuit and an AD conversion circuit, and when used in a DV decoder circuit for decoding the image signal and the audio signal. A significant increase in circuit scale can be avoided.

  Here, when the first sampling frequency is any one of 48 kHz, 44.1 kHz, and 32 kHz and the second sampling frequency is 48 kHz, one sample period of the first audio signal in the frame period of the image signal is 480. Sampling conversion is performed so that the sampling point of the second audio signal exists at any point divided by an integer multiple of. Thereby, the conversion accuracy can be improved and the noise level generated during the conversion can be suppressed.

  Preferably, the number of samples of the audio signal to be input during one frame period of the image signal is compared with the number of samples of the actually input audio signal, and the sampling point is changed according to the difference. Make control. As a result, even if there is a deviation between the input audio signal or the clock signal of the receiving system, highly accurate frequency conversion is possible.

  Furthermore, desirably, a control cycle corresponding to the frequency of the human audible region is set, and control for changing the sampling point and control for not changing the sampling point are continuously performed within the control cycle. As a result, it is possible to suppress the noise level generated when converting the sampling frequency of the audio signal and improve the reproduction sound quality. Furthermore, according to the present invention, since a PLL circuit that requires an external capacitor element is not necessary, the number of external terminals can be reduced, thereby reducing the chip size and the number of components.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, a sampling conversion circuit that can synchronize an audio signal with an image signal and avoid a significant increase in the circuit scale of a DV decoder without newly providing a DA conversion circuit and an AD conversion circuit is realized. be able to.

Preferred embodiments of the present invention will be described below with reference to the drawings.
In the DV audio standard, three types of sampling modes with sampling frequencies of 48 kHz, 44.1 kHz, and 32 kHz exist for two types of systems, namely, the 525-60 system (NTSC) and the 625-50 system (PAL). In each of these modes, the allowable range of the number of samples AF_SIZE per frame of the video signal is determined. For example, in the 525-60 system, in the 48 kHz mode, the sample number AF_SIZE is a minimum of 1580 samples, a maximum of 1620 samples, and an average of 1601.6 samples. As described above, a mode in which the number of samples AF_SIZE deviates from the average value, that is, a mode in which the frame period of the video signal and the sampling frequency of the audio do not maintain a predetermined ratio is called an unlock mode.

  In the 525-60 system, in the 48 kHz mode, the first frame is 1600 samples and the second to fifth frames are 1602 samples. It is prescribed. However, in this lock mode, the average rate is considered in units of 5 frames, but the average rate is not reached in the first frame. When recording three types of audio signals of 48 kHz, 44.1 kHz, and 32 kHz corresponding to the DV standard on a DVD, it is necessary to synchronize with the video signal, so the input audio signal is sampled corresponding to the DVD standard. It must be converted to a 48 kHz signal.

The sampling conversion circuit of this embodiment realizes this conversion using two control methods. FIG. 1 shows a schematic configuration of a sampling conversion circuit according to the present embodiment.
As shown in FIG. 1, the sampling conversion circuit 200 of this embodiment takes in input audio data by oversampling and performs a product-sum operation (multiplication and addition) of the input audio data and a filter coefficient to obtain a predetermined value. Control and input sampling conversion rate using digital filter 210 that outputs data sampled at frequency, input frame timing signal, sampling frequency, number of samples AF_SIZE, NTSC / PAL identification signal, lock mode / unlock mode identification signal A control circuit 220 that obtains the position of the output sample with respect to the sample and generates output sample position information or timing, a ROM 230 that stores filter coefficients, and a ROM address that generates an address for reading a desired filter coefficient from the ROM 230 Generation And a variable frequency dividing circuit 250 for generating a clock for operating the digital filter 210 in accordance with the frequency of the input audio signal, that is, the number of input samples, and a signal for giving output sampling timing, based on the reference clock φ0. Yes.

  The variable frequency dividing circuit 250 is a static variable frequency dividing circuit (counter) that generates the operation clock φc of the digital filter 210 when the input frequency is determined, and the frequency dividing ratio is changed even during operation. Thus, the frequency dividing ratio of each variable frequency dividing circuit (counter) is set according to the mode by the control circuit 220. The control circuit 220 can know the mode from the sampling frequency and the number of samples in the frame included in the input audio stream.

  In this embodiment, the filter coefficients are not calculated but stored in the ROM. However, necessary coefficients may be calculated as needed. The digital filter 210 is a polyphase filter that is an FIR (finite impulse response) type filter.

  For example, as shown in FIG. 2A, a sampling conversion circuit using a normal FIR filter is obtained by delaying input data oversampled at N times sampling points by delay circuits DLY1 to DLYn and a predetermined filter coefficient. The sum of the values obtained by the multipliers MUL1 to MULn and then thinning out to 1 / M to obtain sample data after conversion.

  On the other hand, as shown in FIG. 2 (B), the polyphase filter multiplies multipliers MUL1 to MULn by multiplying the input data oversampled at N times the sampling points with the filter coefficient corresponding to the output sampling points. The converted sample data is obtained by summing up the values taken in step S1, and operates as if thinning is performed in the preceding stage of the multipliers MUL1 to MULn. Thus, comparing FIG. 2A and FIG. 2B shows that the same result can be obtained. On the other hand, when the product-sum operation as shown in FIG. 2B is performed, the number of multiplications of the input sampling data and the filter coefficient can be greatly reduced as compared with the product-sum operation shown in FIG.

  FIG. 2 shows that the product-sum operation in the polyphase filter is a convolution operation (convolution operation, weighted average operation). The principle of the polyphase filter is a well-known technique described in published books such as Shogodo Co., Ltd., “Multi-rate signal processing” published by Hitoshi Kiya, p. Since the same polyphase filter as that described in the same document can be used in the invention, detailed description thereof is omitted.

  As an invention in which a polyphase filter is used for the sampling conversion circuit and the frequency of the least common multiple of the input sampling frequency is used as the oversampling frequency, there is one disclosed in JP-A-8-125493. However, according to the prior invention, the FIR filter operation is performed with 3 times oversampling in the first stage and the second stage, and the polyphase filter operation is performed with 49 times oversampling in the third stage. This is different from the present invention in which all operations are performed by a polyphase filter. Since the invention of the prior application is intended to prevent the circuit from becoming complicated and large-scale, it is indispensable to perform a polyphase filter operation in part.

  Certainly, when the invention of the prior application is applied, the filter coefficient can be reduced. Therefore, when the filter coefficient is stored in the ROM, there is an advantage that the storage capacity of the ROM can be reduced. . On the other hand, since all the calculations are performed by polyphase filter calculation, the scale of the filter becomes larger than that of the prior invention. However, the invention of the present application uses a devised filter coefficient storage method as described later. Since the storage capacity of the ROM is made small, the total circuit scale is not greatly different from that of the previous application. Further, in the prior application invention in which the FIR filter calculation is performed by oversampling three times in the first stage and the second stage, fine adjustment of the sampling point as described later becomes relatively troublesome. There is also an advantage that fine adjustment can be easily performed.

  Further, in the sampling conversion circuit of the embodiment, in order to be able to correct the sampling conversion rate according to the input in order to output audio data at a predetermined sampling frequency from the digital filter 210 regardless of the lock mode / unlock mode, the control is performed. The circuit 220 is provided with a counter that counts the number of samples of audio data actually input.

  Furthermore, the sampling conversion circuit 200 of the present embodiment is configured to have the following performances (1) to (3).

(1) Number of filter taps To realize an ideal sampling conversion with no error, the number of product-sum terms (the number of taps) of the filter 210 may be infinite, but this is not feasible. On the other hand, if the number of taps is too small, the band limitation is insufficient and aliasing noise occurs. Therefore, the minimum number of taps that satisfy the noise level specification must be obtained. In order to determine the number of taps, the present inventors have created a C language simulation model and studied the optimum value.

  At this time, a sound source having an input sampling frequency of 32 kHz / 44.1 kHz and sweeping from 50 Hz to 20 kHz was used. As a result, it was found that if the number of taps is about 64, the noise level does not change even if the number of taps is further increased. Therefore, in this embodiment, 58 taps are adopted as the number of taps of the filter 210 in consideration of the capacity of the ROM 230 that stores the filter coefficients.

(2) Number of inter-sample divisions Sampling conversion is performed when the sampling frequency of the input signal is 32 kHz and 44.1 kHz, and from 32 kHz to 48 kHz and 44.1 kHz to 48 kHz, respectively. Therefore, the frequency ratio is 32 kHz: 48 kHz = 2: 3 and 44.1 kHz: 48 kHz = 147: 160. On the other hand, in order to have an error-free coefficient when the frame period of the video signal and the phase of the sampling frequency of the audio signal are synchronized, as shown in FIG. 4A, the sampling frequency of the input signal is 32 kHz. Sometimes it can be converted by interpolating the data so that it becomes a 96 kHz data string with sampling points at the points where the input sample interval is divided into three, that is, with the time axis accuracy of the reciprocal of 96 kHz which is the least common multiple of 32 kHz and 48 kHz. It can be seen that conversion is possible by virtually interpolating.

  Further, when the sampling frequency of the input signal is 44.1 kHz, the data is interpolated so that a data string of 7056 kHz having sampling points at the points obtained by dividing the input sample interval by 160 as shown in FIG. 4B. In the case of conversion from 44.1 kHz to 48 kHz, conversion is possible by virtually interpolating with the time axis accuracy of the reciprocal of 7056 kHz which is the least common multiple thereof. Accordingly, it is sufficient to divide 160 into 44.1 kHz, but in order to be able to support any of the three frequency modes of 32 kHz, 44.1 kHz, and 48 kHz as the sampling frequency on the input side, FIG. As shown in FIG. 4, it is sufficient to have a time axis accuracy of 480 divisions, which is a common multiple of “3” and “160”, or an integral multiple thereof.

  However, in the DV standard unlock mode, the number of samples in a frame has an allowable range. Therefore, an ideal conversion cannot be performed only with a specific least common multiple. On the other hand, in order to bring the performance closer to the ideal, the time axis accuracy should be set as high as possible, that is, the number of divisions between samples should be as large as possible, but this requires filter coefficients corresponding to the number of divisions. If the filter coefficients are stored in the ROM, the required storage capacity of the ROM increases. Also, if the number of divisions is reduced, the circuit scale can be reduced, but noise due to sampling errors is generated. Therefore, the minimum number of divisions must be determined so as to satisfy the noise level specification.

  The present inventors performed the same study as (1) in order to obtain a filter that satisfies the noise level specification even in the unlock mode in which the video signal and the audio signal are asynchronous. As a result, the noise level satisfies the specification when 960 divisions, which is twice the 480 division accuracy, is used, so in this embodiment, 960 divisions are adopted as the number of divisions between samples, and the time axis accuracy of the filter is 1/960 fs. Accordingly, the number of necessary filter coefficients is the number of taps × the number of divisions = 58 × 960 = 55680 words.

  The number of divisions between samples is given by the output of the frequency divider that divides the reference clock, and the frequency division ratio of the frequency divider is set according to three types of sampling modes of 32 kHz, 44.1 kHz, and 48 kHz. The As a result, a clock is output from the frequency divider such that the number of pulses between samples in each mode is 960, and the product sum of the input audio data and the filter coefficient read from the ROM in the digital filter 210 according to this clock. An operation is performed. In the 32 kHz mode, output sampling is performed every 640 (= 960 × 2/3), and in the 44.1 kHz mode, output sampling is performed every 882 (= 960 × 147/160). In the 48 kHz mode, sampling frequency conversion is performed by sampling the output every 960 (= 960 × 1/1).

(3) Control of sampling frequency conversion rate In the lock mode, the sampling conversion rate is changed every 15 frames of the input video signal as shown in FIG. 5 so that the number of input / output samples becomes an integer ratio. Control method. This is because the DV audio standard has three sampling modes of 32 kHz, 44.1 kHz, and 48 kHz as described above. In the lock mode, for example, in the 48 kHz mode of the 525-60 system, the first frame is the first. 1600 samples, 2nd to 5th frames are set to 1602 samples, and by repeating this, the average rate of 1 frame is kept constant. It is not.

  Similarly, since the average rate is 15 frames in the 32kHz mode of the 525-60 system and in one frame period in the 625-50 system, the sampling conversion rate is changed every 15 frames that are the average rate in all modes. It was decided to control. This is because if the unit is 15 frames, the number of input samples is always an integer in the lock mode in both NTSC and PAL systems, and there is no error.

  Here, as a method of controlling the sampling conversion rate every 15 frames, the cumulative value of the number of samples “AF_SIZE” (that is, the number of samples to be consumed) during the 15 frame period and the number of samples input to the circuit (ie, the number of samples) Consider a control method in which a difference “differ” from the number of samples actually consumed) is obtained, and a sampling conversion rate is determined in accordance with the difference value “differ” and the accumulated difference value “diff_sum”. In this control, the sampling conversion rate is normalized by 960, which is the time base resolution of the filter, and further, the numerical value of the sampling conversion rate “src_tgt” in the lock mode and the numerical value “delta” of the variation from “src_tgt”. I will represent it as a sum.

  By using such a numerical expression, as shown in FIG. 5, the sum of “src_tgt” and “delta” a, a ′,... Time information of the output sample with respect to the sample position) can be obtained. At this time, the difference b between the output sample position and the input sample position increases twice, three times, and so on. Note that the sampling conversion rate can be determined according to the mode by knowing the mode from the information of the sampling frequency obtained from the data stream.

  Incidentally, the sampling conversion rate “src_tgt” in the 32 kHz mode is “640” and the sampling conversion rate “src_tgt” in the 44.1 kHz mode by normalizing the sampling conversion rate by 960 which is the time axis resolution of the filter. Is “882” and the sampling conversion rate “src_tgt” in the 48 kHz mode is “960”. The sampling conversion rate “src_tgt” is provided when the lock mode does not have the 44.1 kHz mode. These sampling conversion rates “src_tgt” are used not only in the lock mode but also in the unlock mode. This is because a reference sampling conversion rate is required even in the unlock mode 44.1 kHz mode. The sampling conversion circuit according to the present embodiment can operate by using “640” or “960” without “882” as the sampling conversion rate “src_tgt”. Adjustment by "delta" and "duty" becomes easy.

More specifically, as shown in FIG. 6, when a period T0 is set as a control period and n samples are output from m1 samples input during the period T0, the period T0 ₁ The number of input samples “m1” is counted, and the number of samples to be input is obtained from the input sampling frequency and compared with the counted “m1”. From this comparison result, the control amount “delta” is determined, and the value of the sampling conversion rate (src_tgt) a2 is obtained. Since the next period T0 ₂ determines the output sample position from a2, the period T0 ₂ sampling conversion is changed. Then, in the period T0 _2, When m2 samples is input, it compares the number of samples to be input and the count value m2 obtained from similarly input sampling frequency, "delta" period from the following values T0 The operation of determining the sampling conversion rate at ₃ is repeated.

  However, in the control by the “delta”, only ± 1 is changed, and a maximum of 25 (= 1600 × 15 ÷ 960) samples are changed in 15 frames. For this reason, the error of the difference value every 15 frames becomes large, so that correction control for reducing the error is performed. This correction control allows adjustment not only to an integer but also to the decimal point. Specifically, if you want to increase +0.1 within a certain period, divide the period into 10, put 11/10 only once out of 10 times, and repeat 10/10 for the remaining 9 times. Realize.

  Similarly, when -0.1 is desired, 9/10 is inserted only once out of 10 times, and the remaining 9 times can be realized by repeating 10/10. Also, when +0.01 is desired, the period is divided into 100, and 101/100 is inserted only once out of 100 times, and the remaining 99 times are realized by repeating 100/100. Furthermore, when +0.001 is desired, the period is divided into 1000, and 1001/1000 is entered only once in 1000 times, and the remaining 999 times are realized by repeating 1000/1000. While the input sampling frequency is only a few tens of kHz at most, a logic LSI including a DV decoder that can be operated with a clock of several tens to several hundreds of MHz can be easily designed. You can make adjustments below the decimal point of the rate.

Furthermore, in this embodiment, the correction cycle is determined so that the sound fluctuation generated by the correction control is outside the audible frequency band. That is, since the output sampling frequency is 48 kHz, if correction is performed every frame (1600 samples), the frequency of noise due to sound fluctuation generated by the correction control is 30 Hz (= 48 [kHz] / 1600), which is audible. Although it falls in the frequency band (20 Hz to 20000 Hz), if the period in which 4096 samples are output is one cycle, the frequency of noise due to sound fluctuation generated by the correction control is as follows:
(Output sampling frequency) / 4096 = 48 [kHz] /4096≒11.72 [Hz]
It will deviate from the audible frequency band.

  More specifically, a numerical value “duty” determined according to the above-described difference value “differ” and the cumulative value “diff_sum” of the difference value is newly generated. As shown, control is performed to increase or decrease the conversion rate of the sample by the absolute value of “duty” in 4096 samples (2.56 frames). By performing such control, sampling conversion corresponding to when the input is asynchronous is realized.

  Further, by performing such control, as shown in FIG. 8, the sampling conversion rate changes twice within the duty control period T2, but this control cycle T2 is outside the audible frequency range (10 Hz in the embodiment). By deciding in the following, it is possible to prevent the sound fluctuation from being heard. Since the sampling position correction based on the variation “delta” is also performed every 15 frames, it is outside the audible frequency range, and the sound fluctuations associated with the correction control cannot be heard by human ears.

Next, a specific procedure when the sampling frequency conversion rate control method is applied will be described.
Here, as an example, consider a case where the input is the 48 kHz mode of the NTSC lock mode. At this time, the number of input samples is determined to be 1600 for the first frame and 1602 for the 2nd to 5th frames, so the total number of 5 frames is 8008 and the number of input samples is 24024 in 15 frames. It is. On the other hand, since the output sampling frequency is 48 kHz, the number of output samples is 1600 per frame and 24000 per 15 frames. Therefore, the difference between the number of input samples and the number of output samples is a very small value of 24 per 15 frames.

  In order to fill this difference in the number of samples, the number of input samples is counted in units of 15 frames, and the period of output samples in the next 15 frames is determined. Here, it is possible to achieve 24024/24000 by repeating 2400/2400 (2400-24) times and repeating 2401/2400 24 times. For example, this can be achieved by repeating 1000/1000 (1000-2) times and 1001/1000 twice to realize 10002/10000.

  In this embodiment, the sampling frequency conversion rate is controlled using 960/960 and 961/960. When the audio signal is synchronized with the video signal, that is, in the lock mode, the error can be prevented by using 1/960. An error occurs when the audio signal is not synchronized with the video signal, but the error is 1/960. Similarly, in order to realize 10002/10000, it can be achieved by repeating 10,000 / 10000 (10000-20) times and repeating 10001/10000 20 times. Therefore, sampling frequency is used using 9600/9600 and 9601/9600. The conversion rate may be controlled.

  Here, when 10,000 / 10000 is repeated (10000-20) times and 10001/10000 is repeated 20 times, instead of inserting 10001/10000 at equal intervals, 10001/10000 is continuously repeated 20 times and then 10,000 Even if / 10000 is repeated (10000-20) times, the same result is obtained. This corresponds to the above-described duty control of the sampling frequency conversion rate.

  In the control of the sampling frequency conversion rate as described above, the sampling conversion rate “src_tgt” and the variation “delta” are given as time axis information to the variable frequency divider 250 of FIG. This is achieved by dynamically changing. Specifically, every time the count number “9600” is given 959 times, the count number “9601” is given once, so that the frequency conversion rate can be finely adjusted to 1/960. A circuit that generates the sampling conversion rate “src_tgt” and the variation “delta” will be described later, but it is also possible to use a sigma delta modulator.

  Next, a method for storing the filter coefficient when the number of taps used for the digital filter having the above-described configuration is “58” and the time axis accuracy is 1/960 fs in the ROM 230 of FIG. 1 will be described.

Note that the ROM 230 requires a storage capacity represented by the following equation in order to store all the filter coefficients. Specifically, if the number of bits of the filter coefficient is N (= 17) and (number of taps) × (time axis accuracy) is the number of words,
N [bit] x ((number of taps) x (time axis accuracy)) [word]
= 17 [bit] x (58 x 960) [word] = 17 [bit] x 55680 [word] (1)
It is. If a ROM having such a storage capacity is to be built in a chip, the chip size will be greatly increased. Therefore, in this embodiment, the storage capacity of the ROM is reduced by storing the filter coefficient in the filter coefficient ROM 230 as follows.

FIG. 9 shows the filter coefficients with the tap numbers on the horizontal axis and the coefficient values on the vertical axis.
As is clear from FIG. 9, the filter coefficients have a symmetrical configuration, so only half of the data need be stored. When the sampling frequency of the sampling function for determining the value of the filter coefficient is set to the sampling frequency of the input signal or 1 / integer thereof, the positive / negative switching point of the filter coefficient is a tap switching as shown in FIG. Is equal to The sampling function can be restored to the original signal before the sampling conversion by causing each value sampled and converted at the sampling point to be calculated with the sampling function. Therefore, as long as the tap number is known, the sign of the filter coefficient can be known. Therefore, in this embodiment, all the filter coefficients are treated as positive numbers, and the sign bit is reduced.

  Further, as can be seen from FIG. 9, the filter coefficient is smaller by the side lobe value than the main lobe (near the middle of the tap). Therefore, the bit width of the filter coefficient corresponding to the sidelobe tap can be reduced. Therefore, in this embodiment, the bit width of the filter coefficient is reduced to the bare minimum, and the filter coefficients having different bit lengths are combined well and the data is stored as shown in FIG. Was reduced. By using this method, filter coefficients for 55680 words can be efficiently stored in a ROM of 32 [bit] × 8192 [word] (= 32 kbytes). As a result, as shown in FIG. 12, the storage capacity of the ROM can be reduced by 72.3% as compared with the method of sequentially storing the filter coefficients of all taps expressed in 17 bits.

  In FIG. 11, areas with the symbols “Tap28”, “Tap27”... Are areas where the coefficients of the 28th and 27th taps are stored, for example, areas with the code “Tap28”. , 960 16-bit filter coefficients of the 28th tap are stored, and 960 14-bit filter coefficients of the 27th tap are stored in the area labeled “Tap27”. In the area labeled Tap1 ″, 960 2-bit filter coefficients of the first tap are stored. In FIG. 11, the longest 28th tap filter coefficient is 16 bits while the number of bits of the filter coefficient is 17 bits in the above equation (1), and the sign indicating positive or negative is omitted. This is because each coefficient is stored in the ROM.

  The symbols “Tap29”, “Tap30”... Shown in parentheses mean that the coefficients of the 29th, 30th,... Are replaced with the coefficients of “Tap28”, “Tap27”. doing. Further, the space between the regions of each stage means an unused region that is not used for storing the coefficients. In this way, by storing the coefficients in the skipped area, it becomes easy to generate an address for reading each coefficient, and the scale of the address generation circuit can be reduced. Incidentally, the coefficient of each tap is read by an address that can be calculated from the tap number and the offset value.

  Here, the way of storing the filter coefficients is not limited to that shown in FIG. 11, and the same way of storing the filter coefficients is possible even when the sampling frequency of the sampling function of the filter is 1 / integer of the sampling frequency. Can be applied. That is, for example, the filter coefficient when the sampling frequency of the sampling function of the filter 210 is ½ of the sampling frequency is as shown in FIG. 13, and in this case, the positive / negative switching point of the filter coefficient is also the tap switching. Since it becomes equal to the point, the sign bit can be reduced. Further, the number of bits of the filter coefficient at each tap is reduced to the number of bits that can represent the maximum value of the coefficient (the maximum number of effective bits). Then, by storing these coefficients in appropriate combinations at the same address as shown in FIG. 14, for example, the coefficients can be efficiently stored in a ROM of 64 bits × 6144 words.

  16 shows an address generation circuit 240 for sequentially reading out filter coefficients from a ROM storing filter coefficients as shown in FIG. 11, and FIG. 15 shows control information given to the address generation circuit 240 and variable frequency dividing circuit 250. An example of the configuration of the control information circuit 221 that generates the data is shown. The control information circuit 221 in FIG. 15 is provided in the control circuit 220.

  The address generation circuit 240 basically generates an address based on the tap number “TAP_No” and an offset from the start address of the storage area corresponding to the tap number. Here, as the offset, information “tgt_cnt” indicating the output sample position in the input sample interval supplied from the control information circuit 221 of FIG. 15 is used. Thus, an address is generated from “TAP_No” and “tgt_cnt”, and a desired filter coefficient is read from the coefficient ROM 230 and supplied to the FIR filter 210.

  As shown in FIG. 15, the control information circuit 221 determines the difference between the cumulative value ΣAF_SIZE of the audio data sample number AF_SIZE in 15 frames and the audio data sample number “incnt” actually input in 15 frames. Select the subtractor ASC1 that takes "differ", the adder ADD1 that accumulates the obtained difference "differ", the register REG1 that holds the accumulated value "diff_sum", the output of the adder ADD1 or the value of the register REG1 A selector SEL1 to be sent to the register REG1, and a logic circuit ALU that calculates the above-mentioned “duty” and “delta” from the difference “differ” and its accumulated value “diff_sum”.

  For example, values such as ± 1, ± 2, ± 4, ± 8, ± 16, ± 32 are used for “delta”, and “duty” is either 0 or a value in the range of 1/4095 to 4095/4096. It is said. Specifically, when both “differ” and “diff_sum” are small, the sampling position is adjusted by changing “delta”, and when both “differ” and “diff_sum” are large, sampling is performed by changing “duty”. Adjust the position, and if "differ" is small and "diff_sum" is large or "differ" is large and "diff_sum" is small, change "duty" first, and if that is not enough, change "delta" and sample The logic circuit ALU operates to adjust the position.

  It should be noted that a circuit for monitoring “diff_sum” is provided, and when “diff_sum” becomes considerably large, the logic circuit ALU is configured to be capable of switching control so that only “delta” is generated and “duty” is not generated. You may do it. In addition, when conversion is started for the first time, it is preferable to give “delta” and “duty” as appropriate initial values according to the input sampling frequency or the like. If the initially determined initial value deviates significantly from the desired value, it is desirable to reset the initial value.

  The control information circuit 221 shown in FIG. 15 further determines whether the value obtained by dividing the number of output samples “outcnt” by “4096” is larger or smaller than “duty” depending on whether the “duty” is positive or negative (increase or decrease). Determination circuits JDG1 and JDG2, a selector SEL2 that selects the value of “src_tgt” according to the input sampling frequency, an adder ADD2 that adds the selected “src_tgt” and the “delta”, and a determination circuit A selector SEL3 that selects either the output of the adder ADD2 or a value obtained by subtracting “1” from the output according to the output of JDG1, and the output of the selector SEL3 or the output according to the output of the determination circuit JDG2. A selector SEL4 for selecting one of the values “1” is provided.

  The value selected by the selector SEL4 is supplied to one input terminal of the adder ADD3. A value held in the register REG2 is fed back to the other input terminal of the adder ADD3, and a value obtained by adding 960 to the added value “tgt_pre” or “tgt_pre” itself or “tgt_pre” is subtracted 960. The selected value is selected by the selector SEL5 according to the magnitude of “tgt_pre”, and the selected value is latched in the register REG2. Then, it is determined whether or not the holding value of the register REG2 is “960”. When the holding value of REG2 is not “960”, the holding value of REG2 is “0” when the holding value of REG2 is “960”. Is selected by the selector SEL6 and output as output sample position information "tgt_cnt".

  As shown in FIG. 16, the address generation circuit 240 uses the register 241 that holds the output sample position information “tgt_cnt” and the offset value “tgt_cnt” from the head of the block as the offset value from the block end. Is obtained by subtracting the output sample position information “tgt_cnt” from “960” and holding it, and a filter coefficient corresponding to the tap number from the tap number “TAP_No” is stored. An address calculation circuit 243 that calculates upper bits (11 bits or more such as “0000” and “1024” in FIG. 11) of the block address in the ROM, and a bit shifter that shifts the calculated address to 1024 times, that is, 10 bits higher side 244 and adders 245a and 245 for adding the shifted address and the values of the registers REG3 and REG4. Equipped with a.

  The address generation circuit 240 selects the output of the determination circuit 246 for determining whether the tap number “TAP_No” is equal to or less than “29”, and the output of the adder 245a or 245b according to the determination result. A selector 247 to be supplied to the coefficient ROM 230 as an address, a coefficient data selection circuit 248 for selecting data corresponding to the tap number “TAP_No” from the read data for one row in one block, and a tap number “TAP_No” A code generation circuit 249 that generates and outputs a code indicating whether the coefficient is positive or negative based on

  The coefficient data selection circuit 248 is provided, as shown in FIG. 11, in which the same block in the ROM stores filter coefficients of a plurality of taps such as Tap28, Tap27, and Tap1. In this embodiment, the filter coefficients of the plurality of taps are read from the ROM 230 at the same time.

  Next, an example of an application system using the sampling conversion circuit of the above embodiment will be described with reference to FIG. FIG. 17 shows a configuration diagram of a DVD recorder. The sampling conversion circuit of the above embodiment receives the image signal and audio signal from the DV camera 410 or the like input to the DVD recorder signal processing LSI 100 via the IEEE1394 interface. It is provided in the DV decoder 120 for decoding.

  The DVD recorder signal processing LSI 100 switches between a link layer 110 as an IEEE 1394 interface, a DV decoder 120 that decodes an image signal and an audio signal from the DV camera 410, a signal decoded by the DV decoder 120 and a signal from a tuner. Switch 130, MPEG encoder 140 that encodes the decoded image signal and audio signal in accordance with the MPEG system, and outputs the encoded signal to DVD driver 420 and hard disk storage device 430, or the reproduction signal input from these devices An ATAPI interface unit 150 having an encryption processing function for capturing image data, an MPEG decoder 160 for decrypting the captured reproduction signal, and an on-screen display for synthesizing the decrypted video signal with information to be displayed on the screen. Ray circuit 170, NTSC encoder 180 that converts a video signal into a signal suitable for NTSC display 440, and outputs it, audio signal processing that synthesizes and outputs a decoded audio signal and an audio signal input from an audio input terminal The circuit includes a circuit 190, a microprocessor CPU that controls the entire inside of the chip, and the like, and is formed as a semiconductor integrated circuit on a semiconductor chip such as single crystal silicon.

  As shown in FIG. 18, the DV decoder 120 separates a video stream and an audio stream from a data stream input via the link layer 110 serving as an IEEE 1394 interface and generates a frame synchronization signal. A separation circuit 121; a video signal processing circuit 122 that decodes a video signal that is encoded and transmitted according to the JPEG standard; and a video signal that outputs the decoded video signal in synchronization with an output-side synchronization reference signal φ0. A synchronization circuit 123; an audio signal processing circuit 124 that extracts audio data from an audio stream, extracts information such as a sampling frequency and the number of samples in a frame; and the synchronization reference signal for the sampling conversion circuit 200 of the embodiment. Clock synchronized with φ0 A clock generation circuit 125 for giving φref is formed.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above-described embodiment, the variation “delta” and the duty “duty” are used to adjust the sampling point of the output, but adjustment based only on the variation “delta” is also possible.

  In the above embodiment, the case where the present invention is applied to the sampling conversion circuit that converts the audio data having the input frequencies of 32 kHz, 44.1 kHz, and 48 kHz into the audio data of 48 kHz has been described. The present invention can be applied to a case where a signal having an arbitrary sampling frequency is converted into a signal having an arbitrary sampling frequency, such as a sampling conversion circuit that converts the audio data to 44.1 kHz.

  Further, by applying the embodiment of the present invention, it is possible to realize a sampling conversion circuit that can suppress the noise level generated when converting the sampling frequency of the audio signal and improve the reproduction sound quality.

  Further, it is possible to realize a sampling conversion circuit which does not require an external element and can reduce the chip size and the number of parts by reducing the number of external terminals.

  In the above description, the invention applied mainly to the sampling conversion circuit of the DV decoder provided in the signal processing LSI for the DVD recorder, which is the field of use behind the invention, has been described. The present invention is not limited, and can be generally used for a frequency conversion circuit that converts an input signal into a signal having a frequency different from that of the input signal and outputs the signal. In the above embodiment, the digital phase filter is used as the digital filter of the sampling conversion circuit. However, the method of storing the filter coefficient in the ROM of the present invention stores the filter coefficient for the polyphase filter in the ROM. It can be used not only for cases but also for digital filters in general using filter coefficients.

It is a block diagram which shows schematic structure of the sampling conversion circuit based on the Example of this invention. FIG. 2A is an explanatory diagram showing the concept of a sampling conversion circuit using a normal FIR filter, and FIG. 2B is an explanatory diagram showing the concept of a sampling conversion circuit using a polyphase filter in an embodiment of the present invention. It is. It is explanatory drawing which shows the relationship between the sampling frequency in the sampling conversion circuit which concerns on an Example, and a sampling point. It is explanatory drawing for demonstrating the sampling method in the case of converting the audio data of DV standard into the data of 48 kHz of DVD standard. It is a timing chart which shows the method of controlling the sampling conversion rate in an Example. It is explanatory drawing which shows the method of controlling the sampling conversion rate in a present Example. It is a timing chart which shows the timing of the duty control of the sampling conversion rate in an Example. It is explanatory drawing which shows the method of the duty control of the sampling conversion rate in an Example. It is explanatory drawing which illustrated the filter coefficient used for the FIR filter of the sampling conversion circuit in an Example. FIG. 10 is an explanatory diagram illustrating half of the filter coefficients illustrated in FIG. 9 in association with the positive and negative of each tap. It is explanatory drawing which illustrated the storing method in the case of storing the filter coefficient used for the FIR filter of the sampling conversion circuit in a present Example in ROM. It is explanatory drawing which illustrated the general storage method in the case of storing the filter coefficient used for a FIR filter in ROM. It is explanatory drawing which illustrated the filter coefficient when the sampling frequency of the sampling function of a FIR filter is made into 1/2 of a sampling frequency. It is explanatory drawing which illustrated the example of the storage method in the case of storing the filter coefficient of FIG. 13 in ROM. It is a block diagram which shows the structural example of the control information circuit in an Example. It is a block diagram which shows the structural example of the address generation circuit which reads a filter coefficient sequentially from ROM in which the filter coefficient was stored. It is a block diagram which shows the example of the application system using the sampling conversion circuit of an Example. It is a block diagram which shows the structural example of the DV decoder using the sampling conversion circuit of an Example.

Explanation of symbols

100 DVD Recorder Signal Processing LSI
110 IEEE 1394 link layer 120 DV decoder 140 MPEG encoder 150 ATAPI interface unit 160 MPEG decoder 170 On-screen display circuit 180 NTSC encoder 190 Audio signal processing circuit 200 Sampling conversion circuit 210 Digital filter 220 Control circuit 221 Control information circuit 230 ROM for storing filter coefficients
240 address generation circuit 250 variable frequency dividing circuit

Claims (39)

A sampling conversion circuit that receives a first audio signal sampled at a first sampling frequency asynchronous with an image signal, converts the first audio signal to a second audio signal at a second sampling frequency synchronized with the image signal, and outputs the second audio signal. A system,
When converting the sampling frequency, the first audio signal of the first sampling frequency has the same sampling point, and the sampling point is asynchronous in the short term but synchronized in the long term. A system comprising a sampling conversion circuit, wherein the sampling conversion circuit is a common multiple of sampling frequencies of the first audio signal and the second audio signal.   The system having a sampling conversion circuit according to claim 1, wherein the sampling point is a sampling point at the time of convolution calculation.   3. The system having a sampling conversion circuit according to claim 1, wherein when the sampling frequency is converted, correction for shifting the position of the sampling point on the time axis is performed in a predetermined cycle.   4. The system having a sampling conversion circuit according to claim 3, wherein the predetermined period is every 15 frames of the image signal.   4. The sampling point correction is performed according to a result obtained by comparing the number of input samples to be sampled within one frame of the image signal with the number of actually input samples. A system comprising the sampling conversion circuit described.   The sampling point correction is control for changing a correction amount in accordance with a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples. A system comprising the sampling conversion circuit according to Item 5.   The correction of the sampling point includes a first period in which the position of the sampling point is shifted according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples, and the sampling point. 6. The system comprising the sampling conversion circuit according to claim 5, wherein the ratio of the second period during which the position is not shifted is controlled to change at a predetermined cycle.   The sampling point correction is performed according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples and an accumulated value thereof. A system comprising the sampling conversion circuit according to 7. A sampling conversion function is provided that receives a first audio signal sampled at a first sampling frequency asynchronous with the image signal, converts the first audio signal to a second audio signal having a second sampling frequency synchronized with the image signal, and outputs the second audio signal. A system,
When converting the sampling frequency, a frequency corresponding to a common multiple of the sampling frequencies of the first audio signal and the second audio signal that are asynchronous in the short term but synchronized in the long term, A system having a sampling conversion function characterized by oversampling the first audio signal.   The common multiple is n times the least common multiple of the sampling frequency of each of the first audio signal and the second audio signal, and n is a positive integer of 2 or more. A system with a sampling conversion function. A sampling conversion function that receives a first audio signal sampled at any frequency within a range from the first frequency to the second frequency, converts the first audio signal to a second audio signal at the second sampling frequency, and outputs the second audio signal. A system comprising:
When converting the sampling frequency, a common sampling point is used for the first audio signal having the first sampling frequency, and all the frequency conversions are performed by a polyphase filter. Combine the half of the symmetric filter coefficients used in the product-sum operation for frequency conversion into the same area by combining the same number of effective maximum bit numbers of the coefficients of multiple taps. A system having a sampling conversion function, wherein desired coefficients are sequentially read from a stored nonvolatile memory and supplied.   The first audio signal sampled at any frequency within the range of the first frequency to the second frequency is a 32 kHz audio signal, a 44.1 kHz audio signal, or a 48 kHz audio signal. A system comprising the sampling conversion function according to claim 11.   The sampling according to claim 11, wherein the first audio signal is an audio signal that is synchronous or asynchronous with an image signal, and the sampling point is an integer multiple of 480 in one frame of the image signal. A system with a conversion function. When converting the sampling frequency, it has a control function for performing correction to shift the position on the time axis of the sampling point,
The control function is
A first control for changing a correction amount according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples;
A first period in which the position of the sampling point is shifted according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of samples actually input, and a second period in which the position of the sampling point is not shifted A second control for changing the ratio of the period in a predetermined cycle;
The system having a sampling conversion function according to claim 11, wherein the system is configured to be able to switch between execution of the first control and second control and execution of only the first control.   15. The system having a sampling conversion function according to claim 14, wherein the predetermined period is a period corresponding to a frequency outside a human audible frequency range.   Non-volatile memory comprising a plurality of delay means for delaying an input for a predetermined time, a plurality of multipliers for multiplying the output of the delay means by a predetermined coefficient, and an adder for adding the outputs of the plurality of multipliers Is a digital filter that is read out at a desired timing and supplied to the multiplier to perform a predetermined operation, and when the desired coefficient is read from the nonvolatile memory, the coefficient is Correspondingly, the digital filter is configured such that a sign indicating whether the coefficient is positive or negative is supplied from another path.   The digital filter according to claim 16, wherein the non-volatile memory stores a plurality of tap coefficients in a form expressed by the number of effective maximum bits for each tap.   18. The digital filter according to claim 16, wherein a sampling frequency of the sampling function is 1 / n (n is a positive integer of 1 or more) of the sampling frequency.   The digital filter according to claim 16, wherein the code is configured to be determined based on a tap number of the coefficient.   In the nonvolatile memory, coefficients corresponding to half of the symmetric taps out of all the filter coefficients necessary for the predetermined calculation have the same sum of effective maximum bit numbers of coefficients of a plurality of taps. The digital filters according to claim 17, which are combined and stored in the same area. A sampling conversion function for receiving a first audio signal sampled at any frequency within a range from the first frequency to the second frequency, converting the second audio signal to a second audio signal having the second sampling frequency, and outputting the second audio signal. A system comprising:
When converting the sampling frequency, a common sampling point is used for the first audio signal of the first sampling frequency, and correction for shifting the position of the sampling point on the time axis is performed in a predetermined cycle. A system having a sampling conversion function characterized by being configured.   The system having a sampling conversion function according to claim 21, wherein the first audio signal is a signal synchronized with an image signal, and the predetermined period is every 15 frames of the image signal.   The system having a sampling conversion function according to claim 22, wherein the predetermined period is a period corresponding to a frequency outside the audible frequency range.   The sampling according to claim 21, wherein the first audio signal is an audio signal that is synchronous or asynchronous with an image signal, and the sampling point is an integer multiple of 480 in one frame of the image signal. A system with a conversion function.   25. The correction of the sampling point is performed according to a result obtained by comparing the number of input samples to be sampled within one frame of the image signal with the number of actually input samples. A system with the sampling conversion function described.   The sampling point correction is control for changing a correction amount in accordance with a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples. Item 26. A system comprising the sampling conversion function of Item 25.   The correction of the sampling point includes a first period in which the position of the sampling point is shifted according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples, and the sampling point. 26. The system having a sampling conversion function according to claim 25, wherein the control is to change the ratio of the second period in which the position of the second period is not shifted in a predetermined cycle. A semiconductor integrated circuit including a sampling conversion circuit that receives a first audio signal sampled at a first sampling frequency, converts the second audio signal to a second audio signal at a second sampling frequency, and outputs the second audio signal.
When converting the sampling frequency, a common sampling point is used for the first audio signal of the first sampling frequency, and the sampling point is equal to the first sampling frequency of the first audio signal and the second sampling frequency. A semiconductor integrated circuit including a sampling conversion circuit which is n times the least common multiple of sampling frequency (n is an integer of 2 or more).   29. The semiconductor integrated circuit comprising a sampling conversion circuit according to claim 28, wherein when the sampling frequency is converted, correction for shifting the position of the sampling point on the time axis is performed in a predetermined cycle.   30. The semiconductor integrated circuit according to claim 29, wherein the first audio signal is a signal synchronized with an image signal, and the predetermined period is every 15 frames of the image signal.   31. The semiconductor integrated circuit according to claim 30, wherein the predetermined period is a period corresponding to a frequency outside a human audible frequency range.   29. The semiconductor according to claim 28, wherein the first audio signal is an audio signal that is synchronous or asynchronous with an image signal, and the sampling point exists in an integer multiple of 480 in one frame of the image signal. Integrated circuit.   The correction of the sampling point is performed according to a result obtained by comparing the number of input samples to be sampled within one frame of the image signal with the number of actually input samples. The semiconductor integrated circuit as described.   The sampling point correction is control for changing a correction amount in accordance with a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples. Item 34. The semiconductor integrated circuit according to Item 33.   The correction of the sampling point includes a first period in which the position of the sampling point is shifted according to a difference between the number of input samples to be sampled in one frame of the image signal and the number of actually input samples, and the sampling point. 34. The semiconductor integrated circuit according to claim 33, wherein the ratio of the second period during which the position is not shifted is controlled to change at a predetermined cycle.   29. The semiconductor integrated circuit according to claim 28, wherein the sampling conversion circuit can perform sampling conversion even if the first audio signal is synchronous or asynchronous with the image signal. The system according to any one of claims 1, 9, 11, and 21 is implemented by a semiconductor integrated circuit.   The digital filter according to claim 16, wherein the digital filter is formed on one semiconductor substrate.   36. The semiconductor integrated circuit according to claim 35, wherein the predetermined period is a period corresponding to a frequency outside a human audible frequency band.

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