JP2010212779A - Sampling frequency converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sampling frequency converter for synchronizing with the sampling frequency of only the output side and outputting a discrete signal after frequency conversion when the ratio of sampling frequency to be converted is not a simple integer ratio or the sampling frequency fluctuates. <P>SOLUTION: The sampling frequency converter includes: a first latch section 1-1 for capturing discrete signal data of a first sampling frequency according to clocks of the first sampling frequency and latching them; an oversampling synchronizing section 1-2 for capturing the discrete signal data outputted from the first latch circuit 1-1 according to clocks of a frequency of integer multiple of the second sampling frequency and outputting the captured data; a digital filter 1-3 for allowing a low band component of the output signal of the oversampling synchronizing section 1-2 to pass; and a decimation section 1-4 for decimating signal outputted from the digital filter 1-3 per clock of the second sampling frequency and outputting the decimated signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a sampling frequency converter. The present invention converts a sampling frequency between digital signals that are asynchronous or have different sampling frequencies, such as a signal between a digital audio output signal such as a CD (Compact Disc) and an audio signal distributed on a transmission path. The present invention relates to a device (SRC: Sampling Rate Converter).

  As an example, the sampling frequency of a consumer CD (Compact Disc) is 44.1 kHz, but the sampling frequency on a commercial audio device or transmission line is 32 kHz or 48 kHz. The amount of data varies depending on the sampling frequency, and conversion of the sampling rate including the amount of data is required. A sampling frequency converter (SRC) is used as a circuit or element that satisfies such requirements.

  In general, when digital signals with different sampling frequencies are combined, the amount of data (information amount) itself varies depending on the sampling frequency, and this is achieved by using a phase locked loop such as a PLL (Phase-locked loop) circuit. Cannot be realized by adjusting the speed to the other speed.

  FIG. 7 is a general explanatory diagram of a sampling frequency converter (SRC). A digital audio signal and a sampling frequency signal are sent from the digital audio device 7-1. As a general example, the sampling frequency Fso is 44.1 kHz, and the digital audio output signal is output in synchronization with this sampling frequency.

  The digital transmission apparatus 7-3 sends a digital audio signal to the transmission line in synchronization with the clock of the transmission network. When the 41 recommendation is followed, the sampling frequency Fst is 32 kHz. A sampling frequency converter (SRC) 7-2 receives a 32 kHz synchronization signal from the digital transmission device 7-3 and converts the speed of the digital audio signal. In this figure, the sampling frequency converter (SRC) 7-2 is shown as an independent block, but in reality, it is often built in the digital transmission device 7-3.

  As the simplest method of sampling frequency conversion, the input data of the first sampling frequency is once converted into an analog signal by digital-analog conversion, and the analog signal is analog-digital converted at the second sampling frequency and output. There is a technique.

  When various operations are performed on the configuration of the sampling frequency converter (SRC) 7-2 according to the above-described method, the sampling frequency converter (SRC) 7-2 includes a DA converter 7-4 and an AD converter 7-5.

  Then, the digital audio signal sampled at Fso = 44.1 kHz shown in FIG. 7A is converted into an analog signal by the DA converter 7-4 as shown in FIG. 7B. This analog signal is converted into a digital signal by the AD converter 7-5 at a sampling frequency of 32 kHz as shown in FIG. In contrast to the analog signal waveform shown in FIG. 2B, the vertical straight lines in FIG. 1A and FIG. 1C represent discrete digital signals.

  It can be said that all differences and fluctuations in the frequency of the sampling signal are absorbed by converting them into analog signals. In other words, this method can be said to be an excellent method that can cope with fluctuations in the sampling frequency regardless of the sampling frequency to be converted. However, the problem is degradation of the S / N ratio due to digital-analog conversion and analog-digital conversion, and an increase in noise in analog signal processing.

  As another method of converting the sampling frequency, there is a method of processing a digital signal as it is without converting it into an analog signal. This method converts the amount of information by converting to high frequency sampling data of the least common multiple and processing with a digital filter.

  As processing when the sampling frequency ratio is an integer ratio of M: N, for example, it is disclosed in Patent Document 1 below. In the one disclosed in Patent Document 1, in order to convert the sampling frequency of the input signal and the output signal into the least common multiple sampling frequency, interpolation is performed by inserting zero between the sampling data of the input signal.

  Then, the data is converted into a data string having a sampling frequency of the least common multiple obtained by deleting all unnecessary spectra through a digital filter. By sampling (decimating) data from the data string at the sampling frequency of the output signal, the sampling frequency is converted without any missing input information.

  FIG. 8 shows an example of sampling frequency conversion by the digital processing method described above. FIG. 5A shows an input signal with a sampling frequency Fso of 44.1 kHz. Between each sample point of the input signal, the S / P conversion zero insertion unit 8-1 sends a zero level signal of 14.012 MHz which is the least common multiple of 44.1 kHz and 32 kHz as shown in FIG. insert.

  In this example, since interpolation (zero insertion) is performed at 320 times the sample point, 319 zero level signals are inserted between the original input signals. By passing the signal through a steep low-pass filter (LPF) 8-2 that passes a frequency less than 1/2 of 44.1 kHz, for example, 20 kHz or less, the zero level signal disappears as shown in FIG. A sample value of 14.012 MHz following the level of the analog signal is obtained.

  Since the signal passing through the low-pass filter (LPF) 8-2 is a signal of 14.012 MHz, which is the least common multiple of 32 kHz, the signal output from the low-pass filter (LPF) 8-2 has a period of 1/32 kHz. Therefore, the signal is taken out by decimating the signal at a frequency of 32 kHz by the decimation unit 8-3, and a sample value of a sampling frequency of 32 kHz is output as shown in FIG.

  The point to be noted here is that the level of the waveform in FIG. 8C is represented by the same level as the level of the waveform in FIG. Since the energy of the signal level is smoothed to 319 zeros, the level of the waveform in (c) is reduced to 1/320 by simple calculation.

  1/320 is −50.1 dB in dB. Since the signal level is ½ (that is, decreased by 1 bit) is −6.02 dB, this corresponds to 50.3 / 6.02 = 8.3 bits. Accordingly, if the digital data of the input signal level is 24 bits, the signal level is reduced to 15 bits. The calculation result needs to be amplified accordingly. In the case of binary digital data, this corresponds to shifting by 9 bits. If the digital filter is 32 bits of double precision, there is not much influence, but if it is 16 bits, the calculation error becomes very large and it cannot be used in practice.

  The general theory of combining digital samplings with different sampling frequencies is described in Non-Patent Document 1 below. The processing in the case where the sampling frequency ratio is an integer ratio of M: N is disclosed in Patent Document 1 below. This method is theoretically correct but has the following drawbacks.

  The first drawback is that if the sampling frequency to be converted is a simple integer ratio (2: 3) such as 32 kHz and 48 kHz, the sampling frequency of the least common multiple may be as low as 96 kHz. However, when the sampling frequency to be converted is 44.1 kHz and 32 kHz, the ratio is 441: 320, and the least common multiple is 14.012 MHz, which is a very large value.

  A further problem is that when the fluctuation of the sampling timing itself such as 44.1 kHz is large, the sampling frequency varies, and the least common multiple always varies. In order to cope with this problem, the one described in Patent Document 2 below uses a method of approximating an integer ratio with a simple one without using a strict least common multiple and linearly interpolating data. .

  The following Patent Document 3 proposes a technique for avoiding the least common multiple from becoming very large and transforming into the frequency domain (digital Fourier transform and inverse Fourier transform), but this complicates the processing. In Patent Document 4 below, countermeasures against time variation are taken by interpolation using a mathematical curve called a B-splice line.

  The following Patent Document 5 processes a difference in sampling frequency in an AD converter for ΣΔ conversion, and there is basically no frequency fluctuation although the frequency ratio is different. Patent Document 6 (digital / analog conversion system and method) is an invention that combines blocks controlled to different frequencies by a PLL in a ΣΔ AD / DA converter.

  To summarize the above, a sampling frequency converter (SRC) that absorbs the difference in sampling frequency becomes a very high frequency when converted to a frequency of the least common multiple of different sampling frequencies, and constitutes a low-pass filter (LPF) that passes the signal It is not realistic to do. As an alternative, a technique for obtaining a signal to be interpolated by special calculation, a circuit for converting the signal to the frequency domain, and the like have been proposed.

  Next, the influence of a small sampling frequency shift will be described with reference to FIG. 9A shows an ideal case where there is no deviation in the sampling frequency of 44.1 kHz, FIG. 9B shows a case where the sampling frequency of 44.1 kHz is increased by 100 ppm, and FIG. 9C shows that 44.1 kHz. A case where the sampling frequency is reduced by 100 ppm is shown. Here, 1 ppm means that the pulse increased or decreased at a rate of 1 in 1,000,000.

  As shown in (a) of FIG. 9, a signal having no deviation in the sampling frequency of 44.1 kHz (0 ppm) is output as a discrete signal having a period of 22.6757 μsec. The 10,000 cycles of the discrete signal are about 226 msec.

  When the sampling frequency of 44.1 kHz is shifted to a high frequency at a rate of 100 ppm (1 in 10,000), the period of the discrete signal is 22.6735 μsec as shown in FIG. The time is shortened by 100 ppm, that is, 1/10000 from the ideal state. When 10,000 discrete signals are sent continuously in the short cycle, one discrete signal data is insufficient after 226 msec as shown in (b) with respect to the ideal state.

  Insufficient data requires input by interpolating the previous data as it is, or taking an average value with the next data and performing linear interpolation. When 44.1 kHz shifts to a low frequency at a rate of 100 ppm, one discrete signal data is not propagated (lost) after 226 msec. Therefore, as shown in (c), processing such as inputting next data is required.

  226 msec is a frequency of 4.41 Hz, which is a very low frequency spectrum outside the audible range. The frequency accuracy of 100 ppm is a fairly good value and cannot be realized without control by a high-accuracy crystal oscillator. If digital data is output by servo control of a motor such as a simple CD player, a fluctuation of 0.1% or more is predicted. If the fluctuation is large, the time when the shortage or missing of the data of the discrete signal occurs is further shortened. In a similar calculation, 1000 ppm (0.1%) is 44.1 Hz, and 10000 ppm (1%) is 441 Hz. Therefore, if harmonics are included, the noise becomes sufficiently periodic that enters the audible range.

JP-A-5-91287 Japanese Patent Laid-Open No. 11-27096 JP-A-8-23262 JP 2006-345508 A Special table flat 9-502847 JP 10-51309 A

Digital Methods for Conversion Between Arbitrary Sampling Frequencies: IEEE Transactions pm Acoustic, Speech and Signal Processing Vol.ASSP-32, No.3 JUNE 1984 TOR A.RAMSTAD

  When converting the sampling frequency, if the ratio of the sampling frequency to be converted is not a simple integer ratio, such as the sampling frequency of the digital signal from the digital audio device etc. and the sampling frequency of the digital signal distributed on the transmission line Is complicated and the circuit scale increases.

  Further, even if the ratio of sampling frequencies to be converted is a simple integer ratio (including 1: 1), there is a problem that sampling data may be lost or missing due to a difference in sampling frequency clock accuracy or the like. Also, the sampling frequency of the transmission signal may fluctuate due to fluctuations in the motor drive of the audio device and its servo circuit, resulting in missing or insufficient sampling data. These are all due to fluctuations or fluctuations in the sampling frequency, but the state is not uniform. The present invention provides a means to solve these problems.

The sampling frequency converter of the present invention is a sampling frequency converter for converting a discrete signal having a first sampling frequency into a discrete signal having a second sampling frequency, wherein the discrete signal data having the first sampling frequency is converted to the first sampling frequency. A first latch unit that captures and latches with a clock having a sampling frequency of 1 and discrete signal data output from the first latch circuit are captured and output with a clock having an integer multiple of the second sampling frequency. An oversampling synchronization unit, a digital filter that passes a low-frequency component of the output signal of the oversampling synchronization unit, and a signal output from the digital filter are output by thinning out each clock of the second sampling frequency Decimation department,
It is provided with.

  The present invention converts a sampling frequency by oversampling a discrete signal at an integer multiple of the sampling frequency of the output signal regardless of the sampling frequency of the input signal, thereby converting the sampling frequency to a simple integer multiple (M / N). In addition, even when the sampling frequency slightly changes from time to time, it is possible to output a discrete signal after frequency conversion at a timing synchronized only with the sampling frequency on the output side.

It is a figure which shows embodiment of invention. It is a figure which shows the example of a specific circuit of this invention. It is the figure which represented operation | movement of this invention in the form of the spectrum. It is a figure which shows the structural example which provided the latch circuit in the back | latter stage of the S / P conversion latch circuit. It is a figure which shows the structural example which takes in data synchronizing with LRCK. It is explanatory drawing of the influence by the shift | offset | difference of the minute sampling frequency by this invention. It is a sampling frequency converter (SRC) general explanatory drawing. It is a figure which shows the example of conversion of the sampling frequency by the method of the conventional digital processing. It is explanatory drawing of the influence by the shift | offset | difference of the conventional fine sampling frequency.

  FIG. 1 shows an embodiment of the present invention. A discrete digital signal having a sampling frequency Fso of 44.1 kHz shown in FIG. 6A is first latched (temporarily stored) by a clock of the sampling frequency Fso by the first stage S / P conversion latch circuit 1-1. Is done. The stored digital signal is sampled at a frequency of Fst × N sufficiently higher than the sampling frequency Fso by the oversampling synchronization circuit 1-2. Here, Fst is the sampling frequency after conversion, and N is an integer.

  As a result, the discrete waveform is a waveform in which signals of the same level appear continuously at sampling points having a frequency of Fst × N, as in the waveform shown in FIG. This is because the signal latched by the S / P conversion latch circuit 1-1 at the first stage changes only at the sampling frequency Fso of the input signal, and as shown in FIG. 1B, at the sampling frequency Fso of the input signal. The waveform changes stepwise.

  Compared to the conventional example shown in FIG. 8, in the conventional example, signals other than the discrete signal at the sampling point of the input signal are interpolated with the zero level signal. It is equivalent to interpolating by continuously inserting discrete signals of the same level.

  By passing the step-like high-frequency discrete signal through a low-pass filter (LPF) 1-3 in the next stage, as shown in FIG. The feature of this method is that there is almost no decrease in the signal level because no zero level signal is interpolated. By decimation of the discrete signal output from the low-pass filter (LPF) 1-3 at the converted sampling frequency Fst by the decimation unit 1-4 (decimation), the signal shown in FIG. Speed conversion is complete.

  In summary, the present invention converts the sampling frequency by oversampling the discrete signal at an integer multiple of the sampling frequency Fst of the output signal, regardless of the sampling frequency Fso of the input signal. By doing this, the sampling frequency conversion is not a simple integer multiple (M / N) ratio, and even when the sampling frequency slightly changes from moment to moment, at a timing synchronized only with the sampling frequency Fst on the output side, A discrete signal after frequency conversion is output.

  Although there is concern about the occurrence of aliases (unnecessary aliasing) due to data being fetched in an asynchronous state, the sampling frequency of digital audio signals originally fluctuated in the short and long terms. The characteristic deterioration on the axis is offset by the characteristic improvement in the amplitude component.

  FIG. 2 shows a specific circuit example of the present invention. In general, an output signal of a digital audio device includes DATA, which is audio serial data, BCK (Bit Clock), which is a clock signal for reading the DATA, a stereo left channel (L-ch), and a right channel (R). -Ch) is also composed of LRCK which is also a clock signal.

  Which serial data appears at which timing based on LRCK is defined by various standardized specifications. The timing chart of DATA, BCK, and LRCK is shown at the bottom of FIG. Note that DATA represents one sample value as 24 bits.

  The serial data DATA is input to the S / P conversion latch circuit 2-1, converted to parallel data of, for example, 24 bits as parallel data, and temporarily held (latched). Next, in the oversampling synchronization circuit 2-2, the parallel data is sampled at a high speed at a frequency N times the output sampling frequency Fst.

  This data is input to the low-pass filter (LPF) 2-3 at the next stage. The low-pass filter (LPF) 2-3 is a digital filter, and its configuration may be a FIR (Finite Impulse Response) filter or an IIR (Infinite Impulse Response) filter, and strictly restricts the band to 1/2 or less of the output sampling frequency Fst. . As a condition for this filter, assuming that the filter operates at a frequency M times the output sampling frequency Fst, M and N generally satisfy N ≧ M.

  The output of the low-pass filter (LPF) 2-3 is decimated (decimated) at the output sampling frequency Fst in the decimation unit 2-4. When the decimated data is output as serial data, it is processed by the P / S conversion unit 2-5 that converts parallel data into serial data.

  Due to advances in LSI, higher-order digital filters that have been impossible in the past can be realized relatively easily. Further, by using an IIR filter instead of an FIR filter as a low-pass filter (LPF), the amount of hardware can be reduced.

  FIG. 3 shows the operation of the present invention in the form of a spectrum. Since the digital audio signal is a discrete signal every 44.1 kHz, and the audio component is usually 20 kHz or less, the spectrum of 0 to 20 kHz and the spectrum is 44.1 kHz as shown in FIG. It will be folded on both sides.

  Furthermore, similar spectra appear at 88.2 kHz, 132.3 kHz, etc., which are integral multiples of 44.1 kHz. In order to oversample this signal, for example, it is sampled at 1024 kHz, which is 32 times the output sampling frequency of 32 kHz. Then, the spectrum becomes a spectrum in which the spectrum of FIG. 10A repeatedly appears in every region as shown in FIG.

  In this case, the data every 22.6757 μsec (= 1 / 44.1 kHz) is equivalent to being sampled finely every 0.9765 μsec (= 1/1024 kHz). As described above, even if the fluctuation is 100 ppm, the deviation is only 0.9765 μsec in this example as compared to 22.6757 μsec for one sample every 226 msec. Since the difference in amplitude of the audio signal in the time width of about 1 μsec is small, the distortion of the amplitude is greatly improved over the distortion due to the temporal variation.

  The higher the oversampling speed, the better, but the optimum value is determined in consideration of the means for realizing the low-pass filter (LPF). As shown in FIG. 3C, the band is limited by a low-pass filter (LPF). In this example, the band is limited to a spectrum of 0 to 15 kHz (1/2 or less of 32 kHz). By decimating and outputting this spectrum signal at 32 kHz, the spectrum signal shown in FIG. 3D is output.

  FIG. 4 shows a configuration example in which a latch circuit 4-1 is provided at the subsequent stage of the S / P conversion latch circuit 2-1. In general, in the case of a synchronous / asynchronous circuit that captures a signal that is not synchronized, if data is captured at a timing when the latched data is about to change, data may not be captured normally (racing).

In order to prevent this, as shown in FIG. 4, a latch circuit for punching out output data of the S / P conversion latch circuit 2-1 at the subsequent stage of the S / P conversion latch circuit 2-1 with a clock LRCK ^* slightly delayed from LRCK ^. 4-1. LRCK ^* can be a clock obtained by delaying LRCK by, for example, several clocks of N times the output sampling frequency Fst.

A time chart of the above-described circuit operation is shown on the right side of FIG. (A) is parallel data Data of the audio signal output from the S / P conversion latch circuit 2-1, (b) is LRCK, (c) is a clock N times the output sampling frequency Fst, (d) is LRCK ^*. , (E) shows data output from the latch circuit 4-1.

As can be seen from the time chart of FIG. 4, the parallel data Data slightly shifted from the timing at which the parallel data Data of the audio signal output from the S / P conversion latch circuit 2-1 changes (timing synchronized with LRCK). By capturing the output data of the S / P conversion latch circuit 2-1 at a timing that does not change (timing synchronized with LRCK ^* ), the data can be captured normally. This data is continuously output to the oversampling synchronization circuit 2-2 with a clock N times the output sampling frequency Fst.

FIG. 4F illustrates an example of a circuit that generates a clock LRCK ^{* obtained} by delaying LRCK by several clocks of N times the output sampling frequency Fst. This circuit example shows a circuit example in which a clock N times the output sampling frequency Fst is delayed by two clocks.

FIG. 5 shows a means for inputting zero in the same manner as the conventional method by devising a latch circuit and taking in parallel data Data in synchronization with LRCK ^* . Although the signal amplitude is reduced by inserting zero, this method can be used when the same as the conventional method is required.

As means for capturing parallel data Data in synchronization with LRCK ^* , a latch circuit 5-1 is provided between the S / P conversion latch circuit 2-1 and the oversampling synchronization circuit 2-2. The latch circuit 5-1 takes in the parallel data Data with the clock LRCKB obtained by differentiating the clock LRCK ^* obtained by slightly delaying the LRCK.

A time chart of the above-described circuit operation is shown on the right side of FIG. (A) is parallel data Data of the audio signal output from the S / P conversion latch circuit 2-1, (b) is LRCK, (c) is a clock N times the output sampling frequency Fst, (d) is LRCK ^*. , (E) shows a clock LRCKB obtained by differentiating LRCK ^* , and (f) shows data output from the latch circuit 5-1.

As can be seen from the time chart of FIG. 5, the parallel data Data can be captured at the timing when LRCK ^* changes. FIG. 5G shows an example of a circuit that generates a clock LRCKB obtained by differentiating a clock LRCK ^* obtained by slightly delaying LRCK.

  FIG. 6 is an explanatory diagram of the influence of a slight sampling frequency shift according to the present invention. (A) shows an ideal case where there is no deviation in the sampling frequency of 44.1 kHz, (b) shows a case where the sampling frequency of 44.1 kHz is increased by 100 ppm, and (c) shows that the sampling frequency of 44.1 kHz is The case where it reduces by 100 ppm is shown.

  As shown in FIG. 6A, a signal with no deviation in the sampling frequency of 44.1 kHz (0 ppm) is output as a discrete signal having a period of 22.6757 μsec. The 10,000 cycles of the discrete signal are about 226 msec.

  When the sampling frequency of 44.1 kHz shifts to a high frequency at a rate of 100 ppm (1 in 10,000), data shortage occurs as shown in FIG. 6 (b). If the frequency Fst × N is 1024 kHz, data after about 1 use is input.

  That is, the data loss of 22.6 μsec that occurs once every 226 msec and the insertion of substitute data are inserted as substitute data shifted by only 1 μsec. Although the frequency of insertion is increased, the signal level difference is smaller because the signal is 1 μsec apart than the signal 22.6 μsec apart. Temporal variations are improved by a decrease in amplitude variation (1 / N) and can be ignored.

  Even when 44.1 kHz shifts to a low frequency at a rate of 100 ppm, as shown in (c), one piece of discrete signal data is not propagated (lost) after 226 msec. As data is inserted, the temporal variation is improved by a decrease in amplitude variation (1 / N) and can be ignored.

1-1 S / P conversion latch circuit 1-2 Oversampling synchronization circuit 1-3 Low pass filter (LPF)
1-4 Decimation part

Claims (3)

In a sampling frequency converter for converting a discrete signal having a first sampling frequency into a discrete signal having a second sampling frequency,
A first latch unit that captures and latches the discrete signal data of the first sampling frequency with a clock of the first sampling frequency;
An oversampling synchronization unit that captures and outputs discrete signal data output from the first latch circuit with a clock having an integer multiple of the second sampling frequency; and
A digital filter that passes the low frequency component of the output signal of the oversampling synchronization unit;
A decimation unit that outputs a signal output from the digital filter by decimating the signal every clock of the second sampling frequency;
A sampling frequency conversion device comprising:   Between the first latch unit and the oversampling synchronization unit, the discrete signal data output from the first latch unit is output from the first latch unit at a timing position shifted from the change timing. The sampling frequency converter according to claim 1, further comprising a second latch unit that takes in and latches discrete signal data.   For the second latch unit, the rising and falling timings of the synchronization signal synchronized with the clock of the first sampling frequency are extracted, and the rising and falling timings are extracted from the first latch circuit. 3. The sampling frequency converter according to claim 2, wherein one discrete signal data to be output is captured.

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