JPS6326119A - Sampling frequency converting circuit - Google Patents

Abstract

PURPOSE:To attain highly accurate interpolation by applying over-sampling at a frequency being twice the 1st sampling frequency and using data twice the original data obtained by the over-sampling so as to apply approximation to new data. CONSTITUTION:The original sampling data whose sampling frequency is Fs1 is used to apply approximated operation to new sampling data having a sampling frequency Fs2. Thus, it is not required to restore the data in an analog signal and the increased frequency for a signal processing clock is prevented different from the system applying resampling by the least common multiple of the two sampling frequencies. Prior to the approximation, the data used for the approximation is doubled by the over-sampling. Thus, the accuracy of the approximated operation is improved and an excellent data as that having anew sampling frequency Fs2 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling frequency conversion circuit that is applied, for example, to convert the sampling frequency of a digital color video signal.

[Summary of the invention]

In this invention, in order to convert a digital signal sampled at a first sampling frequency into a digital signal at a second sampling frequency, oversampling is performed at a frequency twice as high as the first sampling frequency. 2 of the original data obtained with
New data is approximated using twice the data, and highly accurate interpolation is performed.

[Conventional technology]

The sampling frequency of the digital color video signal of the NTSC system is 3 fsc (fsc: color subcarrier frequency) + 4 fsc, 13.5 (MHz
) etc. is known. For example, if a digital color video signal with a sampling frequency of 13.5 (MHz) is
As a sampling frequency conversion circuit for converting into a signal with a sampling frequency of SC, the following first method and second method are known.

In the first method, a digital color video signal is once converted to an analog video signal, and then the analog color video signal is resampled and converted to a digital color video signal at a different sampling frequency.

In the second method, a digital color video signal is oversampled at a frequency that is the least common multiple of 4 fsc and 13.5 (MHz), and the digital signal obtained by this oversampling is passed through a low-pass filter.
A digital color video signal with another sampling frequency is obtained from the low-pass filter.

[Problem that the invention seeks to solve]

In the first method, in which the digital color video signal is once converted back to an analog signal, an analog filter for band limiting,
The signal is likely to deteriorate due to the characteristics of the amplifier, etc., and the entire sampling frequency conversion circuit cannot be constructed only from digital circuits.

In the second method, the frequency of the least common multiple of 4 fsc and 13.5 CM)Iz) becomes extremely high, making digital signal processing difficult, and even if signal processing were to be performed, the circuit scale would be extremely large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a sampling frequency conversion circuit that is constructed of small-scale digital circuits and that converts the sampling frequency with high precision.

[Means for solving problems]

In the sampling frequency conversion circuit according to the present invention, the first
an oversampling circuit 2 that samples a digital signal sampled at a sampling frequency Fsl at a sampling frequency 2Fsl that is twice the first sampling frequency Fsl; and a low-pass filter 3 to which the output signal of the oversampling circuit 2 is supplied. , and an approximation calculation circuit 4 to which the output signal of the low-pass filter 3 is supplied, and which performs approximate calculation of the value of sample data at a sampling point determined by a second sampling frequency Fs2 different from the first sampling frequency Fsl.

[Effect]

In this invention, the value of the new sampling data of the sampling frequency Fs2 is approximated using the value of the original sampling data of the sampling frequency Fsl. Therefore, there is no need to return to an analog signal once, and unlike a method of resampling at the least common multiple of two sampling frequencies, the frequency of the signal processing clock is prevented from increasing. Furthermore, in the present invention, before performing the approximate calculation, the data used for the approximate calculation is doubled by oversampling. Therefore, the accuracy of the approximation calculation becomes high, and high-quality data can be obtained as data for the new sampling frequency Fs2.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. A digital color video signal is supplied to an input terminal indicated by 1 in FIG. This input digital color video signal has a sampling frequency Fs1, for example 13
．． 5 (MHz) signal.

An input digital color video signal is supplied to an oversampling circuit 2. In the oversampling circuit 2, the sampling frequency is converted from Fsl to 2Fsl. At points where there is no sample value, a value of 0 is inserted, and the output signal of the oversampling circuit 2 is supplied to the digital low-pass filter 3 at the next stage. Data at a sampling frequency of 2Fsl from the low-pass filter 3 is supplied to an approximation calculation circuit 4.

The approximation calculation circuit 4 uses the output data of the low-pass filter 3 to form new data at a sampling frequency Fs2. The approximation calculation circuit 4 is supplied with coefficients necessary for the approximation calculation from the coefficient generation circuit 7. The coefficient generation circuit 7 is
For example, it is composed of a ROM. This approximate calculation circuit 4
The output data of is supplied to the latch 5, and a digital color video signal having a sampling frequency of Fs2, for example, 4fsc (fSc: color subcarrier frequency) is taken out to the output terminal 6.

A timing signal generation circuit 8 is provided, and a synchronization signal and a burst signal synchronized with the input digital color video signal are supplied to the timing signal generation circuit 8 through a terminal 9.
and 10, respectively. A clock with a frequency of 2Fsl generated by the timing signal generation circuit 8 is transmitted to the oversampling circuit 2. The signal is supplied to a low-pass filter 3 and an approximation calculation circuit 4. Further, a clock of frequency Fs2 generated by the timing signal generation circuit 8 is supplied to the latch 5. Further, clock signals, control signals, etc. are supplied from the timing signal generation circuit 8 to the coefficient generation circuit 7.

FIG. 2 shows a sampling frequency conversion operation to which the present invention is applied, in which O indicates the original sample value of the sampling frequency FslO, and Δ indicates the new sample value of the sampling frequency Fs2. In general, the ratio (ΔT/T') of the period T' corresponding to the sampling frequency Fsl and the interval ΔT of the new sample point to the original sample point
The value of new sample data is determined using the approximation function defined by . However, when (ΔT/T') approaches 0.5, a problem arises in that the error increases. In this invention, the oversampling circuit 2 and the low-pass filter 3 add interpolated values indicated by x in FIG. 2 to the original sample values. Therefore, the sampling frequency of the digital color video signal supplied to the approximation calculation circuit 4 is 2Fsl, and the period T corresponding to 2Fsl is 2 of T'. As a result, the approximate calculation circuit 4
The approximation accuracy in is made higher.

The low-pass filter 3 has a frequency characteristic 11 shown by a broken line in FIG. 3, and unnecessary signal components centered around the original sampling frequency Fsl are removed by the low-pass filter 3. FIG. 4 shows an example of this low-pass filter 3.

In FIG. 4, a digital color video signal having a sampling frequency of 2Fsl is supplied from an oversampling circuit 2 to an input terminal indicated by 12.

Eighteen unit delay elements are connected in cascade to the input terminal 12. The unit delay element is (T-1/(2F
sl) )) respectively. Nineteen taps are derived from this cascade of unit delay elements. Data from the center tap is multiplied by coefficient a1, data from taps derived symmetrically with respect to the center tap are added together, and coefficients a2 to alO are added to the added output.
is multiplied.

The data multiplied by coefficients a2 to alo are added by an adding circuit, and the scaling coefficient all is added to the added output.
is multiplied. This scaled data is taken out to the output terminal 13.

An example of coefficients a1 to all is shown below.

a L =4.82 a 2 =3.14a
3 =0.17a 4--0.96a 5-
−0.15 a 6 =0.47 a 7 =0.
12 a 8 = −0, 25 a 9 = −
0.10a 10-0.13a 1 1 =0.10
04 FIG. 5 shows the characteristics of the low-pass filter in which the values of the coefficients 31 to all are set as described above.

FIG. 6 shows the configuration of an example of the approximation calculation circuit 4. As shown in FIG.

In FIG. 6, the digital signal from the low-pass filter 3 (sampling frequency 2Fs) is input to the input terminal 21.
1, for example (2X 13.5) (MHz). The input signal is sent to the delay circuit 22. The signal is supplied to a delay circuit 23 and an adder circuit 24. The delay circuit 22 has a delay amount T, and the delay circuit 23 has a delay amount 2T.

Time-successive sample data of the input signal 14 indicated by broken lines in FIG. 7)' , , -+, ! -,Y-
9+, Y7°2, . . . are sequentially supplied to the input terminal 21. At the timing when sample data)'ass is supplied to the input terminal 21, sample data)'n+1 is obtained from the delay circuit 22, and sample data Yn+1 is obtained from the delay circuit 23. The output signal of the delay circuit 23 is inverted and supplied to the adder circuit 24. The input signal and the output signal of the delay circuit 23 are supplied to an adder circuit 25 .

The output signal of the adder circuit 25 is supplied to an adder circuit 26.

The output signal of the delay circuit 22, which has been doubled by the multiplication circuit 27, is inverted and supplied to the addition circuit 26.

From the adder circuit 24, a signal of (y, .3 Y+s++) is obtained, and from the adder circuit 26, a signal of (y, .++yn*) is obtained.
s 2yn-z) signal is obtained. The output signal of the adder circuit 24 is supplied to a variable delay circuit 30 via a multiplier circuit 28. The output signal of the adder circuit 26 is supplied to the variable delay circuit 32 via the multiplier circuit 29.

The output signal of the delay circuit 22 is supplied to the variable delay circuit 31. Both of the 0 multiplication circuits 28 and 29 multiply the input signal by the coefficient of A. has been done.

The variable delay circuits 30, 31, and 32 have a delay amount of T or 2T.
can be switched to As shown by the broken line in Figure 7,
When sample data Ya or Yb of sampling frequency Fs2 (for example, 4 fsc) is calculated by the approximation calculation circuit 4, variable delay circuits 30, 31.3 are used depending on the interval ΔT between the original sample data y7 and the sample data to be calculated.
The delay amount of 2 is controlled. In the case of (ΔT/T≦0.5) like the sample data Ya, the variable delay circuit 30
, 31.32 is assumed to be 2T, and sample data Ya is calculated from the original sample data )' , , -+, 3' n, 'j□1. On the other hand, sample data Yb
In the case of (Δ'l'/T>0.5), the delay amount of the variable delay circuit 30, 31, 32 is set to T, and the original sample data)'a, y□++'In+* Sample data Yb is calculated from. Variable delay circuit 30, 31.3
A control signal for controlling the amount of delay in step 2 is supplied to terminal 33 from timing signal generation circuit 8 (see FIG. 1).

The output signal of the variable delay circuit 30 is supplied to the multiplication circuit 34, and the output signal of the variable delay circuit 32 is supplied to the multiplication circuit 35.
The coefficient (ΔT/T) is supplied to the multiplier circuit 35, and the output signal of the zero multiplier circuit 34 and 35, which is supplied with the coefficient (ΔT/T)" from the coefficient generation circuit 7 to the terminal 37, The output signal is supplied to an adder circuit 38. An output terminal 39 is derived from the adder circuit 38.

The delay amounts of the variable delay circuits 30, 31, and 32 are set to 2T, and sample data Ya is calculated.

From the variable delay circuit 30 % (3' a* + 3'
a-υ is obtained, y is obtained from the variable delay circuit 31,
'A O'+s*t'' 7*- from the variable delay circuit 32
+-2'In) is obtained. Therefore, the output terminal 39
The sample data Ya obtained in the following equation is quadratic approximated.

Ya ='A (y, l*++y, 1-+-2yn)
・(AT/T)"+ 'A ()' 11+1-
)' fi−1)・(ΔT/T)+y.

Further, when the sample data yb is calculated, the delay amount of the variable delay circuits 30, 31, and 32 is set to T. Therefore, from the variable delay circuit 30, 'A(ynot)'+
, ) is obtained, y7.1 is obtained from the variable delay circuit 31, and 'A (yn.2'')'II is obtained from the variable delay circuit 32.
2yR-1) is obtained. Therefore, sample data y
b is determined by the following formula.

Yb-'A C'In, 2+V*-23'n++)
・(AT/T)"+'A ()'+5-z-y*
) ・(ΔT/T) ” Yn-+(ΔT/T) is a unique value if there is a relationship between the original sampling frequency Fsl and the converted sampling frequency Fs2 and a timing signal and data clock synchronized with the beginning of the line. Then,
(ΔT/T) can occur sequentially. (F
sl=13.5 MHz), 8 in one line
There are 58 sample data, (Fs2=4 f
sc), there are 910 sample data in the ■line. Therefore, the sampling frequency is 13.
The length of the 35 pieces of data whose sampling frequency is 4 fsc is equal to the length of the 33 pieces of data whose sampling frequency is 4 fsc. In this case, at the beginning of the line (ΔT/T
= 0), and the coefficients (ΔT/T) and (ΔT/T)" that change with one period corresponding to the number of pieces of data of the above-mentioned greatest common divisor are generated. The value of this coefficient is written in the ROM in advance.

Note that, unlike this embodiment, high-order approximation of third order or higher may be performed. Furthermore, the present invention can also be applied to SECAM and PAL systems other than the NTSC system.

[Effects of the Invention] In this invention, since the sampling frequency is converted in the form of a digital signal, unlike the method of converting it back to an analog signal once, the sampling frequency is converted to an analog circuit (amplifier).

There is no influence of errors caused by filters, etc.), and a sampling frequency conversion circuit can be realized using only digital circuits. Further, unlike a method of resampling at the least common multiple of two sampling frequencies, the clock frequency for circuit operation does not increase, and the circuit scale is prevented from increasing.

Furthermore, in the present invention, since the sampling frequency of the input digital signal is doubled by oversampling, the accuracy of approximation can be increased when approximating new sample data.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a waveform diagram used to explain the sampling frequency conversion operation, and Fig. 3 is a waveform diagram used to explain the sampling frequency conversion operation.
The figure is a schematic diagram used to explain the frequency characteristics of a low-pass filter, Figure 4 is a block diagram of an example of a low-pass filter, Figure 5 is a graph showing the frequency characteristics of an example of a low-pass filter, and Figure 6 is an approximate calculation circuit diagram. An example block diagram, FIG. 7, is a waveform diagram used to explain the operation of the approximate calculation circuit. Explanation of main symbols in the drawings 1: Input terminal, 2 Oversampling circuit, 3:
Low-pass filter, 4: Approximate calculation circuit, 6: Output terminal, 7: Coefficient generation circuit.

Claims (1)

[Claims] Oversampling means for sampling a digital signal sampled at a first sampling frequency at a sampling frequency twice the first sampling frequency, and an output signal of the oversampling means is supplied. a low-pass filter, and an output signal of the low-pass filter is supplied, and the first
1. A sampling frequency conversion circuit comprising: means for approximating the value of sample data at a sampling point defined by a second sampling frequency different from the second sampling frequency.