JPH07264626A - Sampling frequency converting circuit - Google Patents

Abstract

PURPOSE:To perform sampling frequency conversion by a small-scale circuit by using a memory for coefficients in common for both a luminance system interpolation filter and a color difference system interpolation filter when the sampling frequency conversion of the luminance signal and color difference signals of a digital video signal is performed. CONSTITUTION:This circuit consists of the luminance system interpolation 65, a luminance system FIFO 67, the color difference system interpolation filter 69, a color difference system FIFO 71, a write address generating circuit 56, a luminance system read address generating circuit 61, a color difference read address generating circuit 62, and the memory 58 for coefficients which are connected to the luminance system interpolation filter 65 and color difference system filter 69. This constitution performs the sampling frequency conversion by sharing the memory 58 for coefficient by the luminance system and color difference system. Here, the coefficient memory 58 is supplied with a clock signal of the same 4fsc as a signal supplied to the latch circuit of the luminance system interpolation filter 65 and the latch circuit of the color difference system interpolation filter 69.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency conversion circuit for digital video signals.

[0002]

2. Description of the Related Art Recently, in the fields of video equipment and audio equipment,
In order to improve the playback screen and audio, it is desired to process analog video and audio signals into digital signals, and digital video equipment such as digital television receivers and digital video tape recorders, and compact disc players, Digital audio devices such as digital audio tape recorders have been devised.

In the digital video equipment and the digital audio equipment, the sampling frequency at the time of conversion into digital data differs depending on the equipment or manufacturer. For example, the sampling frequency of a digital television receiver is often 3 fsc. Alternatively, the frequency becomes 4 fsc (fsc is the color subcarrier frequency). Therefore, when exchanging data between different devices, it is necessary to convert the sampling frequency of input or output data.

A conventional sampling frequency conversion circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-73781.

A case of conversion from 4fsc to 3fsc (4fsc, 3fsc are frequencies indicated by an integer ratio of 4: 3) by a conventional sampling frequency conversion circuit will be described below.

Data Q _i (..., Q _-1 , Q ₀ , Q ₁ , ...) sampled by 4 fsc and P _j (..., P _-1 , P ₀ , P ₀ , sampled by 3 fsc) P ₁ , ...) has a specific phase relationship as shown in FIG. 10, and the following equation is established from this phase relationship.

[0007]

[Equation 1]

Here, K and l are integers, S _{3l + 4} , S _3l and S
3l _-4 is impulse response data of an ideal low-pass filter in the band ω that operates at a frequency of 12 fsc.

That is, according to (Equation 1), 12 fsc
The interpolating filter that operates in 3 can be divided into three types of filters, and conversion can be realized by switching the three filters with a clock of 3 fsc.

As shown in (Equation 1), an ideal conversion can be performed by performing an infinite number of additions. However, since it is actually impossible, the 25th order as shown in FIG. Use the filter of. The phase relationship at this time has a specific phase relationship as shown in FIG. 9, and (Equation 1) becomes (Equation 2).

[0011]

[Equation 2]

The conversion of (Equation 2) into a determinant gives (Equation 3).

[0013]

[Equation 3]

FIG. 11 shows a conventional sampling frequency conversion circuit, which realizes the configuration represented by (Equation 3).

In FIG. 11, 5 is an input terminal for digital data of 4 fsc cycle, 6 to 18 are latch circuits, and 19 to 19.
Reference numeral 29 is a multiplication circuit, 31 to 40 are addition circuits, 41 is a coefficient control circuit, and 42 is an output terminal of digital data of 3 fsc cycle.

The operation of the sampling frequency conversion circuit configured as described above will be described below.

A clock signal of 4 fsc is used as a clock in the latch circuits 6 to 8, and fsc in the latch circuits 9 to 12.
Clock signal is used as a clock, and the latch circuits 13 to 1
In 8, the clock signal is 3 fsc. The clock signals of 4fsc, 3fsc, and fsc must have a predetermined synchronization relationship.

Each of the latch circuits 6 to 18 operates as a delay circuit for one clock. The coefficient control circuit 41 includes
The same 3fs that is supplied to the latch circuits 13 to 18
The c clock signal is supplied. Then, from the coefficient control circuit 41, the coefficients α ₀ to
α ₁₀ is output. Then, this coefficient is sequentially switched at the cycle of the 3fsc clock signal.

The adders 31 to 40 add the outputs of the multipliers and the latch circuits and output the result. The latch circuits 9 to 12 output four data in parallel. This is because four data must be held for one cycle period of switching the multiplication coefficient.

Then, when the data Qn as shown in FIG. 12A is input, it is delayed and converted into parallel data, e, f, g,
The output is like h.

First, in the first 1/3 fsc period, α
_{0, α 1, α 2} of S _-5 as coefficients, S _-8, is supplied S _-11, is to latch circuit _{13 (S -11 Q 0 + S} -8 Q 1 + S -5
Q ₂ ) data is supplied. In the next 1/3 fsc period, S _-9 , S _-12 , 0 are output as coefficients, and the data of (S _-12 Q ₁ + S _-9 Q ₂ ) is supplied to the latch circuit 13. All the coefficients are 0 in the last 1/3 fsc period,
Then, 1 / fsc is generated by the latch circuits 13, 14, and 15.
It is delayed for a period and input to the adder 33.

The coefficients α _{3 to} α ₁₀ are similarly controlled, and finally the converted output signal P ₂ , expressed by (Equation 3),
It is output to V as P ₃ and P ₄ .

[0023]

However, in the above-mentioned conventional configuration, in order to perform the sampling frequency conversion of the luminance signal and the color difference signal of the digital video signal as shown in FIG. 4, for example, the same circuit is used for the luminance system and the color difference system. However, there is a problem in that the circuit scale increases.

The present invention solves such a conventional problem, in which the coefficient memory is shared by the luminance interpolation filter and the color difference interpolation filter, and the sampling frequency conversion is performed by a circuit smaller than the conventional one. An object of the present invention is to provide a sampling frequency conversion circuit capable of performing the above.

[0025]

In order to achieve this object, a sampling frequency conversion circuit of the present invention provides a luminance frequency signal and a color difference signal sampled at a sampling frequency fm with a sampling frequency fn (fm lower than the sampling frequency fm. , Fn are sampling frequency conversion circuits that convert the luminance signal and the dot-sequential color difference signal that are sampled at mutually prime integer ratios m: n) and output the converted luminance signals and the write address at the cycle of the write address clock. A write address generation circuit that outputs a signal, a luminance system read address generation circuit that outputs a read address signal at a cycle of the sampling frequency fm, and a color difference system that outputs a read address signal at a cycle of 1/2 of the sampling frequency fm. A read address generation circuit,
A coefficient memory to which coefficient data input from the outside is written to an address of the write address generation circuit, and an address signal of the luminance system read address generation circuit and an address signal of the color difference system read address generation circuit are supplied,
A luminance interpolation filter for multiplying and adding the luminance signal sampled at the sampling frequency fm and the coefficient data read by the luminance read address generating circuit from the coefficient memory, and outputting the luminance interpolation filter; A data first-in first-out memory for writing at the sampling frequency fm and reading out at the sampling frequency fm while thinning out mn data at a first predetermined cycle every time m pieces of output data are input, and at the sampling frequency fm. A color difference interpolation filter for performing a sum-of-products operation and outputting the sampled color difference signals and the coefficient data read from the coefficient memory by the color difference read address generation circuit, and data output from the color difference interpolation filter. m for every m input
A data first-in first-out memory for writing at the sampling frequency fm and reading at the sampling frequency fn while thinning out n pieces of data at a second predetermined cycle.

[0026]

According to the present invention, when a sampling frequency conversion of a luminance signal and a color difference signal of a digital video signal as shown in FIG. 4 is performed, a coefficient memory is used as a luminance interpolation filter as compared with a conventional sampling frequency conversion circuit. The sampling frequency conversion can be performed with a small-scale circuit by sharing it with the color difference interpolation filter.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the luminance signal and the color difference signal shown in FIG. 4 sampled by 4 fsc are converted into the data of the sampling frequency of 3 fsc, as described in the section "Prior Art". The luminance signal has the same phase relationship as Q _i and P _j shown in FIG. 9, and realizes the configuration represented by (Equation 3). Further, in the case where the coefficient data shown in FIG. 8 is used when performing the product-sum calculation of the dot-sequential color difference signals having a clock rate of 1/2 with respect to the luminance signal, each coefficient may be switched at 1/6 fsc. Has a specific phase relationship as shown in FIG. 5, and the CR signal is represented by (Equation 4) and the CB signal is represented by (Equation 5).

[0028]

[Equation 4]

[0029]

[Equation 5]

Regarding the color difference signal, (Equation 4) and (Equation 5)
The configuration represented by is realized. LP at this time
Since the cutoff of F is 1/2 that of the luminance system and the band of the color difference signal is 1/2 or less of that of the luminance signal, there is no problem.

FIG. 1 is a block diagram of a sampling frequency conversion circuit according to an embodiment of the present invention. Figure 1
, 50 is an input terminal for a luminance signal of 4 fsc cycle,
Reference numeral 51 is an input terminal of a color difference signal of 4 fsc cycle, 52 is a write address clock input terminal, 53 is a coefficient data input terminal, 54 is an input terminal of 4 fsc which is a clock before conversion, and 55 is an input of 3 fsc which is a clock after conversion. Terminals, 56 is a write address generation circuit, 58 is a coefficient memory, 61 is a luminance read address generation circuit, 62 is a color difference read address generation circuit, 65 is a luminance interpolation filter, 69 is a color difference interpolation filter, and 67 is luminance. System FIFO
(Luminance system first-in first-out memory), 71 is a color difference system FIFO
(Color difference system first-in first-out memory), 68 is a luminance signal output terminal of 3 fsc cycle, and 72 is a color difference signal output terminal of 3 fsc cycle.

The operation of the sampling frequency conversion circuit of this embodiment having the above structure will be described below.

When data Qn such as 101 shown in FIG. 6 enters the luminance interpolation filter 65 of the circuit configuration shown in FIG. 2 from the input terminal 50, 4fsc is supplied to the latch circuits 122 to 129 to which 4fsc clock signals are supplied. 1 is delayed by 1 clock each and converted into parallel, and 101 to 101 shown in FIG.
The output is 109.

The coefficient memory 58 includes a latch circuit 122.
The same clock signal of 4 fsc that is supplied to ~ 129 is supplied. The coefficient memory 58 supplies 4 to the multipliers 130 to 138 at a 4 fsc cycle.
Coefficients α _{0 to} α ₈ (111 to 119 shown in FIG. 6) that are the same as the immediately preceding coefficient are output once per time. The signals 101 to 1 output from the latch circuits 122 to 129
09 and the coefficients α _{0 to} α output from the coefficient memory 58.
₈ (111 to 119 shown in FIG. 6) are multipliers 130 to 13
They are multiplied by 8 and added by the adder 139,
The product-sum operation is performed as shown in (Equation 6) to (Equation 9). The product-sum calculated signal is an interpolation signal (P ₂ ,
_{P 3, P 4, P 4} ', ···) outputted from the terminal 66 as. Interpolation signal P _2, P _3, P ₄ to be output is the same as P _2, P _3, P ₄ of the conversion output V of the conventional example shown in FIG. 12 As apparent from the formula shown below.

[0035]

[Equation 6]

[0036]

[Equation 7]

[0037]

[Equation 8]

[0038]

[Equation 9]

The interpolation signal of 4 fsc cycle output from the terminal 66 is supplied to the luminance system FIFO by P ₄ 'with ₄ fsc clock.
Is thinned out and written, and read out at 3 fsc clock.
The luminance signals P ₂ , P ₃ , P ₄ , and P ₅ converted into the fsc cycle are output from the output terminal 68.

When data Qn such as 201 shown in FIG. 7 enters the color difference interpolation filter 69 having the circuit configuration shown in FIG. 3 from the input terminal 51, 4 fsc is supplied to the latch circuits 222 to 237 to 4 fsc. 2 are delayed by 2 clocks respectively and converted into parallel data, and the output signals 201 to 201 shown in FIG.
The output is 209.

The coefficient memory 58 includes a latch circuit 222.
The same clock signal of 4 fsc that is supplied to ˜237 is supplied. The coefficient memory 58 supplies the multipliers 238 to 246 with 8 fs cycles.
The coefficients α _{0 to} α ₈ (211 to 219 shown in FIG. 7) that are the same as the immediately preceding coefficient are output twice each time. Then, the input signal 201 and the latch circuits 223, 225, ..., 23
The signals 202 to 209 output from the output terminals 5, 237 and the coefficients α _{0 to} α ₈ output from the coefficient memory 58 (2 shown in FIG.
11 to 219) are multiplied by multipliers 238 to 246, respectively, and added by an adder 247 to obtain (Equation 10) to (Equation 1).
The product-sum operation is performed as shown in 7). The product-sum calculated signals are interpolated signals (P ₂ , P ₃ , P ₄ , P ₅ , P of ₄ fsc cycle).
₆ , P ₇ , P ₆ ′, P ₇ ′, ...) Is output from the terminal 70.

[0042]

[Equation 10]

[0043]

[Equation 11]

[0044]

[Equation 12]

[0045]

[Equation 13]

[0046]

[Equation 14]

[0047]

[Equation 15]

[0048]

[Equation 16]

[0049]

[Equation 17]

The interpolation signal of 4 fsc cycle output from the terminal 70 is written in the color difference system FIFO by thinning out P ₆ ′ and P ₇ ′ at 4 fsc clock, read out at 3 fsc clock and converted to 3 fsc cycle. ₂ ,
P ₃ , P ₄ , P ₅ , P ₆ , and P ₇ are output from the output terminal 72.

According to the present embodiment configured as described above, when the sampling frequency conversion of the luminance signal and the color difference signal of the digital video signal as shown in FIG. 4 is performed, the coefficient is higher than that of the conventional sampling frequency conversion circuit. The sampling frequency can be converted by a small-scale circuit by sharing the memory for the luminance interpolation filter and the color difference interpolation filter.

[0052]

As is apparent from the above description, according to the present invention, compared with the conventional sampling frequency conversion circuit,
By sharing the coefficient memory for the luminance interpolation filter and the color difference interpolation filter, sampling frequency conversion can be performed with a small-scale circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sampling frequency conversion circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a luminance system interpolation filter 65 in FIG.

3 is a block diagram showing an example of a color difference interpolation filter 69 in FIG.

FIG. 4 is a timing chart of a luminance signal and a color difference signal in the same embodiment.

FIG. 5 is a timing chart showing input / output signals in the same embodiment.

FIG. 6 is a timing diagram for explaining the operation of FIG.

FIG. 7 is a timing chart for explaining the operation of FIG.

FIG. 8 is a frequency spectrum diagram showing an impulse response.

FIG. 9 is a frequency spectrum diagram showing the relationship between input and output signals in the conventional example.

FIG. 10 is an explanatory diagram showing the relationship of input / output signals.

FIG. 11 is a block diagram showing a configuration of a conventional sampling frequency conversion circuit.

FIG. 12 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 50 luminance signal input terminal 51 color difference signal input terminal 52 write address clock input terminal 53 coefficient data input terminal 54 sampling frequency fm input terminal 55 sampling frequency fn input terminal 56 write address generation circuit 58 coefficient memory 61 luminance system read address generation Circuit 62 Color difference system read address generation circuit 65 Luminance system interpolation filter 67 Luminance system FIFO 69 Color difference system interpolation filter 71 Color difference system FIFO

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 9/45 Z

Claims (1)

[Claims] 1. A luminance signal and a color difference signal respectively sampled at a sampling frequency fm are sampled at a sampling frequency fn lower than the sampling frequency fm (fm and fn are frequencies indicated by mutually prime integer ratios m: n). A sampling frequency conversion circuit for converting the luminance signal and the dot-sequential color difference signal to output, and a write address generation circuit for outputting the write address signal at the cycle of the write address clock; and a read address signal at the cycle of the sampling frequency fm. A luminance read address generation circuit, a color difference read address generation circuit that outputs a read address signal at a cycle of 1/2 of the sampling frequency fm, and coefficient data externally input to the write address generation circuit. Write to the address and read the brightness system A coefficient memory to which the address signal of the address generation circuit and the address signal of the color difference read address generation circuit are supplied, the luminance signal sampled at the sampling frequency fm, and the luminance memory read address generation circuit from the coefficient memory. The luminance system interpolation filter for multiplying and summing the coefficient data read out according to the above, and for every m number of data output from the luminance system interpolation filter, mn data is input into the first predetermined value. A luminance system data first-in first-out memory that writes at the sampling frequency fm and reads out at the sampling frequency fn while thinning out at a cycle; Multiply and multiply with the coefficient data A color difference interpolation filter for calculating and outputting, and writing m-n data at the sampling frequency fm while thinning out at a second predetermined cycle every time m pieces of data output from the color difference interpolation filter are input. A sampling frequency conversion circuit, comprising: a color difference data first-in first-out memory for reading at the sampling frequency fn.