JPH0730371A - Sampling frequency converting circuit - Google Patents

Abstract

PURPOSE:To perform sampling frequency conversion whose conversion ratio is an optional integer through circuit constitution which does not depend upon the conversion ratio without being affected by mutual phase jitters by using an FIR type filter, a coefficient generating circuit which outputs the coefficient of the FIR type filter, and a memory whose writing and reading can be controlled independently. CONSTITUTION:When conversion between two sampling frequencies fs1 (mXf) and fs2 (nXf) represented with integers (m) and (n) is performed from fs1 to fs2, the FIR type filter 50 which varies in coefficient in fs1 cycles through the coefficient generating circuit 148 performs product sum arithmetic as to an input signal fs1. The signal after the product sum arithmetic is sequentially written in the RAM 51 whose write address and read address can be controlled independently while the write address of a counter 52 which operates at fs1 is controlled and then sequentially read out with the read address of a counter 53 which operates at fs2, so that the sampling frequency is converted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency conversion circuit.

[0002]

2. Description of the Related Art Recently, in the fields of video equipment and audio equipment,
In order to improve the playback screen and sound, it is desired to process analog video and audio signals into digital signals, and digital video equipment such as digital television receivers and digital video tape recorders, and compact disc players, Digital audio devices such as digital audio tape recorders have been devised.

In the digital video equipment and the digital audio equipment, the sampling frequency when converting to digital data differs between the equipments. For example, the sampling frequency of a digital television receiver is often 3f.
The frequency is sc or 4 fsc (fsc is the color subcarrier frequency). Therefore, when exchanging data between different devices, it is necessary to convert the sampling frequency of input or output data.

A conventional sampling frequency conversion circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-73781.

The case of conversion from 4fsc to 3fsc by the conventional sampling frequency conversion circuit will be described below.

Data Q _i (..., Q _-1 , Q ₀ , Q ₁ ...) sampled by 4 fsc and P _j (..., P _-1 , P ₀ , P ₀ , sampled by 3 fsc) It is known that there is a specific phase relationship as shown in FIG. 8 with P ₁ , ..., And from this phase relationship the following equation (Equation 1) is established.

[0007]

[Equation 1]

Here, k and l are integers, S _{3l + 4} , S _3l and S
3l _-4 is impulse response data of an ideal low-pass filter in the band ω that operates at a frequency of 12 fsc.

That is, according to (Equation 1), 12 fsc
The interpolating filter that operates in 3 can be divided into three types of filters, and conversion can be realized by switching the three filters with a clock of 3 fsc.

As shown in (Equation 1), an ideal conversion can be performed by performing an infinite number of additions, but it is actually impossible. Therefore, in relation to the required characteristics, for example, the 25th order as shown in FIG. Use a filter. The phase relationship at this time has a specific phase relationship as shown in FIG. 7, and (Formula 1) is as shown in (Formula 2) below.

[0011]

[Equation 2]

When the equation (2) is converted into a determinant, the following equation (3) is obtained.

[0013]

[Equation 3]

FIG. 9 shows a conventional sampling frequency conversion circuit, which realizes the configuration represented by (Equation 3).

In FIG. 9, 5 is an input terminal for digital data of 4 fsc cycle, 6 to 18 are latch circuits, and 19 to 2
Reference numeral 9 is a multiplication circuit, 31 to 40 are addition circuits, 41 is a coefficient control circuit, and 42 is an output terminal for digital data of 3 fsc cycle.

The operation of the sampling frequency conversion circuit configured as described above will be described below.

A clock signal of 4 fsc is used as a clock in the latch circuits 6 to 8, and fsc in the latch circuits 9 to 12.
Clock signal is used as a clock, and the latch circuits 13 to 1
In 8, the clock signal is 3 fsc. The 4fsc, 3fsc, and fsc clock signals must have a predetermined synchronization relationship.

Each of the latch circuits 6 to 18 operates as a delay circuit for one clock. The coefficient control circuit 41 includes
The same 3fs that is supplied to the latch circuits 13 to 18
The c clock signal is supplied. Then, from the coefficient control circuit 41, the coefficients α ₀ to
α ₁₀ is output. Then, this coefficient is sequentially switched at the cycle of the 3fsc clock signal.

The adders 31 to 40 add the outputs of the multipliers and the latch circuits and output the result. The latch circuits 9 to 12 output four data in parallel. This is because four data must be held for one cycle period of switching the multiplication coefficient.

Then, when the data Qn as shown in FIG. 10A is input, it is delayed and parallel converted to e, f,
The output is g, h.

In the first 1/3 fsc period, α ₀ ,
alpha _1, alpha ₂ of S _-5 as coefficients, S _-8, S _-11 is supplied, is to latch circuit _{13 -5 · (S -11 · Q} 0 + S -8 · Q 1 + S
Q ₂ ) data is supplied. In the next 1/3 fsc period, S _-9 , S _-12 , 0 are output as coefficients, and the data of (S _-12 · Q ₁ + S _-9 · Q ₂ ) is supplied to the latch circuit 13. All the coefficients are 0 in the last 1/3 fsc period,
Then, 1 / fsc is generated by the latch circuits 13, 14, and 15.
It is delayed for a period and input to the adder 33.

The coefficients α _{3 to} α ₁₀ are similarly controlled, and finally the converted output signal P ₂ , expressed by (Equation 3),
It is output to (V) as P ₃ and P ₄ .

[0023]

However, in the above-mentioned conventional configuration, since the sampling frequency is converted by the latch circuit in the FIR type filter, the rising of the clock before conversion (4 fsc clock in the conventional example) is performed. Clock after conversion (3 fsc in the conventional example
If phase jitter occurs such that the rising edge of (clock) fluctuates back and forth on the time axis, a latch miss occurs and normal conversion cannot be performed. Further, there is a problem that the configuration of the latch circuit in the FIR type filter has to be changed according to the conversion ratio.

The present invention solves such a conventional problem, in which a sampling frequency conversion in which a conversion ratio is an arbitrary integer is performed, an FIR type filter and a clock cycle before conversion of a plurality of coefficients of the FIR type filter are performed. By using a coefficient generation circuit that outputs by changing with, and a memory that can control writing and reading of data independently, it is not affected by mutual phase jitter,
The purpose is to make the circuit configuration of the FIR filter independent of the conversion ratio.

[0025]

In order to achieve this object, a sampling frequency conversion circuit of the present invention comprises a first sampling pulse and a second sampling pulse having frequencies of mutually prime integer ratios m: n (m> n). A sampling pulse and a first signal sampled by the first sampling pulse are input, and the first sampling pulse timing is at a cycle of a frequency of the greatest common divisor of the first sampling pulse and the second sampling pulse. A coefficient generating circuit for outputting a coefficient synchronized with the first signal, an FIR filter for multiplying and summing the first signal and a coefficient output from the coefficient generating circuit, and counting the first sampling pulse by an external input. A first counter that can be stopped and the second counter
Second counter that counts the sampling pulses of, the memory to which the write address is supplied by the first counter and the read address by the second counter, and the (m−n) of the m and n by the first sampling pulse. The timing pulse generating circuit outputs a signal for stopping the counting of the first counter when the value n) is incremented and the increment value exceeds n.

[0026]

According to the present invention, as compared with the conventional sampling frequency conversion circuit, even if the phase jitter occurs in the clock before conversion and the clock after conversion, the signal sum-added by the FIR type filter is written to the memory. Since the address is controlled and the clock is written with the clock before conversion and the data is read out after a certain period of time with the clock after conversion, the sampling frequency conversion can be favorably performed without being affected by mutual phase jitter. Also, FIR
The type filter can be formed with the same circuit configuration without changing the circuit configuration for any conversion ratio.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This embodiment converts the video signal data sampled by the signal of 4fsc into the data of the sampling frequency of 3fsc as described in the section of the prior art. The configuration represented by the above (Formula 3) is used. It was realized.

FIG. 1 is a block diagram of a sampling frequency conversion circuit according to an embodiment of the present invention. Figure 1
In the figure, 56 is an input terminal for digital data of 4 fsc cycle, 148 is a coefficient generating circuit, 50 is a FIR type filter whose coefficient is switched by 4 fsc by the coefficient generating circuit 148 in the circuit configuration as shown in FIG. A random access memory (hereinafter abbreviated as RAM) capable of independently controlling an address and a read address, 52
Is a counter that operates at 4 fsc to generate a write address of the RAM 51, 53 is a counter that generates a read address of the RAM 51, 54 is a timing pulse generation circuit that controls the counter 52 and the counter 53, and 55 is a clock before conversion of 4 fsc. An input terminal, 57 is an input terminal of 3fsc which is a clock after conversion, and 58 is an output terminal of digital data of 3fsc cycle.

The operation of the sampling frequency conversion circuit of this embodiment having the above structure will be described below.

FIR type filter 5 having the circuit configuration shown in FIG.
When data Qn such as 100 in FIG. 4 is input to 0 from the input terminal 56, the latch circuits 122 to 130, to which the clock signal of 4 fsc is supplied, are delayed and parallel-converted by 1 clock of 4 fsc to 101 to 109. The output looks like.

The coefficient generation circuit 148 includes a latch circuit 12
The same clock signal of 4 fsc that is supplied to 2 to 130 is supplied. Then, the coefficient generation circuit 148
From .alpha.0 to .alpha.8 which become the same as the previous coefficient once every four times in the 4 fsc cycle supplied to the multipliers 131 to 139.
(111 to 119) is output. Then, the signals 101 to 109 output from the latch circuits 122 to 130 and the coefficients α0 to α8 (111) output from the coefficient generation circuit 148.
˜119) are multiplied by multipliers 131 to 139, respectively added by adders 140 to 147, and product-sum operations are performed as shown in (Formula 4) to (Formula 7). The sum-of-products calculated signals are interpolated signals (P ₂ , P ₃ , P of 4 fsc cycle).
_{4, P 4 ', P 5} , P 6, P 7, P 7', ···) as a terminal 5
It is output from 9. Output interpolation signals P ₂ , P ₃ , P ₄
As is clear from (Equation 4) to (Equation 7), it is the same as P ₂ , P ₃ , and P ₄ of the conversion output (V) of the conventional example shown in FIG.

[0032]

[Equation 4]

[0033]

[Equation 5]

[0034]

[Equation 6]

[0035]

[Equation 7]

The interpolation signal of 4fsc cycle output from the terminal 59 is written to the address of the write address (63) at the falling timing of the 4fsc clock signal in the RAM 51 which can write and read independently as shown in FIG. . The write address (63) is supplied from the counter 52 which operates at 4fsc. The counter 52 is E
For example, a synchronous binary counter with reset having a function of incrementing the address by one during the period when the NABLE signal (61) is "H" and holding it when it is "L" can be used. The ENABLE signal (61) is created by the timing pulse generation circuit 54. The timing pulse generation circuit 54 uses the W. R
ESET (60), R.I. Create RESET (62). Then, the interpolation signal P ₂ goes to the address “0”,
P ₃ to address “1”, P ₄ to address “2”, P
₄ 'are respectively written to the address "0" (at this time,
The interpolation signal P ₂ written to the address “0” has already been read. ). Since P ₅ write address is held in the "0" address P ₄ 'is written "
The data of address "0" written to 0 "is written from P ₄ 'to P
₅ scratch. The above-mentioned interpolation signals sequentially written to the addresses "0" to "2" are sequentially read corresponding to the read addresses "0" to "2" supplied from the counter 53 operating at 3fsc. The counter 53 can be composed of, for example, a synchronous binary counter with reset. Then, the output signals P ₂ , P ₃ , converted into the 3 fsc cycle,
P ₄ and P ₅ are output from the output terminal 58.

According to the present embodiment configured as described above, 3fsc, for the rising edge of the 4fsc clock,
Even if phase jitter occurs such that the rising edge of the fsc clock fluctuates back and forth on the time axis, the interpolation signal is stored in the RAM 51.
To W. The write address (63) is sequentially written at the falling timing of 4 fsc from the time when the RESET (60) changes from “L” to “H”, and the R.R. RESET
Since (62) is sequentially read at the leading edge of the read address (64) from the time when it is not affected by the phase jitter changed from "L" to "H", the sampling frequency is converted without being affected by the phase jitter. be able to. Also, RA
The size of M51 may be the minimum necessary to absorb the phase jitter because the sequential write and read operations are performed as described above. Moreover, if the conversion ratio changes, the RAM 51
This can be handled by controlling the write address of (1) by the timing pulse generation circuit 54, and can be performed without changing the circuit of the FIR filter 50.

[0038]

As is apparent from the above description, according to the present invention, the first sampling pulse, the second sampling pulse, and the first sampling pulse having the frequencies of mutually prime integer ratios m: n (m> n) are used. When the first signal sampled by the sampling pulse is input, the coefficient synchronized with the timing of the first sampling pulse is output in the cycle of the frequency of the greatest common divisor of the first sampling pulse and the second sampling pulse. And a FI for multiplying and adding the first signal and the coefficient output from the coefficient generating circuit.
The R-type filter, the first counter that counts the first sampling pulse and can be stopped by an external input, the second counter that counts the second sampling pulse, and the write address by the first counter The memory to which the read address is supplied by the second counter and the (m−n) value of m and n are incremented by the first sampling pulse, and when the increment value exceeds n, the first
And a timing pulse generation circuit for outputting a signal for stopping the counting of the counter, and the output signal of the FIR filter is written to the memory at the write address and read at the read address, so that the conversion of the sampling frequency is affected by mutual phase jitter. You can do it well without receiving it. Further, the FIR type filter can be implemented with the same circuit configuration without changing the circuit configuration in the case of an arbitrary integer ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sampling frequency conversion circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing an example of an FIR filter 50 according to the same embodiment.

FIG. 4 is a timing diagram for explaining the operation of FIG.

FIG. 5 is a waveform diagram showing an example of an input signal.

FIG. 6 is a waveform diagram showing an example of impulse response.

FIG. 7 is a waveform diagram showing the relationship between input and output signals.

FIG. 8 is a waveform diagram showing the relationship between input and output signals.

FIG. 9 is a block diagram showing a configuration of a conventional sampling frequency conversion circuit.

FIG. 10 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 50 FIR type filter 51 RAM 52 First counter 53 Second counter 54 Timing pulse generating circuit 55 First sampling pulse input terminal 56 First signal input terminal 57 Second sampling pulse input terminal 58 Second Signal output terminal 148 Coefficient generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/14 Z 5/92

Claims (1)

[Claims] 1. A first sampling pulse, a second sampling pulse, and a first signal sampled by the first sampling pulse, which have frequencies of mutually prime integer ratio m: n (m> n), are input. A coefficient generating circuit for outputting a coefficient in synchronization with the timing of the first sampling pulse at a frequency cycle of the greatest common divisor of the first sampling pulse and the second sampling pulse, the first signal and the coefficient An FIR type filter for multiplying and summing the coefficients output from the generation circuit, a first counter that counts the first sampling pulse and can be stopped by an external input, and a second counter that counts the second sampling pulse. And a write address is supplied by the first counter and a read address is supplied by the second counter. When, at the first sampling pulse the m, the n (m-
n) is incremented, and a timing pulse generation circuit that outputs a signal for stopping the counting of the first counter when the increment value exceeds n is provided, and the output signal of the FIR filter is output to the memory. A sampling frequency conversion circuit, characterized in that writing at the write address and reading at the read address obtain an output signal of the second sampling pulse period.