JPS63300616A - Digital interpolation device - Google Patents

Abstract

PURPOSE:To obtain the interpolation circuit constitution without spurious offset by storing input data at the sampling period to a 1st register, switching the selector to store the input data into a 2nd register to offer a new output data. CONSTITUTION:A multiple of 2<->N of a difference between a digital input VIN sampled at a sampling period T1 and a digital input retarded by T1 stored in a register 1 is calculated by a shift register A and stored. The data in the shift register A is read for each T2, added to the data in the register 2 and stored again in the register 2 to be a digital output VOUT sampled by a sampling period T2. On the other hand, the digital input VIN is stored in the register 1 for each T1 and the selector B is switched, stored in the register 2 to offer the digital output VOUT.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention converts a digital signal with a low sampling frequency into a digital signal with a high sampling frequency, and further removes high-frequency spurious signals generated at that time. The present invention relates to a digital interpolator that also has a function, and in particular to a digital interpolator whose impulse response is a triangular response.

[Prior Art] Generally, this type of digital interpolator has a configuration as shown in FIG. 2A. For example, the sampling frequency is 8K
The sampling frequency for one digital word of H2 is 32K.
When converting to a Hz digital signal, first, the zero insertion circuit 1 in Figure 2A outputs the input data as it is once every 125 microseconds, and then gives zero as an interpolated value every 31.25 microseconds. . This situation is shown in (1) in Figure 2B.
Shown in (2). At this time, if the frequency of the input signal is limited as shown in (1) of Figure 2C, the spectrum of the signal after interpolation is 8KH as shown in (2) of Figure 2C.
There is one spurious word centered on an integer multiple of z.

Therefore, in order to suppress this spurious signal, the second
As shown in Figure A, it is necessary to remove signals of 4KH2 or higher using a low-pass filter 2 with a band of 4KH2. If this low-pass filter 2 is an ideal low-pass filter, the output waveform of the digital interpolator will be an ideal interpolated waveform as shown in (3) of FIG. 2B. Further, the spectrum of the output signal completely matches the spectrum of the input signal, as shown in (3) of FIG. 2C.

However, in reality, an ideal low-pass filter like the one used in the above discussion does not exist, and some approximation must be applied. Therefore, a rectangular response filter whose impulse response is a rectangular response is often used, and its transfer function is given by the following equation.

However, here N is the upsampling rate, and in the example above, 32/8 = 4, and the frequency response of this filter is the first
This can be obtained by substituting Z=e2πjrzTs (f is the frequency and fs is the sampling frequency) in the equation. By performing the substitution, we obtain the following equation.

Therefore, the amplitude characteristic is as shown in the following equation.As is clear from the third equation, the rectangular response filter has a zero point at f=-f-/N (k=1.2...N). Therefore, a sharp attenuation factor can be obtained near the center frequency of the spurious signal appearing in the signal spectrum after interpolation by the above-mentioned zero insertion, which is effective in removing the spurious signal.

When it is desired to further suppress spurious signals, a rectangular response filter is connected in two stages in cascade, and its transfer function is given by the following equation.

As is clear from equation 4, this filter has a triangular impulse response and is called a triangular response filter. This triangular response filter is often used in general interpolators.

A method for implementing an interpolator using a triangular response filter will be described below. First, it can be seen from the transfer number shown in the fourth equation that the triangular response filter can be directly configured as an FIR.

The interpolator therefore becomes as shown in FIG. Next, we will consider another method of implementing an interpolator using triangular responses. In general, the impulse response is h (i) gui=o, 1.
2. ...2N-2)
(n), its output signal Y (n) is given by the following equation.

On the other hand, the signal X (
Noting that n) is zero 8 times (N-1) times,
The signal sequence is Xn (k) (k=o.

1.2. ...N-1) can be written as ``Sureha''. Therefore, if h(i) in the fifth equation is a triangular coefficient (coefficient of a triangular response filter) of length 2N-1, then 1/N,
2/N, ..., (N-1)/N.

1, (N+1)/N, ..., 2/N, 1/N
If so, the fifth equation can be written as the following equation.

In the seventh equation, 1 (when = 0, Yn (0) =X (n
-1), so use this Yn (0) and rewrite it as the following equation.

If the relationship between the input and output of the interpolator shown in equation 8 is directly realized, it will be as shown in FIG. 4. Here, REGl and REG2 are registers each for realizing a one-sample delay,
It is assumed that REGI is synchronized with the sampling period of the input (word), and REG2 is synchronized with the sampling period of the output signal.

Further, 1/N indicates a function to multiply data by 1/N.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the interpolator shown in FIG.
Since a delay device is required to be as long as the filter, and a multiplier is also required, there is a problem in that the chip area becomes extremely large when integrated.

On the other hand, the interpolator shown in FIG. 4 has a problem in that it remains as a spurious offset forever unless some erroneous data is input to REG2 and a reset is applied.

[Means and operations for solving the problem] The digital interpolator of the present invention inputs a digital signal sampled at an arbitrary sampling period T1, and receives a digital signal sampled at an arbitrary sampling period T1, and calculates the sampling period 2 to 8 times (N In a digital interpolator that outputs a digital signal sampled and linked at a sampling period T2 (T2=2-NT1) (where T2 is an integer), a first interpolator stores data obtained by delaying the digital input signal by one sampling period (T1). The difference between the input data and the data in the first register is 2.
- a shift register for multiplying by N, a second register for storing output data, and a selector; the data in the shift register and the output stored in the second register are delayed by one sampling period (T2); The sum of the data is stored in the second register as new output data,
Further, when the input data is stored in the first register at the sampling period T+, the selector is switched at the same time in the sampling cycle month T1, and the input data is stored in the second register. and the data becomes new output data.

Therefore, in contrast to the above-mentioned conventional interpolators, the present invention provides a circuit configuration of an interpolator through integration that can obtain an output signal without generating spurious offsets and without interrupting the interpolation operation. In the circuit shown in Figure 4, there is a timing to rewrite the data stored in the register in the feedback loop, that is, REG2, to new data unrelated to this q- data, and this new data becomes the output of the interpolator. It has an original content of making it a value that can be obtained.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, VIN indicates the input terminal of the digital signal sampled at the sampling period T1, VOLIT indicates the output terminal of the digital signal sampled at the sampling period T2 (T2 = 2-"T1), and REGI and REG2 are the registers, respectively. 1, register 2,
A indicates a shift register, B a selector, C an adder, and D a subtracter.

The shift register calculates and stores 2-N times the difference between the digital input sampled at the sampling period T1 and the digital input delayed by T1 stored in the register 1. The data in this shift register is read out every T2, added to the data in register 2, and stored in register 2 again, resulting in a digital output sampled at sampling period T2. On the other hand, the digital input is stored in register 1 every T1, and at the same time the selector is switched, and is also stored in register 2, becoming a digital output.

[Effects of the Invention] As explained above, the present invention has the effect of being able to rewrite the data stored in the register in the feedback loop with new data unrelated to this data, and no spurious offset occurs. .

The newly rewritten data at this time can be a value that can be the output of the interpolator, rather than completely meaningless data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digital interpolator according to an embodiment of the present invention, FIG. 2A is a block diagram showing the configuration of a conventional example, and FIG. 2B (
1) to (3) are waveform diagrams of the main signals in an ideal state of the conventional example, Figures 2C (1) to (3) are frequency characteristic diagrams explaining the general characteristics of the interpolator, and Figures 3 to 3. FIG. 4 is a block diagram showing each conventional example. V4N...Input terminal, VOLIT...Output terminal, REGI...Register 1, REG2...Register 2, A...Shift register, B...Selector, C...Adder, D...Subtraction vessel.

Claims (1)

[Claims] When a digital signal sampled at an arbitrary sampling period T_1 is input, the sampling period T is 2^-^N times (N is an integer) the sampling period of the input signal.
In a digital interpolator that outputs a digital signal sampled at _2 (T_2=2^-^NT_1), the digital input signal is
_1) a first register storing delayed data;
The difference between the input data and the data in the first register is 2^
- A shift register that multiplies by N, a second register that stores output data, and a selector, and the data in the shift register and the data stored in the second register are delayed by one sampling period (T_2). The sum with the output data is stored in the second register as new output data, and the sampling period T_1 is further stored in the first register.
At the same time as the input data is stored, the selector is switched in synchronization with the sampling period T_1, the input data is stored in the second register, and the data becomes new output data. Digital interpolator.