JP2012085177A - Decimator circuit, and operation method for decimator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high accuracy decimator circuit that has a small circuit scale and operates fast.SOLUTION: The decimator circuit includes a plurality of multiply-accumulate circuits 1 and a coefficient memory 2 for giving coefficients of multiplication to the plurality of multiply-accumulate circuits respectively. The plurality of multiply-accumulate circuits each operate in a sampling period of an input digital signal Xi, and include a multiplier 11 for multiplying the input digital signal by the coefficient read out from the coefficient memory and an accumulator 15 for accumulating the operation result of the multiplier. The accumulators respectively included in the plurality of multiply-accumulate circuits are cascade-connected together. At every M (M is an integer of 2 or greater) accumulations, the accumulator connected in the first stage is initialized to a fixed value and the accumulators except of the first stage are to an output signal of the accumulator connected in the preceding stage, and an output signal of the accumulator of the last stage provides a thinned-out output signal having M times as long a sampling period as the input digital signal.

Description

  The present invention relates to a decimator circuit and a calculation method of the decimator circuit. In particular, the present invention relates to a decimator circuit having a built-in decimation filter that thins out and outputs a sampling frequency of an input digital signal to a lower sampling frequency and removes high-frequency noise exceeding the Nyquist frequency, and an operation method of the decimator circuit.

  When it is necessary to transfer digital signals directly between devices with different sampling frequencies, or when converting a signal sequence encoded by delta modulation into a PCM (Pulse Code Modulation) code, the sample rate must be changed. There is a case. In such a case, a decimator that lowers the sampling frequency and an interpolator that raises the sampling frequency are the basic functions of multirate signal processing. Here, the decimator will be further described.

When a signal series obtained by sampling the analog signal xa (t) at the period T is x (nT), Expression (1) is established.
x (nT) = xa (nT) Formula (1)
Here, if a signal sequence sampled with a new period T ′ = MT (M is a natural number) is y (nT ′), Expression (2) is established. That is, y is a signal sequence obtained by thinning out x (nT) at a rate of one for every M samples.
y (nT ′) = x (nMT) Equation (2)

On the other hand, when a high frequency component exceeding f = 1 / (2MT) exists in xa from the sampling theorem, it becomes aliasing noise and degrades the signal quality of the signal sequence y. Therefore, before performing the thinning process, it is necessary to perform the thinning after the band is limited by the LPF characteristic filter (decimation filter) H (f) as shown in Expression (3). M is called decimation ratio.
H (f) = 1: f ≦ 1 / (2MT)
0: f> 1 / (2MT) Formula (3)

  A decimator circuit is a circuit that converts a sampling rate of an input digital signal into a digital output signal having a lower sampling rate and outputs the digital output signal. The decimator circuit uses the sampling theorem to remove signals with a frequency higher than the Nyquist frequency from the input digital signal because a signal with a frequency higher than the Nyquist frequency [f = 1 / (2MT)] degrades the quality of the output signal. A decimation filter having an LPF (Low Pass Filter) characteristic is used.

  FIG. 8 shows a circuit block diagram of a decimator provided with a decimation filter having a polyphase configuration described in Patent Document 1 as a prior art. The configuration of this decimation filter will be described with reference to FIG. The conventional decimation filter shown in FIG. 8 includes a plurality of delay elements 21, a plurality of downsamplers 22, a plurality of filters 23, and an adder 24.

The delay element 21 is an element that delays the input signal by one sampling period, and the downsampler 22 is a circuit that downsamples the input signal to a decimation ratio M. Each of the filters 23 forms part of a decimation filter having a polyphase configuration, and is a filter in which filter coefficients of the decimation filter are selected every N. For example, if M = 3, N = 9, and the filter tap coefficient is αi, the filter 23 is represented by equations (4) to (6), respectively.
D0 (z) = α0 + α3 * Z ⁻¹ + α6 * Z- ² Formula (4)
D1 (z) = α1 + α4 * Z ⁻¹ + α7 * Z- ² formula (5)
D2 (z) = α2 + α5 * Z ⁻¹ + α8 * Z ⁻² formula (6)

  As a result, the output of the adder 24 has a 9th order FIR (Finite impulse response) filter characteristic. When implemented with a circuit, nine multipliers and seven adders are required. As described above, since the number of multipliers is required for the order of the filter, there is a problem that the circuit scale and the power consumption increase in order to realize a higher-order filter.

  On the other hand, Patent Document 1 discloses a decimation filter that further reduces the circuit scale. FIG. 9 shows a circuit block diagram of a conventional decimation filter in which the circuit scale described in Patent Document 1 is reduced. The conventional decimation filter shown in FIG. 9 includes a buffer memory 31, a coefficient memory 32, an arithmetic unit 33, and a timing control circuit 34. A signal Sin sampled at a first sampling frequency is converted into a signal Sot having a lower sampling frequency. It is to convert to.

  The sample information (signal Sin) stored in the buffer memory 31 is read in synchronization with the timing signal given by the timing control circuit 34 and is multiplied by the multiplier 331 by the coefficient value stored in the coefficient memory 32. This result is accumulated in an accumulator (integrator or accumulator) composed of an adder 332 and a register (delay element) 333, and is output when the integration is completed for N taps of the filter. After clearing to zero, integration and integration are repeated again.

  In the decimation filter of FIG. 9, a buffer memory 31 that temporarily stores sample information (signal Sin) and a timing control circuit 34 that performs address management of the buffer memory and the like are newly required. Compared with the provided decimation filter having the polyphase configuration shown in FIG. 8, the circuit amount is reduced by using one multiplier in a time division manner.

  However, since the product-sum operation for N taps needs to be completed within the time of sampling cycle T × decimation ratio M, when the number of taps N is large, the internal calculation is performed earlier than the sampling clock. There is a need. For example, if N = 10, M = 3, and sampling is 30 MHz, the multiplier and accumulator must be operated at 100 MHz. Patent Document 1 describes that the decimation filter shown in FIG. 9 is suitable for filtering a low-frequency signal Sin of 1 MHz or less, for example.

JP 2008-219560 A

  The following analysis is given by the present invention. That is, when a decimation filter having a polyphase structure is used as in the conventional example shown in FIG.

  Further, in the decimation filter disclosed in Patent Document 1 shown in FIG. 9, a clock signal having a high frequency equal to or higher than the sampling frequency of the input digital signal is used, and the order of the filter (the number of taps) is divided in time within the sampling period of the input digital signal. (Min) multiplication and accumulation (integration) must be completed. Therefore, it is impossible to realize when the sampling rate is high, the decimation ratio is relatively small, and the filter order N is large.

  In view of the above-mentioned problems of the prior art, it is desired to realize a decimator circuit that can be equipped with a decimation filter of any order, operates at high speed, and suppresses an increase in circuit scale.

  According to a first aspect of the present invention, a plurality of product-sum operation circuits, and a coefficient memory that gives a coefficient of product operation to each of the plurality of product-sum operation circuits, are provided. Each of which operates in the sampling period of the input digital signal, multiplies the input digital signal and the coefficient read from the coefficient memory, and an accumulator that accumulates the operation result of the multiplier. The accumulators included in each of the plurality of product-sum operation circuits are cascade-connected to each other, and each time accumulating M times (M is an integer of 2 or more), the accumulator connected to the first stage is The accumulators other than the first stage are initially set to a fixed value by the output signal of the accumulator connected to the previous stage, and the sampling period of the input digital signal is thinned M times by the output signal of the last stage accumulator. Decimator times to obtain the output signal There is provided.

  According to a second aspect of the present invention, each of the present invention includes a plurality of product-sum operation circuits, each having a multiplier and an accumulator, in which an input and an output of the accumulator are cascade-connected to each other. An decimator circuit calculation method for outputting an output signal obtained by thinning the sampling period of an input digital signal by M times (M is an integer of 2 or more), each included in the plurality of product-sum calculation circuits and connected in cascade A first step of initializing the first stage accumulators among fixed accumulators with a fixed value and initializing accumulators other than the first stage with output values of the previous stage accumulators, A process of multiplying a predetermined coefficient by the input digital signal by a multiplier included in a plurality of product-sum operation circuits and adding the multiplication result to an initial setting value of the accumulator is performed in the sampling period of the input digital signal. Synchronized M times A second step, and the first step and the second step are repeated in accordance with a cycle of the thinned output signal, and the cascade connection is performed each time the second step is completed. Among the accumulators, there is provided a method for calculating a decimator circuit that obtains an output signal obtained by thinning the sampling period of the input digital signal by M times according to the output value of the accumulator at the final stage.

  According to each aspect of the present invention, a decimator circuit that operates at a sampling frequency of an input digital signal and suppresses an increase in circuit scale can be realized. Further, a decimation filter having an arbitrary order can be realized depending on the value of M and the number of product-sum operation circuits connected in cascade.

1 is a circuit block diagram showing an example of a decimator circuit according to a first embodiment of the present invention. 1 is a circuit block diagram of a general decimator circuit according to a first embodiment of the present invention. It is a process flowchart which shows operation | movement of the decimator circuit by the 1st Embodiment of this invention. It is a figure which shows the state transition for every sampling period about the decimator circuit by Example 1. FIG. It is a circuit block diagram of the decimator circuit by the 2nd Embodiment of this invention. It is a circuit block diagram of the decimator circuit by the 3rd Embodiment of this invention. It is a figure which shows the state transition for every sampling period about the decimator circuit by Example 2. FIG. 10 is a circuit block diagram of a decimator circuit including a conventional decimation filter having a polyphase configuration described in Patent Document 1. FIG. 10 is a circuit block diagram of a conventional decimation filter described in Patent Document 1. FIG.

  Prior to detailed description of specific embodiments, an outline of embodiments of the present invention will be described. Note that the reference numerals of the drawings attached to the description of the outline are merely examples for helping understanding, and are not intended to be limited to the illustrated modes.

  As illustrated in FIG. 1, FIG. 2, FIG. 5, and FIG. 6, the decimator circuit (10, 10A, 10B, 10C) of the present invention operates at the sampling period of the input digital signal Xi. A plurality of product-sum operation circuits (1) having a multiplier 11 that multiplies Xi and a coefficient Cj read from the coefficient memory (2, 2B, 2C), and an accumulator 15 that accumulates the operation results of the multiplier. -A, 1-b, 1-l, 1C-a, 1C-b). The accumulators 15 included in each of the plurality of product-sum operation circuits are cascade-connected to each other [0, da, db, d (l−1), cascade connection using dl signals]. Each time these accumulators 15 accumulate M times, the accumulator connected to the first stage is a fixed value (in FIG. 1, FIG. 2, FIG. 5 and FIG. The accumulators other than the first stage are initialized by the output signals (da, d (l-1), etc.) of the accumulator connected to the previous stage. Then, an output signal obtained by thinning the sampling period of the input digital signal Xi M times is obtained from the output signal of the accumulator at the final stage (db in FIGS. 1, 5, 6 and dl in FIG. 2).

According to the above configuration, since multiplication and accumulation can be performed in parallel by a plurality of product-sum operation circuits, it is not necessary to perform multiplication and accumulation faster than the sampling period of the input digital signal. Operation is possible. In addition, since multiplication and accumulation M times are repeated using the same product-sum operation circuit in accordance with the sampling period of the input digital signal, the number of product-sum operation circuits can be suppressed to a minimum number. If the order of the decimation filter is N and the decimation ratio is M, the number of product-sum operation circuits can be suppressed to L by Equation (7).
L = <N / M> Formula (7)
(However, <X> is rounded up to X.)

  Further, it is not necessary to provide a buffer memory (31 in FIG. 9) for storing an input digital signal as in Patent Document 1, and it is not necessary to control the address of the buffer memory.

  The decimator circuit calculation method according to the present invention includes an accumulator in the first stage among the accumulators that are included in each of a plurality of product-sum calculation circuits and cascade-connected as shown in FIG. A first step of initializing with a fixed value and initializing an accumulator other than the first stage with an output value of a previous stage accumulator (initial setting at step ST1 with an output value obtained at step ST5); The input digital signal Xi is sampled by multiplying a predetermined coefficient (Cj, etc.) and the input digital signal Xi by a multiplier included in the product-sum operation circuit, and adding the multiplication result to the initial setting value of the accumulator. A second step (steps ST2 to ST4) that is repeated M times in synchronization with the cycle, and is repeated according to the cycle of the output signal obtained by thinning the first step and the second step. Is completed, an output signal obtained by thinning the sampling period of the input digital signal by M times is obtained from the output value of the accumulator at the last stage among the cascaded accumulators (step ST5). .

Further, in the present invention, the following modes are possible.
[Mode 1] As in the first aspect.
[Mode 2] The accumulator 15 receives the register 13, the initial set value, and the output signal of the register 13 as shown in FIG. 1, FIG. 2, FIG. a selector 14 that selects and outputs one of them by en; and an adder 12 that adds the output signal of the selector 14 and the output signal of the multiplier 11. The register 13 stores the addition result of the adder 12. It is preferable to do.
[Mode 3] It is preferable to further include timing control circuits (3, 3B, 3C) for controlling the reading of the coefficient Cj from the coefficient memory 2 in accordance with the sampling period of the input digital signal Xi and generating the timing control signal en. .
[Mode 4] A down-rate converter 4 that holds the output signal of the final stage accumulator (db in FIGS. 1, 5, 6 and dl in FIG. 2) and updates it every M accumulations is further provided. It is preferable to provide.
[Mode 5] The number of a plurality of product-sum operation circuits (1-a, 1-b: 1C-a, 1C-b) connected in cascade (as shown in FIG. 5 to FIG. 7 as an example) is expressed as L (L Is a decimator circuit (10B, 10C) in which L cascaded product-sum operation circuits function as a decimation filter as an L * M-th order FIR filter, Furthermore, when L is an even number and L * M taps of the FIR filter are arranged in time series, k is an arbitrary integer greater than or equal to 0 and less than (L / 2) * M (L / 2) * M The coefficient value of the -k-th tap is equal to the coefficient value of the (L / 2) * M + k + 1-th tap, and the coefficient memory (2B, 2C) is the (L / 2) * M-kth of the FIR filter. Tap coefficient and (L / 2) * M + k + 1-th tap coefficient as a common value Preferably stores one address as the same data. That is, when the filter tap coefficients of the decimation filter are configured symmetrically with an early tap and a later tap with respect to the center when the taps are arranged in time series, the coefficient memory (2B, 2C) ) Of the tap coefficients stored in (1), the tap coefficient of only one of the taps at the early time and the tap at the later time is stored, and the number of tap coefficients stored in the coefficient memory (2B, 2C) is halved. The memory capacity can be halved.
[Mode 6] The coefficient memory 2B (as shown in an example in FIG. 5) includes the L / 2 products in the preceding stage among the L cascade-connected product-sum operation circuits (1-a, 1-b). Dual that can simultaneously read out the coefficients used by the sum operation circuit 1-a and the coefficients used by the remaining L / 2 product-sum operation circuits 1-b by designating different addresses. The port memory is preferably 2B.
[Mode 7] The coefficient memory 2C reads L coefficient data in parallel (as shown in an example in FIG. 6), and the L product-sum operation circuits respectively read L coefficient data read from the coefficient memory 2C. Of these, it is preferable to further include a coefficient selector 16 which inputs two corresponding coefficient data and gives one selected coefficient data as coefficient data of the multiplier.
[Mode 8] As in the second aspect.
[Mode 9] When the number of a plurality of product-sum operation circuits is L (L is an integer of 2 or more), the L product-sum operation circuits function as a decimation filter as an L * M-th order FIR filter. In the circuit, the predetermined coefficient is preferably a coefficient of each tap of the L * M-th order FIR filter. The coefficient may be given to each multiplier 11 by any means, but preferably the coefficient may be generated by the coefficient memories 2, 2B, 2C.

  The outline of the embodiment has been described above, and a more specific embodiment will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit block diagram showing an example of a decimator circuit according to the first embodiment. The decimator circuit 10 of FIG. 1 includes two product-sum operation circuits 1-a and 1-b, a coefficient memory 2, a timing control circuit 3, and a down-rate converter 4. Since the product-sum operation circuits 1-a and 1-b have the same internal circuit configuration, only the internal configuration of the product-sum operation circuit 1-a is shown as a representative. The internal configuration is not shown. In the product-sum operation circuits 1-a and 1-b, the connection of the external terminals is slightly different, but the difference in the connection will be described later. The product-sum operation circuit 1-a includes a multiplier 11 and an accumulator 15. The multiplier 11 calculates the product of the input digital signal Xi input from the input terminal In and the coefficient Cj read from the coefficient memory 2. The accumulator 15 accumulates and adds the multiplication results of the multiplier 11.

  Further, the accumulator 15 includes an adder 12, a register 13, and a selector 14. The adder 12 adds the multiplication result of the multiplier 11 to the output value of the selector 14. The register 13 holds the calculation result of the adder 12 in synchronization with the calculation of the adder 12. The selector 14 selects and outputs either the initial setting value given from the outside of the product-sum operation circuit or the operation result held by the register based on the logic level of the timing control signal en output from the timing control circuit 3. To do.

  Here, since the sampling frequency of the digital signal output from the output terminal Out is 1 / M (M is an integer of 2 or more) with respect to the sampling frequency of the input digital signal Xi input from the input terminal In, the decimator circuit The decimation ratio of 10 is M. Therefore, the accumulator 15 repeats accumulation M times in synchronization with the sampling period of the input digital signal Xi, and outputs the accumulation result stored in the register 13 to the outside each time the accumulation is repeated M times. At the same time, the selector 14 takes in the initial setting value from the outside and initializes it. These operations are controlled by a timing control signal en.

  An input digital signal Xi input from the input terminal In and a timing control signal en output from the timing control circuit 3 are commonly connected to the product-sum operation circuits 1-a and 1-b. The coefficient data given from the coefficient memory 2 and the initial set value given to the selector 14 are given different values depending on the product-sum operation circuits 1-a and 1-b. The product-sum operation circuit 1-a is given a fixed value 0 as an initial setting value, and the product-sum operation circuit 1-b receives the output signal da of the register 13 included in the product-sum operation circuit 1-a as an initial setting value. Given.

  The output signal db of the register 13, not shown in the product-sum operation circuit 1-b, is connected to the down-rate converter 4. That is, the product-sum operation circuit 1-a and the accumulator 15 of the product-sum operation circuit 1-b are cascade-connected to each other via the output signal da of the product-sum operation circuit 1-a. A fixed value 0 is given as an initial setting value to the first stage product-sum operation circuit 1-a, and the product-sum operation circuit 1-b other than the first stage accumulates the previous stage product-sum operation circuit 1-a. The output signal da of the device 15 is given as an initial set value. The output signal db of the product-sum operation circuit 1-b at the final stage is output as a signal from which the high-frequency component is removed by the decimation filter as the output signal of the entire decimator circuit 10 through the down-rate converter 4 and the sampling rate is thinned out. The

  The coefficient memory 2 stores the coefficient of each tap of the FIR filter serving as a decimation filter, and the multiplier 11 of each of the product-sum calculation circuits 1-a and 1-b performs calculation of each tap on the input digital signal Xi. The coefficient of each tap is output according to the timing. The memory address ADR is given by the timing control circuit 3, updated for each sampling clock of the input digital signal Xi, and the coefficient of each tap is read. Note that the memory address ADR is repeatedly specified every time M times, and the same memory address ADR is designated, and the reading of the coefficient of each tap is repeated.

  The down-rate converter 4 holds the output digital signal db that is output every time the accumulator of the product-sum operation circuit 1-b accumulates M times during the sampling period of the output signal. The timing control signal en output from the timing control circuit 3 is supplied to the down-rate converter 4 and controls the capture of the output digital signal db and the retention of data. For example, the down-rate converter can be realized by using a data flip-flop that takes in data at the rising edge of the timing control signal en.

  The timing control circuit 3 reads out the coefficients from the coefficient memory 2, controls the selectors 14 of the product-sum operation circuits 1-a and 1-b, and updates and holds data of the down-rate converter. The timing control circuit 3 outputs the memory address ADR and the timing control signal en in synchronization with the sampling period of the input digital signal Xi, and the operation repeats the same operation every M times that is the decimation ratio.

  FIG. 2 is a more general circuit block diagram of the decimation circuit according to the first embodiment. In FIG. 2, L (1 is an integer greater than or equal to 2) product-sum operation circuits 1-a and 1-b to 1-l are provided. The input digital signal Xi and the timing control signal en are commonly connected to each product-sum operation circuit 1.

  The coefficient memory 2 gives independent coefficients to the L product-sum operation circuits 1. Further, a fixed value 0 is connected as an initial setting signal of the accumulator 15 of the first stage product-sum operation circuit 1-a.

  The output signal da of the first-stage accumulator 15 is connected as an initial setting signal to the second-stage product-sum operation circuit 1-b, and the output signal db of the second-stage product-sum operation circuit 1-b is An initial setting signal is connected to a third-stage product-sum operation circuit (not shown). The output signal d (l−1) of the L−1 product-sum operation circuit (not shown) is connected to the initial setting signal of the L-th product-sum operation circuit 1-1, and the final stage The output signal dl of the product-sum operation circuit 1-l is connected to the down-rate converter 4.

  That is, the output signal of the accumulator 15 of the L product-sum operation circuits 1 is used as the initial setting signal of the next product-sum operation circuit 1 and the accumulators 15 of the L product-sum operation circuits 1 are cascaded. Has been. Then, a fixed value (a fixed value 0 as an example in FIG. 2) is given to the initial setting signal of the first-stage product-sum operation circuit 1-a, and the output signal dl of the last-stage product-sum operation circuit 1-1 is reduced. It is output as a decimator output signal via the rate converter 4.

  The number L of product-sum operation circuits is determined by the equation (7) already described based on the order N of the FIR filter serving as a decimation filter and the decimation ratio M. Further, depending on the value of the decimation ratio M, the timing control circuit 3 changes in which period of the input digital signal Xi the timing control signal en is activated once. In the coefficient memory 2, the number of addresses used for M times of reading is determined by the value of the decimation ratio M. The other configuration is basically the same as that in FIG.

  FIG. 3 is a process flowchart showing the operation of the decimator circuit according to the first embodiment. In step ST1, each product-sum operation circuit is initialized. Among the cascaded product-sum operation circuits, the accumulator of the first-stage product-sum operation circuit is initially set to a fixed value, and the accumulators of the product-sum operation circuits other than the first stage are the same as the accumulator of the previous stage. It is initialized by the output signal and stored in each accumulator register.

  In step ST2, the input digital signal Xi and the coefficient of the tap read from the coefficient memory are multiplied by the multiplier of each product-sum operation circuit. When L product-sum operation circuits are provided, L tap coefficients and the input digital signal Xi are multiplied in parallel.

  In step ST3, the multiplication result of the multiplier is added to the data stored in the register by the accumulator of each product-sum operation circuit. This multiplication of step ST2 and the accumulation of step ST3 are repeated M times which is a decimation ratio (step ST4). If M multiplications and accumulations have been performed, the process proceeds to step ST5, where each product-sum operation circuit outputs an accumulation result. Of the cascaded product-sum operation circuits, the accumulation result of the last-stage product-sum operation circuit is the operation result by the decimator filter. When step ST5 ends, the process returns to step ST1 to repeat the decimator process.

[Second Embodiment]
When an FIR filter is used as a decimation filter, the coefficient of each tap of the normal FIR filter is the median value of the time with the coefficient of the tap with the earlier time and the coefficient of the tap with the later time when the taps are arranged in time series. In many cases, the tap coefficient is symmetric with respect to. In such a case, as the coefficients stored in the coefficient memory, a common coefficient can be used between the coefficient of the tap with the earlier time and the coefficient of the tap with the later time. Therefore, the number of coefficients stored in the coefficient memory can be halved.

  That is, when the number L of product-sum calculation circuits of the FIR filter is an even number and the decimation ratio M, and the number of taps L * M of the FIR filter is arranged in time series of the input digital signal, k is 0 or more and (L / 2 ) As an arbitrary integer less than * M, the coefficient value of the (L / 2) * M−k-th tap is equal to the coefficient value of the (L / 2) * M + k + 1-th tap, respectively, and the coefficient memory stores it. The number of coefficients can be halved.

  However, some device is required to read out the coefficients from the coefficient memory. For example, the coefficient memory is a dual-port memory, and among the coefficients of each tap of the FIR filter, the address for reading the coefficient of the tap with the earlier time and the address for reading the coefficient of the tap with the later time are independently parallel from one coefficient memory. Thus, a plurality of addresses can be designated and read out.

  Here, the operation principle of the second embodiment will be described. Assume that the number L of product-sum operation circuits of the decimation filter incorporated in the decimator circuit is L = 4, the decimation ratio M = 4, and the number of taps (order) of the FIR filter N = 16.

The output value of the decimation filter is a total value obtained by accumulating the multiplication results in the first to fourth product-sum operation circuits. Except for the initial value given from the previous product-sum operation circuit, the sums of multiplications newly added by the first to fourth product-sum operation circuits are denoted by S1, S2, S3, and S4, respectively. When the value is D0 (z), it can be expressed by the following formulas (8) to (12).
Do (z) = S1 + S2 + S3 + S4 Formula (8)
S1 = x0 * c0 + x1 * c1 + x2 * c2 + x3 * c3 Formula (9)
S2 = x4 * c4 + x5 * c5 + x6 * c6 + x7 * c7 Formula (10)
S3 = x8 * c8 + x9 * c9 + x10 * c10 + x11 * c11 Formula (11)
S4 = x12 * c12 + x13 * c13 + x14 * c14 + x15 * c15 Formula (12)

  Here, x0 is the value of the input digital signal input at the earliest time, and x15 is the value of the input digital signal input at the latest time. C0 to c15 are tap coefficients of the decimation filter. Assume that the tap coefficients of the decimation filter are symmetrical with respect to the digital signal input in time series.

  That is, as described in [Mode 5], when 16 taps from c0 to c15 are arranged in time series, k is set to an arbitrary integer not less than 0 and less than (L / 2) * M (L / 2) The coefficient value of the M-kth tap is equal to the coefficient value of the (L / 2) * M + k + 1-th tap. When rewriting by substituting L = 4 and M = 4, k is set to an arbitrary integer from 0 to 7 for the coefficient of the first tap coefficient c0 to the coefficient of the 16th tap c15. The coefficient of the 8−kth tap is equal to the coefficient of the 9 + kth tap. More specifically, the coefficients of each tap are c8 = c7, c9 = c6, c10 = c5, c11 = c4, c12 = c3, c13 = c2, c14 = c1, and c15 = c0.

Therefore, the above equations (11) and (12) can be rewritten as the following equations (13) and (14).
S3 = x8 * c7 + x9 * c6 + x10 * c5 + x11 * c4 Formula (13)
S4 = x12 * c3 + x13 * c2 + x14 * c1 + x15 * c0 Formula (14)

In addition, although the first to fourth product-sum operation circuits perform the operations of S1 to S4 are different from each other, the same time is taken while the first product-sum operation circuit performs the operation of S1. Summarizing the operations performed by the second to fourth product-sum operation circuits for the input digital signals x0, x1, x2, and x3, equations (15) to (18) are obtained.
S1 (t03) = x0 * c0 + x1 * c1 + x2 * c2 + x3 * c3 Formula (15)
S2 (t03) = x0 * c4 + x1 * c5 + x2 * c6 + x3 * c7 Formula (16)
S3 (t03) = x0 * c7 + x1 * c6 + x2 * c5 + x3 * c4 Formula (17)
S4 (t03) = x0 * c3 + x1 * c2 + x2 * c1 + x3 * c0 Formula (18)

  That is, the first product-sum operation circuit and the fourth product-sum operation circuit operate on x0, x1, x2, and x3 using the common coefficients c0, c1, c2, and c3. The required timing is different. For example, the first product-sum operation circuit uses c0 as the coefficient of the input digital signal x0, while the fourth product-sum operation circuit uses c0 as the coefficient of the input digital signal x3. The timing at which the same coefficient c0 is required differs between the first product-sum operation circuit and the fourth product-sum operation circuit.

  Similarly, the second product-sum operation circuit and the third product-sum operation circuit perform operations using the common coefficients c4, c5, c6, and c7, but the timing for performing the operations using the respective coefficients is different. In other words, the first and second product-sum operation circuits and the third and fourth product-sum operation circuits need to read the same coefficient at different timings. Therefore, it is necessary to make the coefficient memory a dual-port memory so that the coefficients used by the first and second product-sum operation circuits and the coefficients used by the third and fourth product-sum operation circuits can be read independently. is there.

  FIG. 5 shows a circuit block diagram of such a decimator circuit according to the second embodiment. In the decimator circuit 10B of FIG. 5, the number of coefficients stored in the coefficient memory 2B is reduced to ½ from the decimator circuit of the first embodiment of FIG. The coefficient memory 2B is a dual port memory.

  As an address input signal for the coefficient memory, two types of addresses, ADRE and ADRL, are input, and coefficient data corresponding to the address ADRE and coefficient data corresponding to the address ADRL are simultaneously output corresponding to different addresses. The address ADRE designates the read address of the coefficient used by the L / 2 previous product-sum operation circuits from the top of the L product-sum operation circuits connected in cascade, with the value of L being an even number. Similarly, the address ADRL specifies a read address of a coefficient used by L / 2 remaining product-sum operation circuits from the end among L product-sum operation circuits connected in cascade.

  In FIG. 5, there are two product-sum operation circuits 1-a and 1-b, and among them, the previous product-sum operation circuit 1-a has a coefficient signal read according to the designation of the address ADRE. Ca is connected to the internal multiplier 11. On the other hand, in the subsequent product-sum operation circuit 1-b, the coefficient signal Cb read by the designation of the address ADRL is connected to an internal multiplier not shown.

  In FIG. 5, since the timing control circuit 3B outputs two addresses ADRE and ADRL as addresses of the coefficient memory 2B which is a dual port memory, the configuration and functions of the timing control circuit 3 of the decimator circuit 10 shown in FIG. Is different. In the decimator circuit 10B of FIG. 5, as described above, the configuration and function of the coefficient memory 2B and the timing control circuit 3B are slightly different from those of the decimator circuit 10 shown in FIG. The decimator circuit 10 has substantially the same configuration, function, and operation. Therefore, duplicate description is omitted.

[Third Embodiment]
As can be understood from the equations (15) to (18) described in the second embodiment, four coefficients used by the first to second product-sum operation circuits to calculate the input digital data x0, and x3 The four coefficients used for the calculation of are common, and the four coefficients used for the calculation of x1 and the four coefficients used for the calculation of x2 are common.

  The coefficients used by the first product-sum operation circuit and the fourth product-sum operation circuit for the four operations are common to each other, and the second product-sum operation circuit and the third product-sum operation circuit are used for the four operations. The coefficients used for the calculation are also common to each other. Therefore, as a single-port 2-address coefficient memory that reads out the four coefficients in parallel without using a dual-port memory as in the second embodiment, among the four coefficients read out simultaneously, By providing a coefficient selector for selecting one coefficient from two coefficients on the side of each product-sum operation circuit, the same function as in the second embodiment can be realized.

  That is, if L is an even number and the number of product-sum operation circuits is L, the relationship of the coefficients simultaneously used by the L product-sum operation circuits is determined. Of the L coefficients read out, which coefficient is used, a coefficient selector is provided on the product-sum operation circuit side, and the coefficient selected by the coefficient selector from the L coefficients simultaneously read as the coefficient used by the multiplier is used. Also good.

  FIG. 6 shows a circuit block diagram of such a decimator circuit according to the third embodiment. The decimator circuit 10C of FIG. 6 reduces the number of coefficients stored in the coefficient memory 2C to ½ from the decimator circuit of the first embodiment of FIG. A coefficient selector 16 is provided which reads in parallel the coefficients used by the L product-sum operation circuits from the coefficient memory 2C, and selects the coefficients used by each product-sum operation circuit from the L coefficients read in parallel.

  In FIG. 6, since the value of L is 2, the two coefficients CL and CM are read out from the coefficient memory 2C, but the two coefficients read out simultaneously are the product-sum operation circuits 1C-a and 1C-b. Which one is used is not fixed as in the first embodiment. The product-sum operation circuit 1C of the second embodiment is provided with a coefficient selector 16, and the coefficient selector 16 selects which of the two coefficients read from the coefficient memory 2C is used as a coefficient for multiplication. To do. The coefficient selector 16 provided in each of the product-sum operation circuits 1C-a and 1C-b supplies the coefficient Ca to the multiplier of the product-sum operation circuit 1C-a, and the multiplication (not shown) of the product-sum operation circuit 1C-b. The unit is supplied with a coefficient Cb.

  As shown in FIG. 6, a timing control signal output from the timing control circuit 3C as a coefficient selector selection signal may be used, but the timing control signal is a timing control for controlling the down-rate converter 4 and the selector 14. The signal en1 is a timing control signal en2 having a different timing.

  Next, examples in which the above embodiment is specifically applied will be described.

  FIG. 4 is a diagram illustrating a state transition for each sampling period in the decimator circuit 10 of the first embodiment illustrated in FIG. In Example 1, in the decimator circuit 10 of the first embodiment shown in FIG. 1, the number of product-sum operation circuits L = 2, the decimation ratio M = 3, and the number of FIR filter taps (order) N = 6.

In FIG. 4, “t” is the time for each sampling period of the input digital signal, “xi” is the value of the input digital signal for each sampling period, and “Cj” is from the coefficient memory 2 to the product-sum operation circuit 1 -a. The coefficient value to be read, “C _{N / 2 + j} ”, is the coefficient value read from the coefficient memory 2 to the product-sum operation circuit 1-b. “Da” is an output value of the accumulation result output from the product-sum operation circuit 1-a, and “db” is an output value of the accumulation result output from the product-sum operation circuit 1-b. is there.

  In FIG. 4, in the initial state, the product-sum operation circuit 1-a is initialized with a fixed value 0, so that the value of da is 0. At time t0, the value of the input digital signal xi is x0, and the coefficients c0 and c3 are read from the coefficient memory. In the product-sum operation circuit 1-a, the value x0 of the input digital signal xi and the coefficient c0 are multiplied and added to the initial set value 0, and the value of the output value da becomes x0 * c0.

  At time t1, the next input digital signal x1 and the coefficient c1 are multiplied and added to the value of the output value da at time t0, and the value of the output value da becomes x0 * c0 + x1 * c1. At time t2, the multiplication result of the input digital signal x2 and the coefficient c2 is added to the output value da at time t1, and the value of the output value da becomes x0 * c0 + x1 * c1 + x2 * c2. When this calculation is completed, the product-sum calculation circuit 1-b is initialized with the output value da, and the product-sum calculation circuit 1-a is initialized to a fixed value 0.

  At time t3, the value of the input digital signal xi is x3, and the same coefficients c0 and c3 as at time t0 are read from the coefficient memory. In the product-sum operation circuit 1-a, the value x3 of xi and the coefficient c0 are multiplied, and in the product-sum operation circuit 1-b, the value x3 of xi and the coefficient c3 are multiplied. Since the output value da of the product-sum operation circuit 1-a is initially set to 0 after time t2, the multiplication result x3 * c0 of x3 and c0 becomes the value of the output value da. The output value db of the product-sum operation circuit 1-b is added to the value x0 * c0 + x1 * c1 + x2 * c2 initialized by the output value da after time t2, and the multiplication result x3 * c3 is added to (x0 * c0 + x1 * c1 + x2). * C2) + x3 * c3.

  Similarly, at time t4, the multiplication value x4 * c1 is further added to the value of the output value da, and the multiplication value x4 * c4 is further added to the value of the output value db. At time t5, the multiplication value x5 * c2 is further added to the value of the output value da and output as the next initial set value of the product-sum operation circuit 1-b. The output value db of the product-sum operation circuit 1-b is output to the outside as a filter operation result based on input digital signals x0 to x5. Thereafter, the filter operation result is output to the output value db of the product-sum operation circuit 1-b every three sampling periods (time t8, t11,...) Of the input digital signal, thereby realizing a function as a decimator circuit. .

  That is, the product-sum operation circuit 1-a multiplies the input digital signal xi and the value of the coefficient cj, which are input in synchronization with the sampling period, by the multiplier based on the value of the decimation ratio M = 3, Two multiplication values are added to a fixed value that is an initial setting value, and an operation of outputting as an output value da is performed in synchronization with the sampling period of the input digital signal xi. The coefficient value is multiplied by repeatedly using three coefficients c0, c1, and c2.

  In the product-sum operation circuit 1-b, the output value da resulting from the accumulation of the product-sum operation circuit 1-a is input as an initial setting value, and the result obtained by multiplying the initial setting value by the product-sum operation circuit 1-b is added. To do. Also, the coefficients used by the product-sum operation circuit 1-b are multiplied by repeatedly using the three coefficients c3, c4, and c5.

  FIG. 7 is a diagram illustrating a state transition for each sampling period of the decimator circuit 10B of the second embodiment illustrated in FIG. 5 or the decimator circuit 10C of the third embodiment of the second embodiment. In the second embodiment and the third embodiment, there is almost no difference with respect to the transition state of the operation of the product-sum operation circuit. Therefore, the operation of the second embodiment can be performed using either decimator circuit.

  In the description of the second embodiment shown in FIG. 7, the description that is substantially the same as the first embodiment is omitted, and only different portions are described. In Example 2, in the decimator circuit 10B of the second embodiment shown in FIG. 5 or the decimator circuit 10C of the third embodiment, the number of product-sum operation circuits L = 2, decimation ratio M = 4, FIR filter The number of taps (order) N = 8.

  In FIG. 7, “CL” and “CM” are values of two coefficients read out in parallel from the coefficient memory 2C when the decimator circuit 10C of the third embodiment is used. When the decimator circuit 10B of the second embodiment is used, “CL” and “CM” are meaningless.

  “Ca” is a coefficient given to the multiplier of the previous product-sum operation circuit (1-a or 1C-a), and “Cb” is the subsequent product-sum operation circuit (1-b or 1C−). This is a coefficient given to the multiplier of b). When the decimator circuit 10C of the third embodiment is used, “Ca” and “Cb” are values selected by the coefficient selector from “CL” and “CM”.

  The value da3 accumulated by the previous product-sum operation circuit (1-a or 1C-a) up to time t3 is given as an initial setting value to the subsequent product-sum operation circuit (1-b or 1C-b). , Used for accumulation after time t4. Similarly, the value da7 accumulated by the previous product-sum operation circuit up to time t7 is given as an initial setting value to the subsequent product-sum operation circuit and used for accumulation after time t8.

[Other embodiments]
In the first to third embodiments, the multiplier 11 and the adder 12 may have a pipeline configuration. However, in this case, it is necessary to delay the timing control signal en for initializing the accumulator 15 by the pipeline delay.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention naturally includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

1-a, 1-b, 1-1, 1C-a, 1C-b: product-sum operation circuit 2, 2B, 2C, 32: coefficient memory 3, 3B, 3C, 34: timing control circuit 4: down-rate converter 10, 10A, 10B, 10C: Decimator circuit 11, 331: Multiplier 12, 24, 332: Adder 13, 333: Register 14: Selector 15: Accumulator 16: Coefficient selector 21: Delay element 22: Down sampler 23 : Filter 31: Buffer memory 33: Arithmetic unit In: Digital signal input terminal Xi: Input digital signal Cj, CN2 _{/ 2 + j} , _{CN / L + j} , _{CN * (L-1) / L + j} , _CL , C _M : (tap) coefficient ADR: address signal en, en1, en2: timing control signal

Claims (9)

A plurality of product-sum operation circuits, and a coefficient memory for giving a product operation coefficient to each of the plurality of product-sum operation circuits,
Each of the plurality of product-sum operation circuits operates at a sampling period of the input digital signal, and multiplies the input digital signal by a coefficient read from the coefficient memory, and accumulates the operation result of the multiplier. The accumulators included in each of the plurality of product-sum operation circuits are cascade-connected to each other, and each time accumulation is performed M times (M is an integer of 2 or more), The connected accumulator is set to a fixed value, the accumulators other than the first stage are initialized by the output signal of the accumulator connected to the previous stage, and the input digital signal is sampled by the output signal of the last stage accumulator. A decimator circuit characterized by obtaining an output signal whose period is thinned by M times.   The accumulator includes a register, a selector that receives an initial setting value and an output signal of the register, and selects and outputs any of them according to a timing control signal; an output signal of the selector and an output signal of the multiplier 2. The decimator circuit according to claim 1, further comprising: an adder that adds to each other, and storing the addition result of the adder in the register.   3. The decimator circuit according to claim 2, further comprising a timing control circuit that controls reading of coefficients from a coefficient memory in accordance with a sampling period of the input digital signal and generates the timing control signal.   4. The decimator circuit according to claim 1, further comprising a down-rate converter that holds an output signal of the accumulator at the final stage and updates the output signal every time the accumulation is performed M times. When the number of the plurality of cascaded product-sum operation circuits is L (L is an integer of 2 or more), the L cascaded product-sum operation circuits are L * M-th order FIR ( A decimator circuit serving as a decimation filter as a Finite impulse response) filter,
Furthermore, when L is an even number and L * M taps of the FIR filter are arranged in time series, k is an arbitrary integer greater than or equal to 0 and less than (L / 2) * M (L / 2) * M The coefficient value of the k-th tap is equal to the coefficient value of the (L / 2) * M + k + 1-th tap, and the coefficient memory stores the coefficient of the (L / 2) * M-k-th tap of the FIR filter. 5. The decimator circuit according to claim 1, wherein (L / 2) * M + k + 1th tap coefficient is stored as a common value as the same data at the same address. 6.   The coefficient memory reads out coefficients used by the L / 2 product-sum operation circuits in the preceding stage among the L cascaded product-sum operation circuits and the remaining L / 2 product-sum operations in the subsequent stage. 6. The decimator circuit according to claim 5, wherein the circuit is a dual port memory capable of simultaneously reading out the coefficients used by the circuit by designating different addresses.   The coefficient memory reads L coefficient data in parallel, and the L product-sum operation circuits respectively input two corresponding coefficient data among the L coefficient data read from the coefficient memory, 6. The decimator circuit according to claim 5, further comprising a coefficient selector for supplying one selected coefficient data as coefficient data of a multiplier. Each includes a multiplier and an accumulator, and includes a plurality of product-sum operation circuits in which the input and output of the accumulator are cascade-connected to each other, and the sampling period of the input digital signal is M times ( M is an arithmetic method of a decimator circuit that outputs an output signal thinned out to an integer of 2 or more,
Among the accumulators that are respectively included in the plurality of multiply-accumulate circuits and are cascade-connected to each other, the initial stage accumulator is initialized with a fixed value, and the accumulators other than the first stage are accumulated in the previous stage. A first step of initial setting according to the output value of the container;
A process of multiplying a predetermined coefficient and the input digital signal respectively by a multiplier included in the plurality of product-sum operation circuits and adding the multiplication result to an initial setting value of the accumulator A second step that repeats M times synchronously with
And repeating the first step and the second step in accordance with the cycle of the thinned output signal, and each time the second step is completed, the last of the cascaded accumulators A decimator circuit calculation method, wherein an output signal obtained by thinning the sampling period of the input digital signal by M times is obtained from an output value of a stage accumulator.   When the number of the plurality of product-sum operation circuits is L (L is an integer of 2 or more), the L product-sum operation circuits function as a decimation filter as an L * M-th order FIR (Finite impulse response) filter. 9. The decimator circuit calculation method according to claim 8, wherein the predetermined coefficient is a coefficient of each tap of the L * M-th order FIR filter.

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