JPS58169674A - Digital data processor - Google Patents

Abstract

PURPOSE:To perform the processing at a high speed even in case the data having a varying coefficient is processed, by using two counters as address pointers of a data storing memory and at the same time by setting two routes through which the data reaches a multiplier. CONSTITUTION:Counters 91 and 92 can set initial values with an instruction within an instruction memory 1 and also can count up or down. These counters are provided as address pointers of a data storing RAM 4. In addition, signal lines 101-1 and 101-2 are extended from a constant memory 3, and signal lines 102-1 and 102-2 are extended from the RAM 4. The lines 101-1 and 102-1 are connected to a signal line 104, and the line 104 is connected to the input of one side of a multiplier 8 via a signal line 107. On the other hand, the lines 101-2 and 102-2 are connected to the other input of the multiplier 8 via a selector 52 and a signal line 106. Therefore the data can be set to the multiplier 8 through two routes and at one time.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital data processing device that is used to perform processing such as Fourier transform and filtering on obtained notes that are digitized into digital data. 4 related to this.

[Technical background of the invention]

In order to control various plants and automatic equalizers used for data transmission, processes such as non-filtering and Fourier transformation are performed on the obtained digital data. In order to perform such processing, conventionally, a digital data processing apparatus as shown in FIG. 1 has been used.

In the digital data processing device shown in FIG. 11, each part is controlled by instructions stored in an instruction memory 1 being read out by an instruction order control circuit (not shown) and decoded by a decoder 2.

For example, this digital data processing device is caused to perform transparsal filter processing represented by the calculation of ΣanXn, which is filter processing. here s&h
is a coefficient that represents the characteristics of the filter, and in many cases,
This is a predetermined constant.

Moreover, xH is a sample value of input data.

In this case, the coefficient an is fixedly stored in the constant memory lJ3,
Data xn is sequentially stored in the data storage RAM 4.

Next, in order to perform the operation ΣanXn, the coefficient part is first read out from the constant memory 3 to the signal line 101, and
4 and signal line 106 to one input of the multiplier 8. Next, the data signal is read out from the data storage RAM 4, and the signal line 104 and the signal line 10 are read out from the data storage RAM 4.
7 to the other input of the multiplier 8. Then, the multiplication result is obtained from the multiplier 8 for a certain period of time wkK. This multiplication result is given to the selector 5 via the signal 1Fj 108, passes through the selector 5, and is set to one input of the p-arithmetic logic unit (hereinafter referred to as ALU) 6 via the signal @105.

Now, assuming that the transpersal filter processing is being performed continuously, the accumulator 7 stores the previous processing result, so the previous processing result is sent to the ALU 6 via the signal line 106. given to the other input.

As a result, the data inputted from the signal line 105 and the data inputted from the signal line 106 are added by the ALU 6, and the result of the addition is stored in the Akinimuretafu again. When this operation is repeated, the processing result of the above-mentioned transpersal filter is obtained.

Also, normally, in such a digital data processing device, when addition is being performed in U and ALU 6, so-called pipeline processing is performed to simultaneously set the data of the next sample value into the multiplier 80 input cache. The aim is to shorten the Go-C processing time.

Furthermore, in the digital data processing device shown in FIG.
Instead of storing the address of M4, counters 9 and 10 are provided as address pointers, and the address is specified using these counters. Before processing, the counters 9 and 1 are set according to the output from the instruction memory 1.
When an initial value of 0 is set and repeated processing is performed, the counters 9 and 10 are counted up (or down) by a command to perform efficient processing.

Read the constant data an from the 6,4 constant memory 3 as described above? This processing method is used when fixed coefficients are used. On the other hand, when applying filter processing to an automatic equalizer used for data transmission, for example, the coefficients must be stored in the data storage RAM 4. . In other words, it is necessary to perform variable coefficient filter processing that detects the transmission output and automatically corrects its own coefficients to reduce distortion, so the coefficients are rewritable memory. It is stored in the data storage RAM 4.

Therefore, conventionally, a coefficient storage area and a data storage area are provided in the data storage RAM 4, a part of the address of the data storage RAM 4 is specified by the counter 9, and the remaining part is given by a command. It had been taken. For example, if the address of the data storage RAM 4 is 6 bits, the counter 9 gives the lower 5 bits, and the higher 1 bit is given to the instruction for switching.

When the coefficient an and the data are stored in the data storage RAM 4 in this way, the coefficient ay1 is first read out from the data storage RAM 4 and is read out via the signal line 102, the signal line 104, and the signal line 106. Next, the data set to one input of the multiplier 8 is transferred to the data storage RAM.
4 and set to the other input of the multiplier 8 via the signal line 102, the signal line 104, and the signal line 107. The following process is addition using AlO2 as described above. - Problems with Background Art] However, although such processing poses no problem the first time, the following problems occur from the second time onwards.

For example, the coefficient an is the address X of the data storage RAM4.
The data is stored from (000000,) to address L's (001111), and the data is transferred from address (iooooooo,) of data storage RAM 4 to address (1o111).
12), data X is stored in the first process. is stored at the address (000000z), and there is no problem because the coefficient m (1 is 7)" is stored at the address (1000001) K. However, the second new data X6 is stored as data x0, and the previous data data x0 is data x
Correct processing cannot be performed unless it is treated as 1. In other words, the previous data must be shifted to the address of data x1, the previous data x1 to the address of data x2, and so on. If the operation is executed using a command, the same processing time as the original filter processing is required, and the processing efficiency decreases. Furthermore, 2 of multiplier 8
Since data must always be supplied to the human power via the signal line 104, only one piece of data can be supplied, and this also increases the processing time.

[Purpose of the invention]

The present invention has been made based on the circumstances described above. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital data processing apparatus that can process data at high speed even in data processing in which coefficients change.

[Overview of the invention] Therefore, in the present invention, the above-mentioned object is achieved by providing two counters as address pointers of data storage memory and two routes for data to reach the multiplier. did. .

[Embodiments of the invention]

FIG. 2 shows an embodiment of the present invention.
Components that are the same as those in the figures are given the same reference numerals, and their explanation will be omitted.

In the embodiment shown in FIG. 2, the commands in command list 1
Counters 91 and 92, to which initial values can be set and which can be counted up (or down), are provided to the left of the address pointer of the data storage RAM 4.

Furthermore, a signal 41101-1 and a signal line 101-2 extend from the constant memory 3, and a signal 11101-1 and a signal line 102-2 extend from the data storage RAM 4. The signal line 101-1 and the signal line 102-1 are
The signal line 104 is connected to one input of the multiplier 8 via the signal line 107. Also, signal line 1
01-2 and the signal line 102-2 are connected to the selector company, and are connected to the other input of the multiplier 8 via the selector company signal line 106. Therefore, data can be set to the multiplier II8 simultaneously from two routes.

Next, the operation will be described assuming that transpersal filter processing is performed. - First, in the case of a fixed coefficient, the coefficient axis is read out from the constant memory 3, and the coefficient aBFi signal It 101-2 is sent to one input of the multiplier 8 via the selector 52 and the signal line 106. Set. From the data storage RAM4, data xn
is read out, and this u-yu x, ta<s+&1102
-1, multiplier 8 via signal line 104 and signal line 107
is set to the other input of As a result, the multiplier 8 performs multiplication, and the obtained result is transferred to the signal line 108 and the selector 5.
and is set to one input of AlO2 via signal line 105.

Still, the other input of AlO2 has an Akinimulator 7
The previous processing results are set through the signal line 106, and the AlO2 adds these. At this time, the counter 91 performs the function of loading data from the data storage RAM 4.

Next, the case of processing using variable coefficients will be explained.

The coefficient an is now 917 in the data storage RAM4.
113 As shown in Figure A, data is stored from address (0000002) to address (0011112), and data is stored from address (1000002) to address (1011).
112). In prisoners,
Although the memory is out of memory, it is actually continuous.

Then, the next time new data is stored, it is slid. For example, for new data x5, the 3rd H
Store it at address (111111,) like D. Note that the counter has 5 binary digits, and the upper 1 bit of the address is fixed as 10"+, @, corresponding to counter 91.92.
1% shall be given.

Then, for the next process, a counter is incremented so that the set values can be read out in the order of data, intuition + 11 + --- + Xn-1. As for the coefficient, here too the coefficient is 16 * J + J * −−−
&. The counter 91 is set so that it can be read in the order of (go 0
0-001) and count up.

Furthermore, new data X'6' + 1'6' r --
Slide the counter every time - is obtained. fr
iJ address (1
111102), and if new data
1. It is stored as shown in the 3rd diagram.

Then, at the time of reading, in the case of FIG.
D) jlih 16, tefi X6 + xo #x
ol--o I of XH-2-, give. Even in the case of stiff snow, the coefficient a11 is aQ, sl,
", e -p"n in the order of reading ゛t-.

At the same time, the counter 91#i address (000000) is incremented by 1 at the time of 6% translation in the turtle 1iA, and the counter 92 is counted up by 1 from the address (000000).
00, ) is incremented by 1. 3rd HD
When reading data from IH5, counter 92 stores 92 digits of data
000000x) and increments by 1. A similar restriction i is made for the set 3-C1 13 in FIG. 1D.

In addition, due to the softening of 1 or more, the coefficient: IJ Kayobachi 10
2-2, selector 52, multiplier 8 via signal w106
is set to one input of the data Xntl signal #10.
2-1, Signal - 104 and U * "t lN!' 1
07 is set to the other input of the multiplier 8. The following processing is the same as that for the identification coefficient, so the explanation will be omitted.

In this way, counters 91 and 92 always read out and process the appropriate set of coefficients and data (a, xn) to multiplier 8 simultaneously.

Furthermore, the contents of the counters 91 and 92 can be exchanged by a command.
The second-order piquad filter processing can also be performed at high speed.

In addition, in the embodiment, an example was shown in which new data is sequentially stored in the free area, but the following is an example in which new data is stored in the address value where the oldest data is stored at that time. Now, in the data storage RAM 4 shown in
For example, the address (000
It is assumed that data is stored from address (000,) to address (001111,)K, and data is stored from address (100000,) to address (1011112).

Then, the counter 92 stores the new data X- at address (101111,). Then, for the next process, from the set values, data can be read in the order of data

Count up 92 colors. About the coefficients ゛ is also a coefficient -1a ~ jl! , . . . The counter 91 is set to (0000001)K and counted up so that it can be read out as a set of &1.

Further, each time new data 4 4 , . . . is obtained, the counter catfish is slid. New data needs; if available, please send to Mori, address (10111Of).

If new data x@:p6 is created, the address (1
01101m) respectively.

Then, at the time of reading, if new data xot is obtained, data Xa,
Read out as a set of XQ XQ...xl-1. In any of these cases, the coefficient details are ak84...
・Read out in the order of the rings.

#3 Figure AK&%A is used when starting out.

The counter 91 is counted up by 19 from the address (000000*), and the callan 492 is counted up by 19 from the address (000000*).
000m) is counted up by 1. When new data
It is counted up one by one.

The counter 92 is controlled from the address (101111,) to 7 addresses (10000 (h), and is counted up by Kl. If new data X: is obtained, new data X;' is obtained. Similarly, new data is stored and read at that address instead of the oldest data at that time.

[Effect of sale]

As explained above, according to the present invention, two counters are provided and two routes for data to reach the multiplier are secured, so coefficients and data can be set at the same time, resulting in a high-speed digital data processing device. becomes.

Furthermore, since the new data storage address is processed by sliding it using one counter, the data shift time that was previously required is not required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a conceptual diagram of a data storage memory for explaining the operation of the embodiment of the present invention. 1... Instruction memory 2... Decoder 3...
・Constant memory 4...RAM for data storage (memory for data storage) 5
．． 52...Selector 6...MULU7...
7 unit t/-t 8... multiplier 9.91,92
．． 10... Counter agent Patent attorney Book 1) Figure 1 Figure 3 (A) ゛ (B) (C) CD)

Claims (1)

[Claims] CI) An arithmetic logic operation unit, a multiplier, a data storage memory, and a memory for storing instructions and constant data, the memory for storing instructions and constant data A digital data processing device that processes digitized data with instructions controlling the valleys, comprising: two counters whose initial values can be set by the instructions and which also function as address pointers for the data storage memory; A digital processing device comprising at least two routes through which data output from a data storage memory reach different input terminals of the multiplier. (2) Consisting of a memory that stores instructions and constant data, or a memory that stores instructions and a memory that stores constant data, the data read from the memory that stores constant data is transmitted to two different input terminals of the multiplier, respectively. The digital data processing apparatus according to claim 1, characterized in that the digital data processing apparatus has two routes leading to the digital data processing apparatus. (3) The digital data processing according to claim 1 or 2, wherein one of the two counters is set by sequentially sliding a new data storage address. Device. (4) The digital data processing device according to any one of claims (1) to (3), characterized in that the two counters exchange their self-answers in response to a command. .