JPH0199312A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware by connecting an output of a multiplier input register and an input of two inputs of an adder to which an output of an accumulator is connected. CONSTITUTION:A multiplier 3 receiving a multiplicand such as a filter coefficient to a 1st input terminal A and receiving a multiplier such as a filter input/ output to a 2nd input terminal B, a 1st register 6 and a 2nd register 7 storing a multiplier given to the multiplier, a 1st selector means 81 giving a multiplier to the 2nd input terminal of the multiplier while selecting one output of both the registers, an adder 4 receiving the output of the multiplier at the 1st input terminal, a 3rd register storing the output of the adder and a 2nd selection means 82 selecting any of the output of the 1st register, the output of the 2nd register, the output of the 3rd register and a zero and giving it to the 2nd input terminal of the adder, are provided. Thus, the 1st and 2nd registers 6, 7 are selected complementarily by the 1st and 2nd selection means 81, 82 to execute the multiplication and addition in parallel thereby decreasing the number of steps.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic device used for digital signal processing such as a digital filter.

(Prior Art) Generally, a digital filter is constructed by cascade-connecting second-order IIR digital filters according to the order of the filters. Figure 2 shows the second order II due to the direct form configuration.
This shows an example of the configuration of an R filter, with an adder of 1.2*3
+4, multiplier S, 6.7°8, and delay units 9 and 10. The transfer function of this filter is expressed as. Here, al+! L2 + tll
+1)2 is the filter coefficient. The arithmetic expression for this digital filter is shown by equation (2).

vn is input to adder 1 as a filter input, and yn is output from adder 3 as filter output. Further, un is the output of the adder 1, and u n-1+un-2 are the outputs of the delay devices 9 and 10, respectively.

Since the delay devices 9 and 10 only delay the input by one sample time interval, un-1 is equal to the value of un one sample time ago, and un-2 is equal to the value of un two sample times ago. The filter shown in FIG. 2 has the disadvantage that as the cutoff frequency of the filter becomes lower, the coefficient sensitivity decreases and the dynamic range of the filter deteriorates.

As another example of the configuration of a second-order IIR filter, an example of the configuration of a second-order low element sensitivity IIR filter is shown in FIG.

This filter has the excellent characteristics that even when the cutoff frequency of the filter is low, the coefficient sensitivity is small and the dynamic range of the filter does not deteriorate. The filter in FIG. 3 is composed of adders 1, 2.3.4.11.12, multipliers 5.6.7, 8.13.14, and delay device 9.10. The transfer function of this filter is expressed as: α1. α2. β1. β2 r Sl , S
2 are the multipliers of multipliers 7, 8.5.6.13.14, respectively. The calculation formula for this digital filter is un
=xn+β1vn-1+β2wn-1(4,1)yn=
un+α1vfi-1+α2”n-1(4,2)wn=
w,, 1 +52vn-, (4,3)vn=vn-
It is expressed as 1+51un(4,4). X is input to adder 1 as a filter input, and y is output from adder 3 as filter output. v
, v are the outputs of the adders 11 and 12 at the current time n, and vn-11wn-1 are the outputs of the delay device 9, respectively.
10, which is the output of adder 11.12 one sample time ago.

Figure 4 shows the above equations (2,1), (2,2) or (
This is an example of a conventional arithmetic device that performs calculations of equations 4,1) to (4,4), and is a read-only memory (hereinafter referred to as ROM).
J, data memory (hereinafter referred to as 1'eAM) 2, multiplier 3
, adder 4, accumulator 5, first multiplier input register (M) 6, second multiplier input register (L) 7,
It consists of 8 selection circuits (SEL), 9 data buses, and 10 auxiliary registers (Wφ) (Configuration of DSP with sum-of-products type ALU 'i suitable for IIR filter, 1988)
Annual National Conference of the Institute of Electronics and Communication Engineers, Communications Division, P, 1-281.
,reference).

In Fig. 5, (2, 1) and (2, 2
) operation step 76 is shown. However, Dl and D2 are data u n -1r u
Please give me the storage address of n-2 RAM. Also,
FIG. 6 shows the operational steps when calculating equations (4,1) to (4,4) using the arithmetic device shown in FIG. However, Do
.

D and D2 indicate the storage address of the data un+Vnrwn in the RAM. The fourth step and fifth step in FIG. 6 are the multiplier 14 and adder 12 in FIG.
, (4, 3
) corresponds to the operation shown in the formula. The calculation of equation (4, 3) represents the calculation of an integrator whose transfer function is expressed by equation (5, 1).

Similarly, equation (4,4) represents the operation of an integrator whose transfer function is shown by equation (5,2). be done. The calculations in the sixth and seventh steps in FIG. 6 are steps for calculating the integrator of equation (4, 4).

Incidentally, an actual filter is constructed by cascading the second-order IIR filters shown in FIG. 2 or 3 according to the order of the filters. In this case, k
Storing u n -2 of the second-order IIR filter in the second stage into the M register can be performed simultaneously with the last step of the (k-1)th stage. Therefore, when performing the second-order IIR filter processing continuously, the actual number of operation steps per stage of the second-order IIR filter is 4 steps in the example of FIG. 5, and 9 steps in the example of FIG. Become. That is, the fourth
When all calculations of the low element sensitivity filter shown in Fig. 3 are performed using the arithmetic unit shown in the figure, the second-order I of the direct form configuration shown in Fig. 2 is
The operation steps are increased by 5 steps compared to the IR filter.

(Problems to be Solved by the Invention) As stated above, in the conventional arithmetic device, other element sensitivity IIR
Performing filter calculations has the disadvantage that the number of operation steps of the calculation device increases, so in order to realize the calculation of low element sensitivity filters, the operation speed of the calculation device must be increased. However, there was a problem in that it was difficult to realize.

The present invention eliminates the drawback that the operation steps of the arithmetic device increase when performing the arithmetic operation of the multi-element sensitivity IIR filter described above, and performs the arithmetic operation of the low element sensitivity filter without increasing the operation speed of the arithmetic device. The aim is to provide an excellent device that can

(Means for Solving Problems) In the present invention, a multiplicand such as a filter coefficient is given to a first input terminal (A), and a multiplier such as a filter input/output is given to a second input terminal (B). a multiplier 3; a second luzisk 6 and a second register 7 for storing a multiplier to be applied to the multiplier;
a first selection means 81 which selects one output of both registers and applies a multiplier to a second input terminal of the multiplier; an adder 4 whose first input terminal is supplied with the output of the multiplier; A third register stores the output, and a third register stores the output of the first and second register.
It is provided with a second selection means for selecting one of the output of the register, the output of the third register, and a zero value and applying the selected one to the second input terminal of the adder.

(Operation) By complementary selecting the first and second registers by the first and second selection means, multiplication and addition can be executed in parallel, for example, the fifth step and the fifth step in FIG. The sixth and seventh steps can each be executed in one step, reducing the number of steps.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a read-only memory (ROM) 1, a data memory (RAM)
2, multiplier 3, adder 4, accumulator (ACC
) 5. First multiplier input register (M, hereinafter referred to as M register) 6. Second multiplier input register (L, hereinafter referred to as L)
7. First selection circuit (SELL)
81, a second selection circuit (5EL2) 82, a data bus 9, and an auxiliary register (Wφ) 10. M
The output of the L register 6°7 is applied to the input B of the multiplier 3 via the first selection circuit 81, and at the same time,
It is applied to the input of the adder 4 via the second selection circuit 82.

FIG. 7 shows the operational steps when the calculation device of FIG. 1 performs the calculation of the low element sensitivity filter shown in FIG. 3. The operation of each step will be explained in detail below.

Memo IJ ROM 1 contains multiplication coefficient α1. α2. β,
.

β21 S1+ 82 is written in advance. Furthermore, data vn and Wn as the results of the previous filter calculation are written in addresses Dl and D2 of the memory RAM 2, respectively. The accumulator 5 also stores input data Xn of the previous filter operation result.

Step 1> First, in the first step, RAM 2
The content Wn-1 of address D2 is read out and the data bus 9
The data is stored in the M register 6 and the auxiliary register 10 via the M register 6 and the auxiliary register 10.

Step 2> In this step, the multiplication coefficient β2 is read from the ROM 1 and applied to the input A of the multiplier 3, and at the same time, the content Wn-1 of the M register is applied to the multiplier 3 via the first selection circuit 81. is given to input B of Therefore, the multiplication result AXB becomes AXB=β2''IFn-+. This multiplication result is given to the input C of the adder 4,
On the other hand, the accumulator 5
The content X of is given as input. The adder 4 outputs the addition result C+D=(β2·Wn-1]+xn, which is stored in the accumulator 5.

On the other hand, at the same time that these multiplications and additions are performed, the RAM
2, the contents vn-4 of address D1 are read out and stored in L register 7 via data bus 9.

<Step 3> In this step, the multiplication coefficient β is read from the ROM 1 and given to the input A of the multiplier 30,
The content Vn-1 of the L register is selected and applied to the input B by the first selection circuit 8.

The multiplication result is given to the input C of the adder 30 as follows: AXB=β1·vn-1. On the other hand, as an input, the calculation result [β2・wn-1+
xn] is given. Therefore, the output of the adder 5 is
] Then, un of the equation (4, 1) is obtained. This result is stored in accumulator 5.

<Step 4> In this step, the multiplication coefficient 82 is read from the ROM 1 and given to the input A of the multiplier 3,
The content vn-1 of the L register is selected and applied to the input B by the first selection circuit 81.

The multiplication result is A x B = 82-V, 1 and is given to the input C of the adder 3. - If possible, the second selection circuit 82 selects the contents of the M register w.
n-1 is selected and given. The output result of the adder 5 is: C+D=(S2''vn-,]+wn.

Then, W of equation (4,3) is obtained. This result is
The unO value stored in the accumulator 5 is stored in the accumulator 5, but before that, the unO value stored in the accumulator 5, which is the result of the operation in step 3>, is stored in the M register via the data bus 9.

<Step 5> In this step, ROM 1,
Multiplication coefficient 81 is read out and applied to input A of multiplier 3. - The content U of the M register is selected and given to the universal power B by the first selection circuit 81. The multiplication result is AxB=81·un, which is applied to the input C of the adder 3. For one-way tensioning, the second selection circuit 82 selects the contents of the L register vn.
-1 is selected and given. The output result of the adder 5 is C+D=[:Sl.un]+vn-1, and Vn of equation (4, 4) is obtained. This result is
The WnO value is stored in the accumulator 5, but before that, the WnO value stored in the accumulator 5, which is the calculation result in step 4>, is written to address D2 in the RAM 2.

(Stella 7'6) In this step, the fixed value '''1# from ROM 1 is read out and given to the input A of the multiplier 3.
The contents of the register un are selected and given. The multiplication result is given to the input C of the adder 4 as follows: AXB=(1.U).On the other hand, a fixed value "0#" is given to the input via the second selection circuit 82, and the addition The result is C+D=(1・u)+O. This result is stored in the accumulator 5, but before that, the value of the calculation result V in step 5> stored in the accumulator 5 is It is written to address D1 of RAM 2 via bus 9.

<Step 7> In this step, the multiplication coefficient α1 from ROM 1 is read out and applied to the input A of the multiplier 30. The first selection circuit 81 selects and applies the content V n-1 of the L register to the one-sided power B. The multiplication result is AXB=[:α1·V n-1] and is given to the input C of the adder 4. On the other hand, as an input, the second selection circuit 82 selects the calculation result [un
) is selected and given.

The addition result is C + = (α, ·vn-4] + [un], and this result is stored in the accumulator 5. On the other hand, at the same time as these additions and multiplications are performed, the auxiliary register 10 The value of fCw, -1 is read out, and the data bus 9f
t is written to the M register.

<Step 8> In this step, the multiplication coefficient α2 is read from the ROM Z and given to the input of the multiplier 3. On the other hand, the content wn-1 of the M register is selected and given to the input B by the first selection circuit 81, and the multiplication result is AXB=[α2'''1-1), and the input C of the adder 4 is is given to .For input,
The calculation result [α1・vn−
1+un') is selected and given. The addition result is C+D=[:α2・”n-+)+Cα1・vn-1+u
n], and the filter output y of equation (4, 2) is obtained.

This result is stored in the accumulator 5.

When a large number of second-order low element sensitivity filters shown in FIG. Can be done at the same time. Therefore, the actual number of operation steps in this case is 7 steps, as indicated by the broken line in FIG.

(Effects of the Invention) As described above in detail, according to the present invention, the output of the multiplier input register of the arithmetic unit and the input of the two inputs of the adder to which the output of the accumulator is connected As a result, the operation of the integrator of the low element sensitivity filter can be processed in one step, and the operation of the arithmetic unit is faster than when calculating the low element sensitivity filter with a conventional arithmetic unit. The number of steps can be reduced. Thereby, a low element sensitivity filter can be realized at the same operating speed as a conventional arithmetic device. By using a low element sensitivity filter, the coefficient word length,
Since the calculation word length can be reduced, the number of calculation units can be reduced.
It is expected that the amount of hardware will be reduced.

Furthermore, since the addition function of the adder is strengthened, the present invention can also be applied to arithmetic devices for digital signal processing that require high-speed calculations other than digital filters.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the configuration of a direct type general filter, and FIG.
FIG. 5 is an explanatory diagram of the prior art, FIGS. 5 and 6 are explanatory diagrams of the operation of the arithmetic unit of FIG. 4, and FIG. 7 is an explanatory diagram of the operation of the embodiment of the present invention. 1.2... Memory, 3... Multiplier, 4... Adder, 5... Accumulator, 6, 7... Register, 8
1゜82...Selection circuit. Patent Applicant: Oki Electric Industry Co., Ltd.Professional 1 of Implementation Point 1 of the Present Invention. Fig. 1Filk 1FlQtz side 11 Explanation of Yakuharaju (2) Fig. 4j #, 4 cOrlk11 first appearance Fig. 5 Vermilion 4 Fig. 1 Long l's slash 1 Lower parting Fig. 6 Unexploded November Movement 1h ¥ - Setup R Month Chart 7 Figure 1, Case Display 1988 Patent Application No. 256298 2, Invention Title Calculation Device 3, Person Making Amendment Relationship with the Case Patent Applicant 6. Contents of amendment (1) On page 3 of the specification (the 2nd formula is amended as follows. un: Xn+b1un-1+b2un-2(2,1
)y = u + alu, -1+a2un-2(2,
2) n n (2) Formula (5.1) on page 6 of the same oath is amended as follows. (3) In the same book, page 8, line 10, "with the register" is corrected to "with the register 5." (4) In the same book, page 8, line 10, it says "with the second selection means." (5) Correct the drawing “Fig. 4” as shown in the attached sheet.

Claims (1)

[Claims] A multiplier (3) to which a multiplicand such as a filter coefficient is given to a first input terminal (A) and a multiplier such as a filter input/output to a second input terminal (B), and a multiplier to be given to the multiplier. The first register (6) and the second register (
7), and first selection means (
81), an adder (4) to which the output of the multiplier is applied to a first input terminal, a third register (5) that stores the output of the adder, an output of the first register, and an adder (4) that stores the output of the multiplier. a second selection means (82) that selects one of the output of the second register, the output of the third register, and a zero value and supplies it to the second input terminal of the adder;