JPH0414173A - Fixed point product sum computing element - Google Patents

Abstract

PURPOSE:To secure an optimum hardware quantity and the computing accuracy by deciding automatically numerical format by an arithmetic unit and at the same time converting automatically the input and output data into a numerical format by the arithmetic unit. CONSTITUTION:The input data are arithmetically shifted to the right by a right shifter 14 by an extent equal to the value of a shift extent register 15. An arithmetic unit ALU 16 performs an operation based on the outputs of the shifter 14 and an accumulator 17. When this arithmetic result has an overflow, this result is shifted to the right by 1 bit and stored in the accumulator 17. At the same time, +1 is given to the value of the register 15 and an input data format is automatically matched with a numerical format under calculation. Meanwhile a data format under calculation is matched with an output data format. In such a constitution, an optimum hardware quantity and the optimum computing accuracy can be secured regardless of the dynamic range, the computing frequency, etc., of the input data. Thus this computing element can be applied to an arithmetic part, etc., of a signal processor to simply deal with various algorithms.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a fixed-point product-sum calculator that can be used in the calculation section of a signal processing device and can be easily applied to various algorithms. It is something.

(Prior Art) Conventionally, regarding an arithmetic device, r 5econd -Ge
nerationJTMS 320 User's G
uide 3 22 to 3-27, and the floating point multiply-accumulator is described in Japanese Patent Laid-Open No. 62-16
It is disclosed in Japanese Patent No. 8228.

FIG. 3 is a block diagram showing the configuration of a conventional fixed-point product-sum calculator. In FIG. 3, the output of multiplier l or the output of input register 2 is selected by multiplexer 3, and the selected output is shifted by shifter 4 by a value specified by a register (not shown). The output of the accumulator 6 and the arithmetic unit 5 (
(hereinafter referred to as ALU).

The output of this ALU 5 is stored in an accumulator 6, and the output of the accumulator 6 is shifted to the left by a left shifter 7 by a value specified by the instruction.

When calculating the inner product of two data strings using a fixed-point product-sum calculator having such a configuration, the following means are required to avoid overflow in the ALU 5.

That is, the output of the multiplier 1 is shifted to the right so that the maximum value of data during the product-sum calculation becomes a value that can be expressed as the output of the ALU. Cumulative addition is performed in this right-shifted numerical format, and finally the result stored in the accumulator is shifted to the left and retrieved in order to return to the original number (1 format).

In addition, as a method other than the above procedure, a configuration is adopted in which overflow is avoided by expanding the bit width of the ALU to be larger than the multiplier output bits so that the data in the middle of the multiply-accumulate operation can be expressed as the output of the ALU. I've been exposed to it.

(Problem to be solved by the invention) However, in the fixed-point product-sum calculator with the above configuration,
It is necessary to conduct a simulation using a general-purpose computer or the like to roughly investigate the dynamic range of input data or data during calculation, and to determine the amount of shift to prevent overflow.

Furthermore, it is not possible to deal with the sudden input of large data.

One possible way to omit or simplify this simulation is to select a shift amount that will not cause overflow no matter what data is input.

This method has a problem in that the calculation accuracy is impaired because the shift amount is set with a margin for the actual input data.

Also, if you extend the ALU width by the number of bits equal to this shift amount, accuracy will be maintained, but if the calculation changes or the dynamic range of the input data changes, the ALU extension bit width cannot be changed. However, there were problems such as insufficient hardware or redundant hardware.

This invention provides a fixed-point multiply-accumulator that solves the problems of the prior art, including the need for simulation, the inability to ensure accuracy, and redundancy in hardware. It is.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a right shifter for arithmetic right shifting input data by the value of a shift amount register in a fixed-point multiply-accumulator, and an output of the right shifter. When an overflow is detected in the result of the calculation, the ALU shifts the result of the calculation by 1 bit to the right and stores it in the accumulator, and adds 1 to the value of the shift amount register, and the output of the accumulator is changed to the shift amount. A left shifter is provided for arithmetic left shifting by the value of the register.

(Function) According to the present invention, since the fixed-point multiply-accumulator is configured as described above, the input data is arithmetic right-shifted by the value of the shift amount register by the right shifter, and the output of this right shifter and the accumulator are The ALU performs calculations based on the output of It acts to automatically adapt the input data format and the data format under operation to the output data format, thus eliminating the above-mentioned problems.

(Example) Hereinafter, an example of the fixed-point product-sum calculator of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment.

In FIG. 1, the output of the multiplier 11 and the output of the input register 12 are input to a multiplexer 13, and are selected and output by the multiplexer 13.

The output of the multiplexer 13 is input to the right shifter 14 as input data to the right shifter 140. This right shifter 14 receives the output of the multiplexer 13 and performs an arithmetic right shift by the contents of the shift amount register 15.

The output of the right shifter 14 and the output of the accumulator 17 are AL
It is configured to be input to U16.

This ALU 16 performs addition and subtraction between the output of the right shifter 14 and the output of the achievator 17, and also detects whether or not the result of the calculation is overflowing.

The calculation result of the ALU 16 is output to the accumulator 17, but when it is detected that the calculation result has overflowed, the calculation result is shifted to the right by 1 bit and stored in the accumulator 17, and the shift amount register 15 +1 is added to the value of .

As mentioned above, the output of this accumulator 17 is
16, and is also output to the left shifter 18.

This left shifter 18 is adapted to perform an arithmetic left shift by the value of the shift amount register 15 and output the result.

Next, the operation will be explained. When performing a product-sum operation, first, both the contents of the accumulator 17 and the contents of the shift amount register 15 are set to O before performing the product-sum operation.

In this state, when data is applied to the two input terminals of the multiplier 11, the multiplier 11 multiplies these two input data and outputs the multiplication result to the multiplexer 13.

The output of this multiplier 11 is selected by a multiplexer 13. When performing a product-sum operation, the multiplexer 13
always selects the output of the multiplier 11 and outputs it to the right shifter 14.

Further, when it is desired to perform an operation on the input register 12, it is necessary to switch the multiplexer 13, but this will be described later.

Now, the case is that the multiplexer 13 selects the output of the multiplier 11. When the multiplexer 13 selects the output of the multiplier 11 and outputs it to the right shifter 14, the right shifter 14 shifts the output of the multiplexer 13 by the amount of shift. The contents of the register 15 are arithmetic shifted to the right, but since the value of the shift amount register 15 is initially O, the data is not affected.

Next, the output of the right shifter 14 and the contents of the accumulator 17 are input to the ALU 16, and the two are added together by the ALU 16. If an overflow occurs as a result of this addition, then
Shift the addition result to the right by 1 bit and transfer it to accumulator 17.
At the same time, the contents of the shift amount register 15 are stored in +
1 and stored in this shift amount register 15.

Thereafter, the ALU 16 will perform calculations in a format in which the position of the decimal point is shifted by 1 bit to the right compared to the previous data format (the data format will be described in detail later).

If no overflow occurs in the ALU 16, the result of addition of the output of the right shifter 14 and the output of the accumulator 17 is stored in the accumulator 17 as is.

Next, the input data of the multiplier 11 is changed and multiplied in the same manner as above, the multiplication result is selected by the multiplexer 13 and output to the right shifter 14, and the output of the right shifter 14 and the output of the accumulator 17 are The operation of adding in the same manner as above and storing the addition result in the accumulator 17 is repeated for the number of data.

However, in the second and subsequent operations, the contents of the shift amount register 15 may not be 0, so the output data of the multiplier 11 is arithmetic right-shifted by the contents of the shift amount register 15 by the right shifter 14.

When the repetition of such operations is completed, the contents of the accumulator 17 are arithmetically shifted to the left by the contents of the shift amount register 15 by the left shifter 18 and output.

By doing so, output data in the same format as the output data format of the multiplier 11 can be obtained without being aware of the data format of the accumulator 17.

Further, when outputting the accumulator 17 and the input register 12 using the ALU 16, the multiplexer 13 is first switched so that the output of the input register 12 is selected by the multiplexer 13 and output to the right shifter 14.

Next, the right shifter 14 shifts the contents of the shift amount register 15 to the right, and the ALU 16 calculates the output of the accumulator 17 and the output of the right shifter 14.

In this way, the data format of the input register 12 can be automatically adjusted to match the data format of the accumulator I7 without being aware of the data format in the accumulator 17. However, input register 1
The data format of 2 must be the same as the output data format of multiplier 11.

Next, the data format handled by the ALUI 6 when performing the above product-sum operation will be explained. FIG. 2 is a diagram showing the data format and the transition of the value of the shift amount register 15.

Assume that the output format of the multiplier 11 is n bits for the integer part and m bits for the decimal part, as shown in FIG. 2(a).

Since the values of the shift amount register 15 and the accumulator 17 are 0 before the product-sum operation is performed, the multiplication results are not shifted in the ALU 16 and are stored in the accumulator 17 in the formant shown in FIG. 2(a). Ru.

Next, assume that the output of the multiplier 11 in the next cycle is added to the value of the accumulator 17 in the ALUI 6, and that the addition result overflows.

At this time, the shift amount register 15 is increased by +1, and the ALU 16 shifts the operation result by 1 bit to the right.
It is stored in the accumulator 17.

The data format of the accumulator 17 in this case is as shown in FIG.

In this way, when the product-sum operation is repeated, the data format in the middle is as shown in Figure 2(c), where the integer part (n
+3) bits, and the fractional part (m-3) bits. The value of the shift amount register 15 at this time is "3j".

The output of the multiplier 11 in the next cycle is shifted to the right by 3 bits by the right shifter 14 by this shift amount register 15, and A
The input to the LU 16 has the same data format as the accumulator 17, and calculations are possible.

In this way, it is assumed that the data format of the accumulator 17 when the repetition of the product-sum operation is completed becomes the integer multiple (n+8) bits and the decimal part (m-8) bits as shown in FIG. 2.

The value of the shift amount register 15 at this time is "8". When outputting the data of the accumulator 17 having this format, the shift amount register 15 causes the left shifter 8 to shift the data to the left by 8 bits. The data format is as shown in FIG. 2(e).

The format shown in FIG. 2(e) is the same as the output format of the multiplier 11.

In this way, the product-sum calculation result can be obtained in the same format as the output of the multiplier 11 without being aware of changes in the data format during the product-sum calculation.

Further, when performing an operation with other data during the product-sum operation, first, the multiplexer 13 is switched so that the output of the input register 12 is selected.

This input register 12 stores data in the same format as the output of the multiplier 11. Assuming that the current data format of the accumulator 17 is as shown in FIG.
The bits are shifted to the right and the data form is the same as that of the accumulator 17, allowing calculation.

Therefore, regardless of the data format of the current accumulator 17, the input register 12 is
If the same data formant as the output of is stored, calculations with the accumulator 17 are possible.

(Effects of the Invention) As explained in detail above, according to the present invention, the ALU automatically determines the numerical format, and the input data and output data are automatically converted into the ALU numerical format. Therefore, it is expected that the optimal amount of hardware and calculation accuracy will be secured regardless of the dynamic range of input data, the number of calculations, etc.

Therefore, if used in the calculation section of a signal processing device,
It can be easily applied to various algorithms.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the fixed-point product-sum calculator of the present invention, and FIG. 2 shows changes in the value of the shift amount register and the data format of the accumulator to explain the same embodiment. The explanatory diagram, FIG. 3, is a block diagram of a conventional fixed-point product-sum calculator. 11... Multiplier, 12... Input register, 13...
- Multiplexer, 14... Right shifter, 15... Shift amount register, 16... ALU, 17... Accumulator, 18... Left shifter. 3@M block diagram of the present invention Fig. 1 Value of register 9: 6°

Claims (1)

[Claims] (a) a multiplexer that selects data from a multiplier and an input register; (b) a right shifter that arithmetic shifts the output of this multiplexer to the right by the value of a shift amount register; An operation is performed using the output of the shifter and the output of the accumulator, and if the operation result overflows, the operation result is shifted to the right by 1 bit and stored in the accumulator, and the value of the shift amount register is +
(d) a left shifter that performs arithmetic left shift on the output of the accumulator by the value of the shift amount register and outputs the result.