JPS59194242A - Digital multiplying and cumulative adding device - Google Patents

Abstract

PURPOSE:To speed up operation and reduce the scale of a circuit by providing two registers wherein one of partial addition results of a multiplying process and a cumulative addition result are accumulated, and allowing a common adder to perform those two kinds of arithmetic. CONSTITUTION:The 1st digital signal sequence X as a multiplier and the 2nd digital signal sequence Y as a multiplicand are inputted. The signal sequence X is divided into a 16-bit high-order part data A and a low-order part data B, and the sequence Y is also divided into data C and D similarly. The 1st multiplier 11 calculates P1=BXC, the 2nd multiplier calculates P2=AXD, and the 3rd multiplier calculates P3=BXC. In this case, while multiplexers 21 and 22 are switched from PA and PB to sides of registers 24 and 25, the 1st adder 15 enters the next adding operation, so the multipliers 11-13 also enter the next multiplying operations, thereby shortening the multiplication period.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a digital multiplication method in which two digital signal sequences consisting of parallel multi-bit data are multiplied for each data as a multiplier and a wave multiplier, and the multiplication results are cumulatively added. The present invention relates to a cumulative addition device.

[Technical background of the invention and its problems]

When the filter processing that is generally performed on analog signals is expressed using a digital circuit, a cyclic or acyclic filter consisting of a delay circuit 17 multipliers 2 and 3, an adder 3, etc. is used as shown in Figure 1. By connecting several stages vertically and horizontally, algebraic arithmetic processing is performed on the input digital signal. Here AOI~A 0+
1 + AIl ~ Aln + A21 ~ A 2n + B
+t~BIllr 821~B2n are coefficients determined by the required filter characteristics, so in actual calculations, they are treated as multipliers in multiplier 2, and are not handled as input digital signals or in delay circuit 1 or adder 3. Multiplication is performed using the digital signal processed as the multiplicand.

Figure 2 shows an example in which the basic configuration of the digital filter shown in Figure 1 is actually configured in hardware. By performing the three processes of multiplication, addition, and delay using time-sharing processing, high-order filters can be achieved with a small-scale configuration. This makes it possible to realize a filter. That is, the input digital signal as the multiplicand input or a signal delayed by the delay memory 4 by a time corresponding to the sampling period thereof is supplied to the multiplier 5, and is multiplied by the digital signal corresponding to the coefficient as the multiplier input. Then, the multiplication result is sent to adder 6. - The configuration is such that it is added to the cumulative addition result that is the output of the register 7, outputs a new cumulative addition result, and is caused to be held in the register 7.

Input signal supply 1 multiplication including such delay.

By repeating the series of cumulative force multiplication operations at a constant cycle (multiplication cycle), the speed can be increased. In other words, assuming that m multiplications can be performed within the sampling period of a human-powered digital signal, the calculation for one stage of fill in Figure 1 includes five multiplications, so in the end it is m / 5 stages. This means that the filter operation can be performed within 1υ of the sample value ◇ Since the actual operation in the mind deals with a finite word length (bi, 1, number), some deterioration of the filter characteristics is unavoidable.
This becomes a problem as the filter becomes higher-order. For this reason, the operations of the multiplier 5, adder 6, etc. in FIG.
For example, a large number of bits, such as 24 bits or 32 bits, is required. However, the limit of IS multipliers that are currently in practical use is about 16 bits, so it may be virtually impossible to achieve desired filter characteristics with the configuration shown in FIG. Therefore, a method has been considered in which a plurality of 12-bit or 16-bit multipliers are used in combination to perform multiplication with a larger number of bits, such as 24 bits or 32 bits.

FIG. 3 shows an algorithm for performing 32-bit x 32-bit multiplication using a 16-bit multiplier. Let the multiplier be X and the multiplicand be Y, and their product f! Let f:P.

Also, let's use X't-32 bits of parallel data, and convert this into 16
Each bit is divided into upper part data and lower part data, and these are designated as A and B, respectively. Similarly, Y is divided into upper part data C' and lower part data D by 16 bits. And p=x*y as P! =A*C*P2 =A*D.

It is divided into four partial products, P3 = B * C and P4 = B * D, and calculated using four 16-bit multipliers.

The multiplication result corresponding to each of these partial products becomes 32-bit data. If these are added in such a way that P=2*P1+2*(P2+P3)+P4, ff1p is obtained as 64-bit data.

FIG. 4 shows the configuration of a conventional digital multiplication/accumulation addition device implemented in hardware according to the algorithm shown in FIG. That is, four 16-bit multipliers 11912, 13
．． 14 to calculate the partial product p 1 + P 2 + P 3
, P 4 as 32-bit data, P 2
+P3 is added by a 32-bit adder 15, and the data of P2+P3 is added to a 64-bit adder 16.
, and aligns the data with the data of "I r P4 and layers it with /JlI to obtain P = X * Y as 64-bit data. Then, in the same way as in FIG. By cumulatively adding P using
Multiply 39 - Obtain the cumulative addition result ACCOUT.

FIG. 5 shows a time chart showing the operation of FIG. 4, where Ftlz+t3 is the calculation time of each of the boosters 15°, 16.17. In the configuration shown in FIG. 4, due to these times, there is a limit to the shortening of the multiplication period. To give a specific numerical example, tl-1-t2-1-ta is at least 90 assuming high-speed adders 15 to 12 are used.
ns + output delay time of multipliers 11 to 14 and register 1
Considering the margin of the maximum value of 'lr near 7III7L, such as the hold-in time of 8, about 150 ns is required.

On the other hand, high-speed multipliers can be realized up to about 100 ns. Therefore, although the multiplication period of the multipliers 11 to 14 itself can be shortened to about 100 ns, in reality it is limited by the total calculation time of the adder. Especially when considering the digital filter mentioned above, the number of stages of the filter that can be realized is determined by the multiplication period, so the difference in the multiplication period of several Ions is actually very large, and there is a situation where the required filter characteristics cannot be achieved. It is also connected to

Another disadvantage of the configuration shown in FIG. 4 is that the circuit scale is relatively large because a large number of adders are required.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital multiplication/accumulation addition device that can operate at high speed and reduce the circuit scale.

[Summary of the invention]

In this invention, two registers are provided to store one of the partial addition results in the multiplication gross and the cumulative addition result, and these two types of addition operations 31 are performed alternately using a common adder. 0 In other words, the present invention provides the first
．． In a device that multiplies a second digital signal raw material for each data and calculates the multiplication results by cumulative calculation, the first a multiplier of
a second multiplier that multiplies the upper part data of the digital signal series by the lower part data of the second digital signal series; and the lower part data of the first digital signal series and the lower part data of the second digital signal series. a third multiplier that multiplies the upper part data; a first adder that adds the output of the second multiplier and the output of the third multiplier; a second adder for performing t710 arithmetic with the output of the first multiplier and for cumulative addition; and first and second registers for temporarily accumulating all the outputs of the second adder. ,,The output of the first adder and the output of the first multiplier are matched in order and are used as two inputs of the second adder, and the output of the second 71[] multiplier at that time is First. The first mode is to accumulate in one of the second registers, the output of the first register and the output of the second register are the two inputs of the second adder, and the output of the second adder at that time is Set the output to 1st. It is characterized in that the second mode in which the storage is stored in the other of the second registers is alternately switched.

In addition to the first to third multipliers, in addition to the first to third multipliers, the present invention further includes a fourth multiplier that multiplies the lower part data of the first and second digital signal series. It will be done.

In that case, the output of the fourth multiplier is combined in order with the output of the first multiplier, and this combined output is combined in order with the output of the first adder in the second adder. will be added.

〔Effect of the invention〕

According to this invention, as soon as the first mode, which is one partial addition in the multiplication process, is completed and the second mode, which is cumulative addition, is entered, the next multiplication can be started.
The calculation time for the daily calculation is effectively inserted into the multiplication period, and the actual multiplication period, that is, the repetition period of multiplication and accumulation addition, is shortened, and the speed is significantly increased. Therefore, when considering the application to digital filters, there is an effect that the filter characteristics that can be realized are expanded.

In addition, the multi-bit adder, which generally occupies a large number of elements, has two
Since only one register is required, the circuit scale of the entire device can be considerably reduced even considering the addition of one register, which can contribute to cost reduction.

[Embodiments of the invention]

FIG. 6 shows the first embodiment of this invention, and except for the fact that there are three multipliers, the basic functions are as follows:
Similar to the one in the figure, PA in the multiplication process of P
The configurations for +Pn partial addition and cumulative addition are different.

That is, the first digital signal sequence X serving as a multiplier,
A second digital signal sequence Y serving as a multiplicand is input. In the case of a digital filter, X is constant data that provides a constant coefficient, and Y is a sample value series sampled at a certain period, and in this example, it is assumed that both are parallel 32-bit data. As explained in FIG. P1=A*C, P2=AID in the second multiplier 12, and P3 in the third multiplier 13
Each partial product of =B*C is calculated. These are not
- Both are 32-bit data.

The output data P1 of the first multiplier 11 is %P1 in the upper 32
bits, and the lower 32 bits are all "0#" 64
The bit data PA is applied to one input of the first multiplexer 21.

On the other hand, the second. Output data P2 of third multiplier 12.13
+P3 is added by the first adder 15 having a 32-bit configuration, resulting in 32-bit partial addition data P2+P3. This data P2+P3 is given to one input of the second multiplexer 22 as 64-bit data Pn in which P2+P3 is the lower 32 bits and the upper 32 bits are all NO.
The output of the first . second register 24
．． 25.

1st. The output of the second register 24.25 is the same as that of the first and second registers.
It becomes the other input of the multiplexer 21, 22 of.

Next, the operation of this embodiment will be explained using the quimchard shown in FIG. In FIG. 7, MPYINCK and MPY OUT CK indicate the input/output clocks of multipliers 11 to 13, MPY OUT indicates the output of multipliers II to 13, and AD♂*ADR reduction first and second adders. 15
．． 23, MPX OUT indicates the output of multiplexer 21.22, RG I CK , RG2
CK indicates the clock for starting the accumulation of registers 24 and 25, and RG 10UT and RG 2QUT are the clocks for starting the accumulation of registers 24 and 25.
．． 25 output is shown.

1st. By inputting data Xo and Yo of the second digital signal series X and Y, the multiplier 11
When the partial product data P1 to P3 are output from ~13 and partial addition data PA + Pn is generated, the multiplexers 21 and 22 select PA r by the select signal SEL.
Ps is selected and sent to the force α calculator 23. As a result, the adder 23 calculates PA+P11, that is, Z(,=Xo *Yo), and this data Zo is stored in the register 24 by the clock RGICK.

Next, the multiplexers 21 and 22 select the select signal SEL.
switches to the register 24 and 25 side, register 2
The data 2° stored in the register 25 and x, *y that had already been stored in the register 25.

The multiplication cumulative addition data w-1 up to and including the data w-1 are sent to the adder 23. As a result, the adder 23 now performs cumulative addition for z, -4- nights, and outputs the result as new multiplication cumulative addition data tA)o.

This data wo is simultaneously accumulated in the register 25 by the clock RG 2 CK, and in preparation for the next cumulative addition, the multiplexers 21 and 22 are switched from the PAIPB side to the register 24e25 side, and at the same time the first adder 15
can move on to the next addition operation, so multiplier 1
K f so that 1 to 13 can also move on to the next multiplication operation.
As a result, the multiplication period can be shortened. That is, as is clear from the time chart in FIG. 7, the calculation time that constrains the multiplication period is the calculation time tl of the first adder 15, the selection time t4 of the multiplexers zz and 22, and the calculation time t4 of the second adder 23. Computation time t2
The sum accounts for the majority, and this is a reduction of more than 20 ns compared to 90n3 in the conventional configuration shown in FIG.

Furthermore, as for the circuit configuration, by reducing the number of 64-bit daily counters by one, the number of registers increases by one, and even taking into account that a multiplexer is required, the actual scale is reduced.

FIG. 8 shows a second embodiment of the invention, where P,=
By adding a fourth multiplier 14 that obtains the partial product of B*D, higher precision calculation is made possible.

In this case, in the data of P4, Pl is the upper 32 bits vP<
is combined with Pl so that it becomes the lower 32 bits, resulting in two pieces of 64-bit data. FIG. 9 is a time chart showing the operation of FIG. 8, and is the same as FIG. 7 except that P4 is added to MPYOUT.

The present invention is not limited to the above-described embodiments, and can be implemented in various ways. For example, by using 3-8 TATE for the output buffer sections of multipliers, adders, registers, etc., and switching the state as appropriate. , the multiplexer can also be omitted. In that case, it is possible to further reduce the number of times.In addition, the method of dividing each data of the input digital signal sequence does not necessarily have to be divided into upper and lower halves, but the content and nature of the data Any division ratio can be selected depending on the situation.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the basic configuration of a digital filter, Fig. 2 is a block diagram when the above digital filter is implemented by time-division processing, and Fig. 3 is a 16-bit x 16-bit filter.
Bit multiplication q: Partial product of 32 bits x 32 bits B' (=A diagram showing the algorithm to be carried out. Fig. 4 is a block diagram of a conventional digital multiplication accumulative addition device constructed using the algorithm of Fig. 3. , 5M is a time chart showing its operation, FIG. 6 is a configuration diagram of the first embodiment of the present invention, FIG. 7 is a time chart showing its operation, and FIG. 8 is a time chart of the second embodiment of the present invention. The configuration diagram of the embodiment, and FIG. 9 is a tight chart showing its operation.
adder, 21.22... multiplexer, 23...
-Second adder, 24.25...first. Second register.

Claims (2)

[Claims] (1) The first data consists of parallel multi-bit data. In a device that multiplies a second digital signal series for each data and cumulatively adds the multiplication results, the first a multiplier; a second multiplier that multiplies the upper part data of the first digital signal series by the lower part data of the second digital signal series; a third multiplier that multiplies the upper part data of the digital signal sequence;
a first adder for adding the output of the second multiplier and the output of the third multiplier; a cumulative addition for adding the output of the first adder and the output of the first multiplier; a second adder for temporarily storing the output of this second adder; and a first adder for temporarily storing the output of this second adder. and a second register, the output of the first adder and the output of the first multiplier are matched in order and used as two inputs of the second adder, and the output of the second adder at that time is Set the output to 1st. The first monid accumulated in one of the second registers, the output of the first register, and the output of the second register are the two inputs of the second adder, and the output of the second adder at that time is Output all lights 1. A digital multiplication accumulation addition device characterized in that the second mode of accumulation in the other of the second registers is alternately switched. (2) The first data consists of parallel multi-bit data. In a device that multiplies a second digital signal series for each data and cumulatively adds the multiplication results, the first a multiplier; a second multiplier that multiplies the upper part data of the first digital signal series by the lower part data of the second digital signal series; A third multiplier multiplies the upper part data of the digital signal series by the lower part data of the first digital signal series, and the third multiplier multiplies the lower part data of the first digital signal series by the lower part data of the second digital signal series. a fourth multiplier that is coupled in order with the output of the first multiplier; a first adder that adds the output of the second multiplier and the output of the third multiplier; A second Calo calculator is provided for calculating the output of the first adder and the combined output of the first and fourth multipliers, and for cumulative addition, and temporarily converting the output of the second power calculator. 1. a second register, the output of the first multiplier and the combined output of the first and fourth multipliers are matched in order and used as two inputs of the second adder; The output of the adder of the first . The first mode is to accumulate in one of the second registers, and the output of the first register and the output of the second register are the two inputs of the second addition: the second addition at that time. The output of the device is the first. the second one that accumulates in the other of the second registers
A digital multiplication accumulator which is characterized in that the modes are alternately switched.