JP2765516B2 - Multiply-accumulate unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a product-sum operation unit, and more particularly to a product-sum operation unit having a CSA (Carry Save Adder: Carry Save Adder) tree for performing a fixed-point product-sum operation.

[0002]

2. Description of the Related Art Conventionally, general-purpose microprocessors employed in personal computers, engineering workstations, and the like have a signed integer multiply instruction in an instruction set.

In recent years, it has become necessary to perform so-called digital signal processing at high speed in order to compress and decompress voice, audio or image.

Therefore, in recent microprocessors, in addition to the above-mentioned existing instruction set (an instruction set having a signed integer multiplication instruction), a signed fixed-point multiply-accumulate operation frequently used in digital signal processing is performed. It is becoming common to add a signed fixed-point multiply-accumulate operation instruction to the instruction set.

[0005] By adding a signed fixed-point multiply-accumulate operation instruction to the instruction set of the microprocessor, the following advantages are obtained. That is, conventionally, the processing performed by two instructions of the signed multiplication instruction and the signed addition instruction can be performed only by the signed fixed-point multiply-add instruction (that is, by one instruction). Digital signal processing can be significantly speeded up.

The present invention is directed to a product-sum operation unit (a product-sum operation unit capable of performing a fixed-point product-sum operation with a sign) built in such a microprocessor (a microprocessor having enhanced digital signal processing performance). It is assumed that.

Here, a multiplicand X with a sign of 33 bits, a signed multiplier Y with a sign of 32 bits, and an addition value Z also with a sign of 32 bits are input to the multiply-accumulate unit targeted by the present invention. Shall be performed. However, the multiplicand X is a value obtained by sign-extending an arbitrary 32-bit signed number to a 33-bit length, or an arbitrary positive number having a 33-bit length.

In this kind of product-sum operation unit, the following processing is required (see FIG. 4). It is assumed that the fixed-point number representation employed in the product-sum operation unit according to the present invention is an expression in which a decimal point is fixed on the most significant bit side.

[0009] Signed multiplication of the multiplicand X and the multiplier Y is performed to obtain an intermediate result having a length of 65 bits.

In the upper 33 bits of the intermediate result,
Signed addition is performed on a 33-bit length value obtained by sign-extending the addition value Z by 1 bit, and a 65-bit length result R is output.

As a "multiplication method" in this kind of multiply-accumulate unit, a partial product is generated by a Booth decoder from a part of the multiplier Y and the entire multiplicand X, and the generated partial products are CSA. A method of adding by a tree is general.

The method of constructing the booth decoder is described in "Principles of Cimos VSI Design, A Systems Perspective, Second Edition" by Neil HE. Weste et al.
VLSI DESIGN, A Systems Per
selective, Second Edition),
Addison-Wesley Publishing
Company, ISBN 0-201-53376
-6, pp. 547-555 ".

Here, the basic concept of the Booth decoder will be described (Equations in this concept and FIGS. 5 and 6 will be referred to in the description of embodiments of the present invention described later).

Now, it is assumed that a product P (P = X × Y) of a signed 33-bit multiplicand X and a signed 33-bit length multiplier Y is to be obtained.

When the bits of the multiplicand X and the multiplier Y (the i-th bit (i is 0 or a positive integer) when the least significant bit is the 0th bit) are denoted by x _i and y _i , respectively, the multiplicand X and the multiplier Y is represented by the following equation.

[0016]

(Equation 1)

When the multiplier Y is divided into three bits by a Booth decoder as follows, the multiplier Y can be rewritten as follows.

[0018]

(Equation 2)

Y _j defined by equation (4) (j is −1,0
Or a positive integer) is -2,-by the combination of three bits of each bit (including y- ₁ ) of the multiplier Y.
It takes one of the values 1, 0, 1, and 2. That is, as shown in FIG. 5, y _{(2j + 1)} , y _2j , and y
All combinations of the three bits of _(2j-1) (0 or 1
), Only one of the above five values is obtained.

The product P to be obtained is expressed by the following equation.

[0021]

(Equation 3)

Here, if P _j = X · Y _j (6), this P _j can be generated by the method (generation method) shown in FIG. 6 for each Y _j value. That is,
If the value of Y _j is negative, by adding the c _j = 1 inverts each bit x _i of the multiplicand X, the 2's complement of the multiplicand X is determined.

When this P _j is written in bit units, the following equation is obtained (for P _ji and c _{j in} the equation, see FIG. 6).

[0024]

(Equation 4)

The multiplicand X is 33 bits long and Y _j is-
2, 1, 0, 1, or 2, P _j is 34 at the maximum.
It can be bit length.

Next, the concept of adding the addition value Z to the product P obtained as described above and obtaining the result R of the product-sum operation will be described.

The addition value Z having a fixed-point fixed-point 32-bit length is represented by the following equation when each bit is represented by z _i and sign extension of one bit is performed by setting z ₃₂ = z ₃₁ .

[0028]

(Equation 5)

Therefore, the result R of the product-sum operation is expressed by the following equation from equations (5), (7) and (8).

[0030]

(Equation 6)

The two's complement conversion of the negative part N in the equation (9) is performed as in the following equation so that it can be handled by the adder. Here, when the multiplicand X and the multiplier Y are the negative maximum value having a 32-bit length and the addition value Z is the positive maximum value, the result R of the product-sum operation has a maximum length of 65 bits. 65
Performed in bit length.

[0032]

(Equation 7)

Using this N, the result R of the product-sum operation is expressed by the following equation.

[0034]

(Equation 8)

From the equation (13), in order to obtain the result R of the product-sum operation, it is necessary to generate all the items shown in the equation (13) using the Booth's decoder and add them in the CSA tree. I understand.

Next, the configuration and operation of a conventional product-sum operation unit (fixed-point product-sum operation unit) based on such a concept will be described with reference to FIGS.

The product-sum operation unit shown in FIG. 7 is an example of this type of product-sum operation unit, and includes a first selector 101, a second selector 102, a third selector 103, and a fourth selector 104, booth decoder 105, and 11 inputs C
SA tree 106 and first pipeline register 1
07, a second pipeline register 108, a carry propagation adder 109, and a sign extender 110.

In the product-sum operation unit having the configuration shown in FIG. 7, the result R of the product-sum operation is basically calculated according to the above-mentioned concept (Equation (13)).
), The amount of hardware is reduced by dividing and generating the partial product a plurality of times. A technique similar to such a product-sum operation unit is disclosed in Japanese Patent Application Laid-Open No. 4-205624 (series-parallel type multiplier). However, JP-A-4-20562
In the serial / parallel type multiplier having the configuration disclosed in Japanese Patent Application Laid-Open No. 4 (1999) -1995, a single value after passing through the carry propagation adder following the CSA is held as an intermediate result of the partial product addition. In the configuration of the product-sum operation unit shown in FIG.
The operation is speeded up by holding a set of half sum and half carry, which are the outputs of SA.

Next, the operation of the product-sum operation unit shown in FIG. 7 will be described with reference to FIGS.

The product-sum operation unit shown in FIG. 7 divides the generation and addition of partial products into two operations of a "first operation step" and a "second operation step" in order to reduce the amount of hardware. Do it.

First, the operation at the time of executing the operation in the first operation step will be described.

In the first operation step, the multiplicand X and the lower 16 bits of the multiplier Y are multiplied to generate the operation result (intermediate operation result) of the first half of the operation (first operation step).

The first selector 101 has an operation step switching bit (1-bit information indicating whether to perform the operation of the first operation step or the operation of the second operation step).
In this case, the calculation in the first calculation step is performed), and the lower 16 bits of the multiplier Y are selectively output.

Further, the second selector 102 selects and outputs a second constant with reference to an operation step switching bit indicating that the operation of the first operation step is performed. Here, the second constant is ^1.232 (j in Expression (13).
^{= 1 · 2 (32 + 2j} ) in the case of 0) and refers to a number indicating the ^{_{c n (1 · 2 31)}} ( see FIG. 8).

Further, the third selector 103 selects and outputs a constant (constant of value 0) indicating all bits 0 with reference to the operation step switching bit indicating that the operation of the first operation step is performed. .

In addition, the fourth selector 104 selects and outputs a first constant with reference to an operation step switching bit indicating that the operation of the first operation step is performed. Here, the first constant is c _z (1 ·
2 ³¹ ), c ₁₅ · 2 ³⁰ (c _j · 2 ^2j when j = 15) and c ₇ · 2 ¹⁴ (c _j · 2 ^2j when j = 7) (FIG. 8). reference).

The booth decoder 105 receives the multiplicand X and the output of the first selector 101, and cuts out the output of the first selector 101 to shift the start position from the most significant bit to the lower bit by two bits at a time. An eighth partial product generator, a seventh partial product generator,
A sixth partial product generator, a fifth partial product generator, a fourth partial product generator, a third partial product generator, a second partial product generator,
And the first partial product generator, and from these values and the value of the multiplicand X, from the eighth partial product generator to the first partial product generator, the eighth partial product to the first partial product ( Eight partial products P when multiplicand X is multiplied by lower 16 bits of multiplier Y
_{7 to} P ₀ ).

Each partial product has a value obtained by multiplying the multiplicand X by -2, -1, 0, 1, or 2 as shown in FIG. 5, and is generated as shown in FIG. A bit indicating ^{1.2 (32 + 2j)} (j = 1 to 8) in the equation (13) is added to the partial products P _{0 to} P _7, and the equation (1) is added to the partial products P _{1 to} P _7.
A bit indicating c _j · 2 ^2j (j = 0 to 6) in 3) is added (see FIG. 8. The information represented by the bit added to the partial product in this manner is called “additional bit information”. ). Here, the value of c _j is calculated based on the value of Y _j in FIG.
Is determined as shown in FIG.

The 11-input CSA tree 106 includes the eight partial products (the partial products generated by the first to eighth partial product generators in the Booth decoder 105).
Including the additional bit information), the output of the second selector 102, the output of the third selector 103, and the output of the fourth selector 104 as first to eleventh inputs.
They are added, and the addition result is output as a set of a half sum and a half carry.

The half sum and the half carry are held in the first pipeline register 107 and the second pipeline register 108, respectively, as the operation result of the first operation step.

FIG. 8 shows a list of each input (bit string) and each output (half-sum and half-carry bit string) of the 11-input CSA tree 106 in the first operation step.

Second, the operation at the time of executing the calculation in the second calculation step will be described.

In the second operation step, the multiplicand X is multiplied by the upper 17 bits of the multiplier Y, and the result of the multiplication is multiplied by the first
Is added to the addition value Z to generate the final product-sum operation result R.

The sign extender 110 calculates 1
Performs bit sign extension. Thus, the added value Z is 33
It becomes bit length.

The first selector 101 has an operation step switching bit indicating that the operation of the second operation step is to be performed (the information of the operation step switching bit at the time of transition from the first operation step to the second operation step). Is switched), and the higher 17 bits of the multiplier Y are selectively output.

Further, the second selector 102 refers to the operation step switching bit indicating that the operation of the second operation step is to be performed, and makes the second pipeline register 1
The upper 35 bits of the value held in 08 (half carry of the operation result of the first operation step) are selectively output.

Further, the third selector 103 refers to the operation step switching bit indicating that the operation in the second operation step is to be performed, and outputs the output of the sign extender 110 (the sign-extended added value Z). Select output.

In addition, the fourth selector 104 refers to the operation step switching bit indicating that the operation of the second operation step is to be performed, and refers to the value held in the first pipeline register 107 ( The upper 34 bits of the half-sum of the operation result of the first operation step are selectively output.

The booth decoder 105 receives the multiplicand X and the output of the first selector 101, and cuts out the output of the first selector 101 to shift the start position from the most significant bit to the lower bit by two bits at a time. An eighth partial product generator, a seventh partial product generator,
A sixth partial product generator, a fifth partial product generator, a fourth partial product generator, a third partial product generator, a second partial product generator,
And the first partial product generator, and from these values and the value of the multiplicand X, from the eighth partial product generator to the first partial product generator, the eighth partial product to the first partial product ( Eight partial products P obtained by multiplying the multiplicand X and the higher 17 bits of the multiplier Y
_{15 to} P ₈ ).

Each partial product has a value obtained by multiplying the multiplicand X by -2, -1, 0, 1, or 2 as shown in FIG. 5, and is generated as shown in FIG. It should be noted that the partial products P _{8 to} P ₁₄ have a value of 1.2 ^{(32 + 2j)} (j = 9 to 15) in the equation (13).
Are added, and the partial products P _{9 to} P ₁₅ are given by the formula (1).
A bit indicating c _j · 2 ^2j (j = 8 to 14) in 3) is added (see FIG. 9).

The 11-input CSA tree 106 includes the eight partial products (the partial products generated by the first to eighth partial product generators in the Booth decoder 105).
Including the additional bit information), the output of the second selector 102, the output of the third selector 103, and the output of the fourth selector 104 as first to eleventh inputs.
They are added, and the addition result is output as a set of a half sum and a half carry.

Carry propagation adder 109 adds the following value and the following value to obtain and output a single result R (result R of the product-sum operation) (the following values and Carry propagation addition). A 49-bit half-sum (half-sum obtained in the second operation step) and the lower 16 bits of the half-sum obtained in the first operation step (lower value of the value held in the first pipeline register 107) 8 and 9 (see FIGS. 8 and 9). A half carry having a length of 48 bits (a half carry obtained in the second operation step) and a lower part of the half carry obtained in the first operation step 15 bits (lower 1 of the value held in the second pipeline register 108)
5 bits) (see FIGS. 8 and 9)

FIG. 9 shows a list of each input (bit string) and each output (half-sum and half-carry bit string) of the 11-input CSA tree 106 in the second operation step.

Each item in the equation (13) is always included in the input bit string in FIG. 8 or FIG. Therefore, in either the first operation step or the second operation step, the value of each item in the equation (13) is set to 11 input CSA.
The data is input and added by the tree 106.

[0065]

In the above-described conventional product-sum operation unit (product-sum operation unit as shown in FIG. 7), the entire sign-extended addition value Z is added in the second operation step. Therefore, in the second operation step, it is necessary to input and add 11 values in the CSA tree (see FIG. 9), and it is necessary to prepare a CSA tree having 11 inputs. CSA
When the number of tree inputs increases, the configuration of the CSA tree becomes complicated, the amount of hardware for realizing the CSA tree increases, and the delay of the operation using the CSA tree (the product due to the increase in the number of adder stages). However, there is a problem that the operating speed of the entire sum operation unit may be reduced.

In view of the above, an object of the present invention is to provide a bit divider for dividing the sign-extended addition value Z into two parts, thereby reducing the number of inputs to the CSA tree and reducing the amount of hardware. It is an object of the present invention to provide a multiply-accumulate unit which requires only a small amount of data and can operate at high speed.

That is, an object of the present invention is to divide an addition value Z sign-extended to a 33-bit length into upper 15 bits and lower 18 bits by a bit divider, and The 18 bits are concatenated with the first constant and provided to the CSA tree in the first operation step, and the upper 15 bits of the sign-extended addition value Z are concatenated with the upper 34 bits of the half sum in the first operation step. In the second operation step, the number of inputs to the CSA tree is reduced by providing the data to the CSA tree.

[0068]

According to the present invention, a multiply-accumulate unit according to the present invention comprises:
A signed multiplicand X having a length of 33 bits, a signed multiplier Y having a length of 32 bits, and an addition value Z having a length of 32 bits are input.
In a product-sum operation unit that outputs X × Y + Z, which is the sum of these products, as a result R, a sign extender that performs one-bit sign extension on the addition value Z, A bit divider for dividing into upper 15 bits, a lower 16 bits of the multiplier Y are selectively output in the first operation step, and a higher 17 bits of the multiplier Y are output in the second operation step.
A first selector for selecting and outputting a bit; and a first operation step for selectively outputting a second constant. In the second operation step, the upper 35 bits of the value held in the second pipeline register are read. A second selector for selecting and outputting;
In a first operation step, a value obtained by connecting the lower 18 bits of the output of the bit divider and a first constant is selected and output;
A second selector for selecting and outputting a value obtained by connecting the upper 15 bits of the output of the bit divider and the upper 34 bits of the value held in the first pipeline register; While shifting the output of the first selector from the most significant bit to the lower bit by two bits from the most significant bit, the values extracted in units of 3 bits are used as the values of the eighth partial product generator, the seventh partial product generator, and the sixth partial product generator. , A fifth partial product generator, a fourth partial product generator, a third partial product generator, a second partial product generator, and a first partial product generator, From these values and the value of the multiplicand X, the eighth partial product, the seventh partial product, the sixth partial product, the fifth partial product, the fourth partial product, the third partial product, and the second partial product A Booth decoder for generating a product and a first partial product; First partial product generated Te, the second
, The third partial product, the fourth partial product, the fifth partial product, the sixth partial product, the seventh partial product, the eighth partial product, the output of the second selector, A 10-input CSA tree for adding the output of the third selector and the additional bit information group, and the 10-input CSA tree in the first operation step
A first pipeline register for holding a half sum of an output of the tree, and a second pipeline register for holding a half carry of an output of the 10-input CSA tree in a first operation step; A value obtained by concatenating the half sum output by the 10-input CSA tree in the second operation step and the lower 16 bits of the half sum held in the first pipeline register in the first operation step; and The half carry output by the 10-input CSA tree in the operation step and the second pipeline in the first operation step.
A carry propagation adder that performs carry propagation addition on a value obtained by connecting the lower 15 bits of the half carry held in the register.

[0069]

In the multiply-accumulate unit of the present invention, a signed multiplicand X having a length of 33 bits, a signed multiplier Y having a length of 32 bits, and an addition value Z having a length of 32 bits are inputted, and X, which is the product sum of these,
In a product-sum operation unit that outputs × Y + Z as a result R,
The sign extender performs one-bit sign extension on the addition value Z, the bit divider divides the output of the sign extender into lower 18 bits and upper 15 bits, and the first selector performs the first operation step. Selects and outputs the lower 16 bits of the multiplier Y, selects and outputs the upper 17 bits of the multiplier Y in the second operation step, and selects the second 16 bits in the first operation step.
In the second operation step, selects and outputs the upper 35 bits of the value held in the second pipeline register. In the first operation step, the third selector outputs the output of the bit divider. And outputs a value obtained by concatenating the lower 18 bits of the first constant with the lower 15 bits of the output of the bit divider and the upper 34 bits of the value held in the first pipeline register in the second operation step. A value obtained by concatenating the bits is selected and output, and the Booth decoder cuts out the output of the first selector and shifts the start position from the most significant bit to the lower bit by two bits at a time in units of three bits, and outputs the value extracted in the eighth bit. Partial product generator, seventh partial product generator,
A sixth partial product generator, a fifth partial product generator, a fourth partial product generator, a third partial product generator, a second partial product generator,
And the values supplied to the first partial product generator and these values and the value of the multiplicand X to calculate an eighth partial product, a seventh partial product, a sixth partial product, a fifth partial product, and a fourth partial product. , The third partial product, the second
, And a first partial product of 10 inputs CS
The A-tree is generated by the Booth decoder using the first partial product, the second partial product, the third partial product, the fourth partial product,
The fifth partial product, the sixth partial product, the seventh partial product, the eighth partial product, the output of the second selector, the output of the third selector, and the additional bit information group are added, and the first Pipeline registers have 10 inputs C in the first operation step
The second pipeline register holds the half carry of the output of the 10-input CSA tree in the first operation step, and the carry propagation adder holds the second operation of the second operation. A value obtained by concatenating the half sum output by the 10-input CSA tree in the step and the lower 16 bits of the half sum held in the first pipeline register in the first operation step, and the 10-input CSA in the second operation step The half carry output by the tree and the lower one of the half carry held in the second pipeline register in the first operation step
Carry propagation addition is performed on a value obtained by concatenating 5 bits.

[0070]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the product-sum operation unit of the present invention.

The product-sum operation unit of this embodiment receives a signed multiplicand X having a length of 33 bits, a signed multiplier Y having a length of 32 bits, and an addition value Z having a length of 32 bits. A product-sum calculator that outputs × Y + Z as a result R. The multiply-accumulate unit includes a first selector 1, a second selector 2, a third selector 3, and a booth decoder 4.
, A bit divider 5, a 10-input CSA tree 6, a first pipeline register 7, a second pipeline register 8, a carry propagation adder 9, and a sign extender 1.
0 is included.

The Booth's decoder 4 includes a first to an eighth partial product generator.

FIG. 2 shows each input of the 10-input CSA tree 6 (a bit string indicating a bit start position and a bit length for representing a bit weight) in a first operation step in the product-sum operation unit of this embodiment and FIG. 6 is a diagram showing a list of each output (bit string of half sum and half carry).

FIG. 3 is a diagram showing a list of each input (bit string) and each output (bit string of half sum and half carry) of the 10-input CSA tree 6 in the second operation step in the product-sum operation unit of the present embodiment. It is.

FIGS. 5 and 6 are diagrams for describing the operation of the multiply-accumulate unit according to the present embodiment (refer to FIGS. 5 and 6 for explaining the concept of the booth decoder employed in the present invention). Figure).

Next, with reference to FIG. 1 and FIGS. 2 and 3, the operation of the multiply-accumulate unit according to the present embodiment will be described.

The product-sum operation unit of the present embodiment shown in FIG. 1 performs generation and addition of partial products by a “first operation step” and a “second operation step” in order to reduce the amount of hardware. This operation is performed twice (this is the same as the conventional product-sum operation unit shown in FIG. 7).

First, the operation at the time of executing the calculation in the first calculation step will be described.

In the first operation step, the product-sum operation unit of this embodiment multiplies the multiplicand X by the lower 16 bits of the multiplier Y and further adds a part (lower 18 bits) of the addition value Z. Generate the intermediate calculation result.

The sign extender 10 performs 1-bit sign extension on the addition value Z. Thereby, the addition value Z becomes 33 bits long.

The bit divider 5 converts the output of the sign extender 10 (sign-extended addition value Z) into the lower 18 bits and the upper 1
Divide into 5 bits.

The first selector 1 has an operation step switching bit (1-bit information indicating whether to perform the operation of the first operation step or the operation of the second operation step. In this case, the lower 16 bits of the multiplier Y are selectively output.

The second selector 2 selects and outputs a second constant with reference to an operation step switching bit indicating that the operation of the first operation step is performed. here,
The second constant is equal to ^1.232 (j = 0) in Expression (13).
In the case of (1) ^{(32 + 2j)} ) and c _n (1 · 2 ³¹ ) (see FIG. 2).

Further, the third selector 3 refers to the operation step switching bit indicating that the operation of the first operation step is performed, and the lower 18 bits of the output of the bit divider 5 (by the bit divider 5). A value obtained by connecting the output “lower 18 bits of sign-extended added value Z”) and the first constant is selected and output. Here, the first constant is c _z (1 · 2 ³¹ ) and c ₁₅ · 2 ³⁰ (j =
The numerical values indicate c _j · 2 ^{2j in} the case of 15 and c ₇ · 2 ¹⁴ (c _j · 2 ^{2j in} the case of j = 7) (see FIG. 2).

The Booth's decoder 4 receives the multiplicand X and the output of the first selector 1 and cuts out the output of the first selector 1 while shifting the start position from the most significant bit to the lower bits by two bits. An eighth partial product generator, a seventh partial product generator, a sixth partial product generator, a fifth partial product generator, a fourth partial product generator, a third partial product generator, The partial product generator, the second partial product generator, and the first partial product generator are supplied to each other, and from these values and the value of the multiplicand X, an eighth partial product generator to a first partial product generator are provided. By the 8th
Product to the first partial product (lower 16 of multiplicand X and multiplier Y)
Eight partial products P _{7 to} P ₀ ) are generated when multiplied by a bit.

Each partial product is a value obtained by multiplying the multiplicand X by -2, -1, 0, 1, or 2 as shown in FIG. 5, and is generated as shown in FIG. As in the conventional product-sum operation unit shown in FIG. 7, the partial product P ₀ to P ₇ bits added showing the Formula 1 and 2 in ^{(13) (32 + 2j)} (j = 1~8) And the partial products P _{1 to} P ₇ have c _j in equation (13).
A bit indicating 2 ^2j (j = 0 to 6) is added (FIG. 2)
reference. As described above, information represented by bits added to each partial product is called "additional bit information").
Here, the value of c _j is determined based on the value of Y _j as shown in FIG.

The 10-input CSA tree 6 includes the eight partial products (the partial products generated by the first to eighth partial product generators in the Booth's decoder 4 and includes additional bit information). ), The output of the second selector 2 and the third
Of the selector 3 are input as first to tenth inputs, and they are added, and the addition result is output as a set of a half sum and a half carry.

The half sum and the half carry are used as a result of the first operation step as a first pipeline register 7 and a second pipeline register, respectively.
It is held in the register 8.

Second, the operation at the time of executing the calculation in the second calculation step will be described.

In the second operation step, the multiply-accumulate unit of this embodiment multiplies the multiplicand X by the higher 17 bits of the multiplier Y, and further calculates the result of the first operation step and a part of the added value Z. (Top 1 not added in the first calculation step
5 bits) to generate a final product-sum operation result R.

At the time of transition from the first operation step to the second operation step, the operation step switching bit changes from “information indicating that the first operation step is performed” to “second operation step”.
Information indicating that the calculation step is performed ”.

The first selector 1 selects and outputs the upper 17 bits of the multiplier Y with reference to the operation step switching bit indicating that the operation of the second operation step is performed.

Further, the second selector 2 refers to the operation step switching bit indicating that the operation of the second operation step is to be performed, and refers to the value (second value) held in the second pipeline register 8. The upper 35 bits of the half carry of the operation result of the operation step 1 are selectively output.

Further, the third selector 3 refers to the operation step switching bit indicating that the operation of the second operation step is performed, and refers to the upper 15 bits of the output of the bit divider 5 (by the bit divider 5). The output “upper 15 bits of sign-extended added value Z”) and the upper 34 bits of the value (half-sum of the operation result of the first operation step) held in first pipeline register 7 Select and output the value concatenated with.

The booth decoder 4 receives the multiplicand X and the output of the first selector 1 and cuts out the output of the first selector 1 while shifting the start position from the most significant bit to the lower bit by two bits. An eighth partial product generator, a seventh partial product generator, a sixth partial product generator, a fifth partial product generator, a fourth partial product generator, a third partial product generator, The partial product generator, the second partial product generator, and the first partial product generator are supplied to each other, and from these values and the value of the multiplicand X, an eighth partial product generator to a first partial product generator are provided. By the 8th
Product to the first partial product (upper 17 of multiplicand X and multiplier Y)
Eight partial products P _{15 to} P ₈ ) are generated when multiplied by the bits.

Each partial product has a value obtained by multiplying the multiplicand X by -2, -1, 0, 1, or 2 as shown in FIG. 5, and is generated as shown in FIG. As in the conventional product-sum operation unit shown in FIG. 7, the partial products P ₈ to P _14-bit additional showing the Formula 1 and 2 in ^{(13) (32 + 2j)} (j = 9~15) And the partial products P _{9 to} P ₁₅ have c in equation (13).
A bit indicating _j · 2 ^2j (j = 8 to 14) is added (see FIG. 3).

The 10-input CSA tree 6 includes the eight partial products (the partial products generated by the first to eighth partial product generators in the Booth's decoder 4 and includes additional bit information). ), The output of the second selector 2 and the third
Of the selector 3 are input as first to tenth inputs, and they are added, and the addition result is output as a set of a half sum and a half carry.

Carry propagation adder 9 adds the following values and the following values to obtain and output a single result R (result R of the product-sum operation) (the following values and Carry propagation addition). A 49-bit half-sum (half-sum obtained in the second operation step) and the lower 16 bits of the half-sum obtained in the first operation step (lower value of the value held in the first pipeline register 7) 16 bits)
(See FIGS. 2 and 3) A half carry of 48 bits (half carry obtained in the second operation step) and the lower 15 bits of the half carry obtained in the first operation step ( A value concatenated with the lower 15 bits of the value held in the second pipeline register 8 (see FIGS. 2 and 3)

In the conventional product-sum operation unit shown in FIG. 7, a dedicated input is provided in the CSA tree (11-input CSA tree 106) in order to add a value obtained by sign-extending the addition value Z. On the other hand, in the product-sum operation unit of the present embodiment shown in FIG.
Is given to the CSA tree (10-input CSA tree 6) according to the procedure shown in FIG. The value obtained by sign-extending the addition value Z is divided by the bit divider 5 so that the bit weight does not overlap with another input value (input value corresponding to each item in the equation (13)). The two values at the output of the bit divider 5 are concatenated with the other input values. The “value in which the addition value Z is sign-extended” divided into two and divided into two by the first operation step and the second operation step and connected to other input values is a CSA tree (1
0 input CSA tree 6).

For this reason, CSA conventionally required 11
The number of tree inputs can be reduced to ten, and hardware simplification of the CSA tree and shortening of operation delay (speeding up of operation) can be achieved.

Referring to FIG. 2 and FIG. 3, each item in equation (13) is always included in the bit string of each input in FIG. 2 or FIG. Therefore, in each of the first operation step and the second operation step, the value of each item in the equation (13) is input by the 10-input CSA tree 6 and added.

Here, 1.2 appearing in equation (13)
^{(32 + 2j)} (j = 0 to 16) and c _j · 2 ^2j (j = 0 to 1)
The form in which 5), c _z, and c _n are given to the 10-input CSA tree 6 is not limited to the forms shown in FIGS. 2 and 3. The above value ( ^{1.2 (32 + 2j)} (j = 0 to 0 ^{) is added to the} position of the same bit weight as the position shown in FIGS.
16), c _j · 2 ^2j (j = 0 to 15), c _z , and c
_As long as the bit indicating _n ) is input, modes other than those shown in FIGS. 2 and 3 are also allowed. Therefore, the values of the first constant and the second constant are not limited to the values in the present embodiment.

In the present embodiment, the additional bit information for the partial products P _{0 to} P _{15 is} added at the booth decoder 4 side. However, these additional bit information is added at the 10-input CSA tree 6 side. It is also possible.

A method of instructing the first selector 1, the second selector 2 and the third selector 3 with information indicating which of the first calculation step and the second calculation step is being performed. Is not limited to the “method instructed by the operation step switching bit” as in the present embodiment.

[0106]

As described above, according to the present invention, the sum Z
Is divided so that the bit weight does not overlap with the other input value, and is connected to the other input value. The value generated by the division / concatenation is divided into a first operation step and a second operation By giving to the CSA tree in two steps, the number of inputs of the CSA tree conventionally required 11 can be reduced to 10 (the hardware amount of the CSA tree can be reduced. ), The amount of hardware can be reduced compared to the conventional product-sum operation unit (fixed-point product-sum operation unit), and the operation can be performed faster than the conventional product-sum operation unit (operation delay can be reduced) There is an effect that it becomes possible to realize a computing unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a product-sum calculator according to the present invention.

FIG. 2 is a diagram showing a list of each input and each output of a 10-input CSA tree in FIG. 1 in a first operation step in the product-sum operation unit shown in FIG. 1;

3 is a diagram showing a list of each input and each output of a 10-input CSA tree in FIG. 1 in a second operation step in the product-sum operation unit shown in FIG. 1;

FIG. 4 is a diagram showing an aspect of a product-sum operation targeted by the present invention.

FIG. 5 is a diagram for explaining the concept of the Booth decoder employed in the present invention and explaining the operation of the product-sum operation unit shown in FIGS. 1 and 7;

FIG. 6 is a diagram for explaining the concept of the Booth decoder employed in the present invention and explaining the operation of the product-sum operation unit shown in FIGS. 1 and 7;

FIG. 7 is a block diagram illustrating a configuration of an example of a conventional product-sum operation unit.

8 is a diagram showing a list of each input and each output of the 11-input CSA tree in FIG. 7 in a first operation step in the product-sum operation unit shown in FIG. 7;

9 is a diagram showing a list of each input and each output of the 11-input CSA tree in FIG. 7 in a second operation step in the product-sum operation unit shown in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st selector 2 2nd selector 3 3rd selector 4 Booth's decoder 5 Bit divider 6 10-input CSA tree 7 1st pipeline register 8 2nd pipeline register 9 Carry propagation adder 10 Sign extender R Result X Multiplicand Y Multiplier Z Add value

Claims (3)

(57) [Claims] 1. A signed multiplicand X, 32 having a length of 33 bits.
A signed multiplier Y having a bit length and an added value Z having a 32-bit length are input, and the product sum X × Y + Z is obtained as a result R
A sign extender that performs 1-bit sign extension on the addition value Z; a bit divider that divides the output of the sign extender into lower 18 bits and upper 15 bits; In the first operation step, the lower 16 bits of the multiplier Y are selectively output, and in the second operation step, the upper 17 bits of the multiplier Y are selectively output. In the first operation step, the second constant is set. Select output, 2nd
A second selector for selecting and outputting the upper 35 bits of the value held in the second pipeline register in the operation step, and a lower 18 bits of the output of the bit divider and the first selector in the first operation step. Select and output the value concatenated with the constant of
A second selector for selecting and outputting a value obtained by connecting the upper 15 bits of the output of the bit divider and the upper 34 bits of the value held in the first pipeline register; While shifting the output of the first selector from the most significant bit to the lower bit by two bits from the most significant bit, the values extracted in units of 3 bits are used as the values of the eighth partial product generator, the seventh partial product generator, and the sixth partial product generator. , A fifth partial product generator, a fourth partial product generator, a third partial product generator, a second partial product generator, and a first partial product generator, From these values and the value of the multiplicand X, the eighth partial product, the seventh partial product, the sixth partial product, the fifth partial product, the fourth partial product, the third partial product, and the second partial product A Booth decoder for generating a product and a first partial product; First partial product generated I, second partial product, the third partial product, the fourth partial product, the fifth
, The sixth partial product, the seventh partial product, the eighth partial product, the output of the second selector, the output of the third selector, and the additional bit information group and a 10-input CS.
An A-tree; the first pipeline register for holding a half-sum of the outputs of the 10-input CSA tree in a first operation step; and an output of the 10-input CSA tree in a first operation step. A second pipeline register for holding a half carry, a half sum output by the 10-input CSA tree in a second operation step, and a first sum in the first operation step.
The value obtained by concatenating the lower 16 bits of the half sum held in the pipeline register of the second register, the half carry output by the 10-input CSA tree in the second operation step, and the second pipe in the first operation step A carry-propagation adder for performing carry-propagation addition on a value obtained by concatenating the lower 15 bits of the half carry held in the line register. 2. The method according to claim 1, wherein the operation of the first operation step is performed.
The operation step switching bit indicating whether or not to perform the operation of the operation step of the first selector, the second selector, and the third selector
2. The multiply-accumulate unit according to claim 1, wherein the sum is given to the selector. 3. The first constant is “c _z , c ₁₅ · ²³⁰ and c ₇
- 2 ¹⁴ and a numerical value "indicating a second constant" number indicating the 1, 2 ³² and the c _n ", in the first operation step, the partial product P _0, P _1, P _2,
^{1.2 (32 + 2j) for} P ₃ , P ₄ , P ₅ , P ₆ , and P ₇
(J = 1, 2, 3, 4, 5, 6, 7, and 8) are added, and the partial products P ₁ , P ₂ , P ₃ , P ₄ ,
P _5, P _6, and P ₇ in the ^{_{c j · 2 2j (j =}} 0,1,
2, 3, 4, 5, and 6), and in a second operation step, the partial products P ₈ , P ₉ , P ₁₀ ,
P ₁₁ , P ₁₂ , P ₁₃ , and ~ P ₁₄ have _1.2 ^{(32 + 2j)} (j
= 9, 10, 11, 12, 13, 14, and 15), and the partial products P ₉ , P ₁₀ , P ₁₁ , P ₁₂ ,
P ₁₃ , P ₁₄ , and P ₁₅ have c _j · 2 ^2j (j = 8, 9, 1
3. The sum-of-products arithmetic unit according to claim 1, wherein a bit indicating 0, 11, 12, 13, and 14) is added.