JP2608090B2 - High radix non-restoring divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A division device for processing a division instruction (DIVIDE instruction) of a computer, wherein a high radix non-restoring division device for obtaining an n-bit quotient in one cycle based on a partial quotient prediction value The purpose of this is to reduce the holding time of the divisor and the dividend, to shorten the operation time, and to reduce the number of arithmetic units. And a means for selecting one of the output of the second quotient prediction circuit and the output of the partial quotient prediction circuit.

[Industrial applications]

The present invention relates to a division device for processing a division instruction (DIVIDE instruction) in a general-purpose scalar computer, a vector computer, and the like. The present invention relates to a dividing device.

[Conventional technology]

FIG. 5 shows an example of a conventional division operation unit, FIG. 6 shows an example of the conventional system, and FIG. 7 shows a time chart of the conventional system.

The arithmetic unit of the high-radix non-restoring division device that obtains an n-bit quotient in one cycle based on the partial quotient predicted value is conventionally configured as shown in FIG.

The divisor D of the input data is set in a divisor register (DSR), and the dividend N is set in a partial remainder register (PR). The multiple generation circuit (MULT) uses the divisor register (DS
R) and the partial quotient predicted value from the partial quotient prediction circuit (QP), and ± m times the divisor D (m is an integer)
Is a circuit for creating the value of.

The adder circuit (ADDER) calculates the difference between the output of the multiple generation circuit (MULT) and the dividend. Here, in order to increase the speed, the upper bit portion and the lower bit portion are separately added.

The partial quotient prediction circuit (QP) is a circuit that obtains a partial quotient prediction value to be used in the next cycle by referring to a decoding table using the output of the addition circuit and the divisor. The multiple generation circuit (MULT) performs multiplication for obtaining the next partial quotient based on the partial prediction value. The partial quotient generation circuit (QG) is a circuit that corrects a quotient and creates a correct partial quotient.

The division device, the i-th partial remainder which is set to the partial remainder register (PR) P _i, the i-th partial quotient predictions multiple generating circuit (MULT) can be used when a d _i, the adder circuit (AD
The DER), by calculating _{P i + 1 = P i -D} × d i, and obtains the d _i in each cycle. The partial remainder output from the adder (ADDER) may be a negative number. In this case, the result is corrected by the partial quotient generator (QG).

In the conventional method, in the first cycle after the divisor and the dividend are set, the partial quotient prediction value is unknown, so this is calculated as 0, and one cycle is run idle, thereby substantially the first partial quotient. A prediction value is obtained.

FIG. 6 shows a case where a plurality of division arithmetic units shown in FIG.
1 shows an example of a conventional method in which continuously input vector data is processed by a pipeline operation. In FIG. 6, DIV0, DIV1,..., DIV5 each correspond to the division operation unit shown in FIG.

In the conventional division operation unit, when the data of the divisor D _i and the dividend N _i are set, the partial quotient prediction value is not input.
In the first 1τ, a partial quotient is not obtained, and a partial quotient is output from the next cycle. For example, for 56-bit data, 1τ
When the quotient is obtained by 4 bits at a time, it takes 1τ to obtain the first partial prediction value, and a total of 15τ of 56 bits ÷ 4 bits = 14τ is required for the division.

In the device shown in FIG. 6, when the divisor D _i and the dividend N _i are sent in one pass, the divisor D _i input first is
Since the dividend N _i needs to be held for 1τ longer before it is prepared, the divisor register (DSR) shown in FIG.
6τ must be held.

As shown in the time chart of the conventional method shown in FIG. 7, if a pair of the divisor D _i and the dividend N _i is sent once in 3τ, the first D ₀ and N ₀ are divided by the division shown in FIG. after being set to a calculator DIV0, the D ₀ is 16τ held in the divisor register (DSR). Thus, a set of divisor and dividend, if went by input to the division operation unit, when has come sixth data D _5, N ₅ is still registers division calculator DIV0 not been empty. Therefore, as shown in FIG. 6, a minimum of six division arithmetic units DIV0 to DIV5 were required.

[Problems to be solved by the invention]

As described above, according to the conventional method, in order to output the first partial quotient predicted value, the divisor and the dividend need to be held in the register by one extra cycle, and for example, as shown in FIG. When the division is continuously processed by the pipeline operation, there is a problem that a large number of division operation units are required.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems, to reduce the holding time of the divisor and the dividend, to shorten the operation time, and to reduce the number of operation units.

[Means for solving the problem]

In the present invention, for example, as shown in FIG. 1, a second quotient prediction circuit 20 is provided in a stage preceding the partial remainder register 10 in which the dividend N is set and the divisor register 11 in which the divisor D is set. In addition, a selection circuit 21 for selecting one of the output of the second quotient prediction circuit 20 and the output of the partial quotient prediction circuit 14 is provided.
Thereby, the dividend and the divisor are prepared in the partial remainder register 10 and the divisor register 11, and at the same time, the second partial quotient prediction circuit 20 prepares the first partial quotient predicted value in the partial quotient prediction register 22. To

[Action]

According to the conventional method, when the multiple generation circuit 12 obtains a value of ± m times the divisor (m is an integer) from the values of the divisor register 11 and the partial quotient prediction circuit 14, the first cycle is
According to the present invention, the partial quotient prediction value is calculated by "0", while the first substantial partial prediction value is calculated by the second quotient prediction circuit.
Since the value is obtained in advance by using 20, the waiting time of the first cycle can be omitted, and the operation cycle can be shortened. From the next cycle, the partial prediction value by the partial quotient prediction circuit 14 is selected by the selection circuit 21.

〔Example〕

FIG. 1 is a configuration example of the present invention, FIG. 2 is an embodiment of an apparatus using the present invention, FIG. 3 is an explanatory diagram of processing of a pre-processing unit shown in FIG. 2, and FIG. 4 is an embodiment of the present invention. 3 shows a time chart.

In FIG. 1, 10 is a partial remainder register (PR), 11 is a divisor register (DSR), 12 is a multiple generation circuit (MULT), 13 is an addition circuit having a carry look-ahead circuit, and 14 is a partial quotient prediction circuit (Q
P) and 15 are partial quotient generation circuits (QG), 20 is a second quotient prediction circuit (QP2), 21 is a selection circuit, and 22 is a partial quotient prediction register (QP
R) and R1 to R4 are registers for temporarily holding values.

The partial remainder register 10, the divisor register 11, the multiple generation circuit 12, and the addition circuit 13 (adder 13A for adding the upper part)
, A partial quotient prediction circuit 14, and a partial quotient generation circuit 15 are the same as those of the conventional example shown in FIG.

When the divisor D and the dividend N are sequentially input, they are set in the divisor register 11 and the partial remainder register 10, respectively, and supplied to the second quotient prediction circuit 20, where the second quotient prediction circuit
By using 20, the partial quotient prediction value is obtained. It should be noted that the second quotient prediction circuit 20 may be considered to be configured similarly to the partial quotient prediction circuit 14. When the dividend N is expressed as an absolute value,
In other words, when expressed as a positive number, it is equivalent to a circuit in which the sign bit of the partial quotient prediction circuit 14 is eliminated and quotient prediction is performed.

At the start of the operation, the selection circuit 21 selects the output of the second quotient prediction circuit 20 according to the selection signal based on the START signal, and outputs the partial quotient prediction value to the partial quotient prediction register 22. Therefore, in the first cycle, the multiple generation circuit 12 uses the value of the divisor register 11 and the partial prediction value output from the second quotient prediction circuit 20.

Subsequent operation is almost the same as the conventional method.
13 generates a multiple generation circuit from the value of the partial remainder register 10.
Find the partial remainder by subtracting the 12 outputs. The value is returned to the partial remainder register 10. That is, after the dividend N is set in the partial remainder register 10 at the beginning of the operation, a new partial remainder is set in each operation cycle. The partial quotient prediction circuit 14 calculates a
From the bits and the upper b bits of the divisor register 11, a partial quotient prediction value serving as a control signal for the multiple generation circuit 12 is created.

The selection circuit 21 selects the output of the partial quotient prediction circuit 14 instead of the output of the second quotient prediction circuit 20 from the second cycle. Depending on the value, the operation cycle will be repeated. The partial quotient generating circuit 15 is a circuit that corrects the quotient when the partial remainder output from the adding circuit 13 becomes a negative number.

FIG. 2 shows an example of an apparatus using the present invention for processing division of continuously input vector data by a pipeline operation. Functionally, it is a device similar to the conventional system shown in FIG.

The second quotient prediction circuit 20 shown in FIG. 1 is provided in the preprocessing unit 30. Therefore, it is commonly used by each of the division operation units DIV0 to DIV4.

When dividing a floating-point value, the preprocessing unit 30 performs the following processing.

The divisor D is bit-shifted to the left so that the most significant bit of the mantissa of the divisor D becomes "1" in order to simplify the decoding table for obtaining the partial quotient prediction value. The dividend N is shifted to the left by the same amount as the divisor D. However, when the quotient becomes larger than 1, that is, when D <N, after the left shift, conversely, it is shifted right by 1 digit (4 bits), and the exponent part is incremented by +1.

For example, when the operation data is a divisor D and a dividend N as shown in FIG. 3A, the divisor D is shifted left by 2 bits. In accordance with this, when the dividend N is shifted to the left by 2 bits, "1" is shifted out, and conversely, it is shifted to the right by 1 digit. That is, a total of 2 bits right shift is performed, and the exponent part is incremented by +1. As a result, the divisor D and the dividend N are adjusted as shown in FIG.

In the present embodiment, the second value is further obtained by this adjusted value.
The first partial quotient prediction value is obtained using the quotient prediction circuit 20 of FIG. The divisor D, the dividend N, and the partial quotient prediction value are sent to one of the available division operation units DIV0 to DIV4. The operation in each of the division calculators DIV0 to DIV4 is the same as the operation described with reference to FIG.

The overall time chart of the apparatus shown in FIG. 2 is as shown in FIG.

First, the divisor D ₀ is input to the division calculator DIV _0, and then the dividend N ₀ and the partial quotient predicted value Q ₀ output from the second quotient predicting circuit 20 are input. Then, the calculation is started by the effective partial quotient predicted value Q ₀ . Next data D ₁ , N ₁ and Q
₁ are input to the next division operation unit DIV1 with a delay of 3τ. Hereinafter, similarly, data is input to each division operation unit, and the operation is performed.

The first divisor D ₀ is the 15τ eyes after being set to the divisor register (DSR), the divisor register (DSR) is empty. Therefore, the sixth data D ₅ and N ₅
Can be input to IV0.

That is, when data is sent once every 3τ in this manner, according to the conventional method, the divisor must be held at 16τ, so that six division arithmetic units are required. When the holding time is 15τ, the calculation can be performed by five division calculators.

Needless to say, the present invention can be applied to both floating-point arithmetic and integer arithmetic.

〔The invention's effect〕

As described above, according to the present invention, the holding time of the divisor and the dividend can be shortened, and the calculation time can be shortened. In particular, when used in a vector computer, the number of arithmetic units required for the pipeline operation can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration example of the present invention, FIG. 2 is an embodiment of an apparatus using the present invention, FIG. 3 is an explanatory diagram of processing of a preprocessing unit shown in FIG. 2, and FIG. 4 is an embodiment of the present invention. FIG. 5 shows an example of a conventional division operation unit, FIG. 6 shows an example of a conventional system, and FIG. 7 shows a time chart of a conventional system. In the figure, 10 is a partial remainder register, 11 is a divisor register, 12 is a multiple generation circuit, 13 is an addition circuit, 14 is a partial quotient prediction circuit, 15 is a partial quotient generation circuit, 20 is a second quotient prediction circuit, and 21 is Selection circuit, 22
Represents a partial quotient prediction register, and R1 to R4 represent registers.

Claims (1)

(57) [Claims] 1. A high radix ratio restoring type dividing device for obtaining an n-bit quotient in one cycle, comprising: at least a partial remainder register (10), a divisor register (11), and a divisor based on a partial quotient prediction value. A multiple generation circuit (12) for generating a multiple, an addition circuit (13) for performing addition and subtraction of the partial remainder and the output of the multiple generation circuit, and a partial quotient prediction circuit (14) for obtaining a partial quotient prediction value from the addition result and the divisor ), The partial remainder register (10) and the divisor register (11).
A second quotient prediction circuit (20) that outputs a first partial quotient prediction value from the value of the dividend and the value of the divisor, and a second quotient prediction circuit (20) that calculates the first partial quotient in a cycle for calculating the first partial quotient. Means (21) for selecting the output of (20) and selecting the output of the partial quotient prediction circuit (14) in the subsequent cycles.