JP3579087B2 - Arithmetic unit and microprocessor - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to means for performing arithmetic processing such as product-sum operation used in image processing or the like at high speed.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in the field of image processing (image processing), high-speed, high-precision, etc., high-level arithmetic performance is required when performing arithmetic processing. The company has produced a dedicated arithmetic unit for arithmetic processing and applied it to image processing.
[0003]
If such a dedicated arithmetic unit is manufactured according to the content of the image processing, and a system for performing the image processing is designed and manufactured, the cost of the system will increase.
[0004]
On the other hand, the performance of general-purpose processors that can be constructed at relatively low cost and can be applied to image processing has improved, but the more general processing is performed by the built-in arithmetic unit in the general-purpose processor, the more general-purpose processors The processing speed and processing content of the arithmetic unit built therein are not excellent.
[0005]
By the way, a so-called product-sum operation, which is an arithmetic process frequently performed in image processing, can be executed by an arithmetic unit configured by appropriately combining a multiplier and an adder.
[0006]
In such a conventional arithmetic unit, a multiplier for multiplying a given two numbers has a function of generating a partial product and a function of adding a partial product.
[0007]
Here, generation of a partial product and partial product addition will be described with reference to FIG.
[0008]
Here, the number of bits of data used for multiplication is 5 bits.
[0009]
The “partial product” is obtained by examining the bits of the multiplier 1901 bit by bit. If the bit content is “1”, it is the value of the multiplicand 1900 itself, and if the bit content is “0”, the partial product is calculated. It is set to “0”.
[0010]
However, the partial product generated by the sign bit of the multiplier 1901 is, if the sign bit content is “1”, the sum of the bit inversion of the multiplicand 1901 and the addition 1, and if the sign bit is “0”, it is “0”. I do.
[0011]
In FIG. 19, the partial product is represented by being surrounded by a rectangle, and its contents are shown in the rectangle.
[0012]
In the 5-bit multiplication, since the number of bits of the multiplier is 5 (bits), five partial products are generated as shown in FIG. In the calculation example shown in the figure, the partial product 1 (1902) and the partial product 2 (1903) are generated when their contents of the bit to be examined are “1”. Become.
[0013]
In addition, the partial product 3 (1904) and the partial product 4 (1905) become “0” because the content of the bit to be examined is “0” at the time of generation, and the partial product 5 (1906) becomes , And the sign bit to be examined at the time of generation is “1”, so that the multiplicand is a negative number.
[0014]
The addition of each partial product is performed by shifting the partial product one bit at a time to the upper (left) side in the order of generation from the lower bits of the multiplier, and then adding the products. In addition, when the multiplier and the multiplicand are expressed in negative numbers, that is, in a so-called two's complement expression, in order to correctly execute the partial product addition, the sign must be extended (hereinafter, referred to as “sign extension”) and added. Must.
[0015]
In the example shown in FIG. 19, the partial product 1 is extended by 4 bits (1907), the partial product 2 is extended by 3 bits (1908), the partial product 3 is extended by 2 bits (1909), and the partial product 4 is extended , One bit extended (1910). By such sign extension, accurate partial product addition can be performed.
[0016]
Usually, this partial product addition is performed using a carry save adder and a carry propagation adder as shown in FIG. The partial product adder shown in FIG. 20 is a carry save adder configured by arranging three-input full adders.
[0017]
FIG. 21 shows the operation of the three-input full adder, which is a basic component of the partial product adder.
[0018]
The 3-input full adder adds the input 3 bits (2100, 2101, 2102) and outputs a carry 2104 and a sum 2103.
[0019]
As shown in FIG. 21, three values are input, and in a predetermined case, carry output (2104) is performed and addition (2103) is performed.
[0020]
In a full adder (2000, 2001, 2002, 2003, 2004) which is an adder having a carry-save function shown in FIG. 20, partial products 1 to 3 shown in FIG. Perform the addition of The "carry" of the result of the addition performed by each full adder is sent to the next-stage full adder of the next digit, and the "sum" is sent to the next-stage full adder (2010, 2011, etc.). And performs addition with the partial product 4 shown in FIG. Further, the result is input to a full adder (2012 or the like) used for adding the partial product 5, and is added.
[0021]
Since the partial product 5 needs to invert the value of the multiplicand and add “1”, the input 2013 of the full adder 2012 is used as an input for adding 1.
[0022]
As an example, the first-stage full adder 2000 includes an extension code 2005 (value is “1”) of the partial product 1, an extension code 2006 (value is “1”) of the partial product 2, and a code of the partial product 3. 2007 (the value is “0”) is input and addition is performed.
[0023]
Then, the carry 2008 of the addition result is inputted to the next-stage full-adder 2010 one digit higher, and the sum 2009 is inputted to the next-stage full adder 2011 of the same digit.
[0024]
Full adder 2010 receives the carry and sum of the addition results of the extension codes of partial products 1 to 3 and performs addition. Since the full adder 2014 that generates the input signal performs the same calculation as the full adder 2000, the addition result 2009 of the full adder 2000 is used as an input of the full adder 2010, and as a result, the full addition The adder 2000 performs the addition of the upper digit, that is, the full adder 2014 existing on the left side can be omitted.
[0025]
As described above, the adder having the carry save function sends “carry” to the next stage and repeats the addition. Therefore, even if the addition of all partial products is completed, two outputs 2024 to 2038 remain. Therefore, in order to obtain the final result, a so-called carry propagation adder as shown in FIG. 20 is required to further add the two outputs.
[0026]
In the configuration shown in FIG. 20, the carry propagation adder includes full adders 2015 to 2022. As an example, the connection between these full adders has a connection relationship such that the carry 2023 of the full adder 2016 becomes an input of the full adder 2015, and literally constitutes a carry propagation adder. ing.
[0027]
[Problems to be solved by the invention]
As described above, for example, in the sum-of-products arithmetic unit shown in FIG. 20, not only an adder having a carry-save function, but also a carry propagation adder must be provided to realize the sum-of-products arithmetic unit. Did not.
[0028]
As described above, when the operation is performed using the conventional dedicated operation unit, the processing performance is satisfied, but the cost of the system is increased in most cases. On the other hand, although the use of the general-purpose arithmetic unit can suppress an increase in cost, there still remains a problem that its processing performance is not satisfactory.
[0029]
However, since the use of a general-purpose arithmetic unit is indispensable for cost reduction, it is necessary to improve the processing performance of the general-purpose arithmetic unit.
[0030]
Therefore, an object of the present invention is to provide a means for independently operating a part of a multiply-accumulate unit frequently used in image processing or the like among general-purpose arithmetic units included in a general-purpose processor, thereby enabling a plurality of multiply-accumulate operations to be performed. It is an object of the present invention to provide a computing means which can be used for high-speed image processing or the like, in which the cost is suppressed, the computation speed is high, and the cost is reduced.
[0031]
[Means for Solving the Problems]
To solve the above problems and achieve the object of the present invention, the following means are conceivable.
[0032]
An arithmetic unit for obtaining a product of a number of N bits having a plurality of multiplicands and a number of M bits having a plurality of multipliers corresponding to each of the multiplicands to obtain a multiplication result for a set of a multiplicand and a multiplier, An arithmetic unit comprising the means of (1).
[0033]
That is, a first register that holds a plurality of multiplicands and is arranged on condition that the sum of bit lengths of each multiplicand does not exceed N, and holds the number of N bits with 0 embedded between each multiplicand And the multipliers corresponding to the respective multiplicands are arranged, provided that the sum of the bit lengths of the respective multipliers does not exceed M, and the number of M bits is held with 0 embedded between the multipliers. A second register, a partial product processing unit for performing a process of obtaining a partial product of the value held in the first register and the value held in the second register, and a set of multiplicands in the partial product. A sign extension unit for embedding bits obtained by expressing the multiplication result in two's complement to compensate for the sign of the multiplication result of the multiplier, and a means for sequentially calculating the sum of each partial product; The sum of all partial products for If obtained, the excess value is discarded when calculating the sum of partial products for the next other set of multiplicands and multipliers, summing means for calculating the sum value of each partial product, From the data of the sum value (“N + M” (bits)), a value that is the result of multiplication of each multiplicand in the first register and the corresponding multiplier in the second register is cut out and corresponds to a set of the multiplicand and the multiplier. Processing means for obtaining a multiplication result for each set.
[0034]
[Action]
The present invention relates to a general-purpose sum-of-products arithmetic unit, which has a function of separating and simultaneously performing multiplication on each data stored in an input register or the like, and adding a multiplication result to each multiplication result. Are provided with an adder having a function of separating and simultaneously performing the operations.
[0035]
First, a plurality of multiplicands are held in the first register, arranged under the condition that the sum of the bit lengths of the multiplicands does not exceed N, and the number of N bits is written with 0 embedded between the multiplicands. Keep it. The second register holds a plurality of multipliers corresponding to the multiplicand, and arranges them on condition that the sum of the bit lengths of the multipliers does not exceed M, and embeds 0 between the multipliers. , M bits are held.
[0036]
Next, the partial product processing unit performs a process of obtaining a partial product of the value held in the first register and the value held in the second register, and the sign extension unit performs one set in the partial product. In order to compensate for the sign of the result of the multiplication of the multiplicand and the multiplier, a process of embedding bits obtained by expressing the result of the multiplication in 2's complement is performed.
[0037]
Then, the summation means sequentially calculates the sum of the partial products, and when the sum of all the partial products for a certain set of the multiplicand and the multiplier exceeds a predetermined value, the exceeded value is replaced with the value of the next other set. The sum of the partial products to be discarded when the sum of the partial products for the multiplicand and the multiplier is obtained is obtained.
[0038]
Finally, the processing means multiplies each multiplicand in the first register by a corresponding multiplier in the second register from the data of the sum (“N + M” (bits)) obtained by the summing means. A value is cut out, a multiplication result corresponding to a set of a multiplicand and a multiplier is obtained for each set, and a parallel operation is realized.
[0039]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0040]
FIG. 1 shows a configuration diagram of an embodiment according to the present invention.
[0041]
The present embodiment is an arithmetic unit for simultaneously executing the operations “a1 × b1 + c1” and “a2 × b2 + c2”.
[0042]
The entire arithmetic unit is composed of two multiplicands a1 and a2 packed in the register 100 (the state in which data is packed is expressed as follows) and two multipliers b1 and b1 packed in the register 101. b2 as inputs 102 and 103, respectively, and a partial product adder 104 having a function of adding partial products generated based on these inputs.
[0043]
Further, the two addends c1 and c2 packed in the register 105 are used as an input 106, and the input data is added to two outputs “a1 × b1” and “a2 × b2” of the partial product adder 104. , A shift-and-selector 107 having the function of shifting the contents of the input 106 and aligning the two outputs of the partial product adder 104 with each other, A three-input full adder sequence 108 having a function of adding the two outputs and the output of the "shift and selector"107; a 64-bit adder 109 having a function of adding the two outputs of the three-input full adder sequence; An aligner 110 for converting the output of the bit adder 109 into a specified format, and an overflow for determining whether the addition result is an overflow or an underflow. The flow / underflow determination unit 111 determines whether the output of the aligner 110 is the maximum value if the determination result is an overflow, and the maximum / minimum value that replaces the output of the aligner 110 with the minimum value if the determination result is an underflow. And a value substitution unit 112. Then, the final operation result is output in a state packed in the register 150.
[0044]
In the embodiment of FIG. 1, the operation of each component when performing the product-sum operation of “a1 × b1 + c1” and “a2 × b2 + c2” is described in the upper 8 bits and the lower 8 bits of a register having a data length of 32 bits. The case where two data are packed will be described as an example.
[0045]
As for the data for which the product-sum operation is performed, two data a1 and a2 are packed in upper 8 bits and lower 8 bits of 32 bits as in a data format 200 shown in FIG. 2, and a “0” value is embedded between them. , 32-bit data.
[0046]
Similarly, data b1, b2, c1, and c2 (not shown) are packed with two data in the upper 8 bits and lower 8 bits of 32 bits, and a “0” value is embedded between them to form a 32-bit data. And
[0047]
By multiplying the 32-bit data packed with the data a1 and a2 and the 32-bit data packed with the data b1 and b2 with the 32-bit data, the multiplication of the packed 8-bit data, that is, , “A1 × b1” and “a2 × b2” are simultaneously executed.
[0048]
FIG. 2 shows which part of the result of the 32-bit multiplication corresponds to the multiplication “a1 × b1” and “a2 × b2”. In FIG. 2, each partial product is represented by a horizontally long rectangle.
[0049]
The multiplication “a1 × b1” is the upper 15 digits of each of the partial products 25 (203) to 32 (204), and the multiplication “a2 × b2” is the partial product 1 (201). Calculated using the lower 15 digits of each, up to product 8 (202). Therefore, the portion painted black in the drawing is a portion in which the signs of the multiplication “a1 × b1” and “a2 × b2” are extended. The concept of sign extension is as shown in FIG.
[0050]
Further, since the value “0” is embedded between the multiplier data b1 and b2, the partial products 9 to 24 generated from those bits (the value is “0”) are always “0”. Therefore, when all the partial products are added, it is possible to eliminate the influence on the multiplication “a1 × b1” caused by the propagation of the carry resulting from the partial product addition by a2 × b2.
[0051]
Also, by setting the addition of the sign extension for 32-bit of the partial product 25 used in the addition of the partial product 25 to “0”, the addition of the sign extension for the 32-bit multiplication (partial product 1 The addition results corresponding to (1) to (8) can be eliminated from affecting the calculation result of “a1 × b1”.
[0052]
By devising these two points, “a1 × b1” and “a2 × b2” can be calculated in a separated state.
[0053]
Next, the operation of the partial product adder 104 having the functions described above will be described in detail.
[0054]
FIG. 3 shows a configuration example in which the function of the extension code of multiplication a2 × b2 is realized by a general-purpose partial product adder.
[0055]
As shown in FIG. 2, the range in which the extension code of this multiplication is required is from the ninth digit to the fifteenth digit in “partial product 1”, from the tenth to fifteenth digit in “partial product 2”, In "partial product 3", from the 11th to the 15th digit, in "partial product 4", from the 12th to the 15th digit, and in "partial product 5", from the 13th to the 15th digit, the "partial product" 6 "is the 14th to 15th digits, and" Partial Product 7 "is the 15th digit.
[0056]
FIG. 3 illustrates a portion corresponding to the partial products 3 to 5 as an example.
[0057]
The operation of each full adder is as shown in FIG.
[0058]
The full adders 300 to 305 perform addition of the 15th to 10th digits of the partial product 3, and the full adders 306 to 311 perform addition of the 15th to 10th digits of the partial product 4. To 317 are used for the addition of the 15th to 10th digits of the partial product 5, respectively.
[0059]
If the signal 330 is “1”, the selector 318 selects 332 out of the two inputs 331 and 332. The other selectors 319 to 321 operate similarly. Since 332 is the sign of the partial product 3 of the multiplication “a2 × b2”, by signifying the signal 330 to “1”, the sign is extended by the signal 332 for expressing the sign and the full adder The partial product 3 can be added.
[0060]
The selectors 323 to 326 and the selectors 327 to 329 also select the codes 333 and 334 of the partial products 4 and 5, respectively, by setting the signal 330 to “1”. As a result, sign-extended addition can be realized for the partial products 4 and 5 as well.
[0061]
In addition, although not shown in FIG. 3, for the partial products 1, 2, 6, and 7, a selector for selecting a signal for sign extension by the signal 330 is provided on the input side of the full adder. With this configuration, sign-extended addition can be realized by partial product addition of multiplication “a2 × b2”.
[0062]
FIG. 22 is an implementation example of a general-purpose partial product adder for generating a partial product 8 from the sign bit (eighth bit from the lower order) of the multiplier b2. Full adders 2200 to 2207 add the lower 8 bits of partial product 8. In order to generate a partial product from a sign bit, as shown in FIG. 19, this is a configuration for realizing a process of inverting data and adding “1”.
[0063]
The logic gate 2208 has a function of inverting the input 2227 when the signal 2225 is “1” and outputting “1” regardless of the value of the input 2227 when the signal 2225 is “0”. The selector 2216 has a function of selecting the output of the logic gate 2208 when the signal 2226 is “1”, and selecting the data 2227 of the eighth bit from the lower order of the partial product 8 when the signal 2226 is “0”. .
[0064]
The “logical gate 2208 and selector 2216” and the “logical gates 2209 to 2215 and selectors 2217 to 2223” operate in the same manner. The selector 2224 outputs “1” when the signal 2226 is “1”.
[0065]
By setting the signal 2226 to “1” using the logic gates 2208 to 2215 and the selectors 2216 to 2224, generation and addition of the partial product 8 of the multiplication “a2 × b2” can be realized. Other partial products can be similarly generated and added. As described above, the configurations shown in FIGS. 3 and 22 can execute the operation of the partial product addition of the multiplication “a2 × b2”.
[0066]
Next, the means having the configuration shown in FIG. 4 is used to eliminate the influence on the multiplication “a1 × b1” due to the result of addition (addition of partial products 1 to 8) for sign extension for performing 32-bit multiplication. This function will be described below.
[0067]
First, a process of adding the values of the 32nd to 25th digits of the partial product 25 (the partial product 1 of the multiplication “a1 × b1” (the partial product 25 in FIG. 2)) by the full adders 400 to 407 is performed. . The full adders 408 to 414 output the addition results up to the partial product 24.
[0068]
The logic gate 415 has a function of setting the sum 433 of the full adder 408 to “0” when the signal 431 is “0”. Similarly, the logic gates 416 to 422 also have a function of setting the sum of the full adders 409 to 414 to “0” when the signal 431 is “0”. The logic gate 423 has a function of setting the carry 432 of the full adder 408 to “0” when the signal 431 is “0”.
[0069]
Similarly, the logic gates 424 to 430 also have a function of setting the carry of the full adders 409 to 414 to “0” when the signal 431 is “0”. When the signal 431 is “1”, the logic elements 415 to 430 have a function of passing the carry and sum values from the full adders 408 to 414 as they are.
[0070]
That is, by setting the signal 431 to “0”, it is possible to control the addition processing of the addition result up to the partial product 24 and the partial product 25. This makes it possible to eliminate the influence on the multiplication “a1 × b1” due to the addition of the sign extension for 32-bit multiplication (addition of partial products 1 to 8).
[0071]
The provision of the means having the configuration shown in FIGS. 3, 22, and 4 described above allows the partial product adder 104 to execute “a1 × b1” and “a2” in the same processing as ordinary 32-bit multiplication. × b2 ”can be performed in parallel.
[0072]
Next, “shift and selector” 107 receives control signal 113 instructing parallel execution of “a1 × b1 + c1” and “a × b2 + c2”, and receives the upper 16 digits of the operation result of partial product adder 104 5 so that the scales of c1 and c2 are correctly aligned with the lower 16 digits, respectively, and c1 and c2 packed as shown by 500 in FIG. 5 are shifted as shown by 501, and "0" is set between c1 and c2. Embed.
[0073]
When the operations of “a1 × b1 + c1” and “a2 × b2 + c2” are not executed in parallel, 500 that is not shifted is selected.
[0074]
As shown in FIG. 5, the three-input full adder sequence 108 outputs the output 503 of the carry save adder of the partial product addition of “a1 × b1” and “a2 × b2” to the upper 16 digits and the lower 16 digits. , And the input 501 selected by the “shift and selector” 107, carry-save addition is performed, and an addition result 506 is obtained. In the case of parallel execution of “a1 × b1 + c1” and “a2 × b2 + c2”, in 501, the value “0” is buried between c1 and c2, so the digits between a1 × b1 + c1 and a2 × b2 + c2 Carry does not occur. As a result, the addition of c1 and c2 does not affect each other.
[0075]
FIG. 6 illustrates a configuration example of the overflow / underflow determination unit 111 that determines in parallel whether an operation result executed in parallel is an overflow or an underflow.
[0076]
The upper-order determination unit 600 and the lower-order determination unit 601 respectively convert the upper 16 bits and the lower 16 bits of 506 shown in FIG. 604 is performed.
[0077]
The upper-order determination unit 600 determines that an overflow has occurred when the contents of the upper 16 bits of 506 shown in FIG. 5 are larger than the 8-bit upper limit value 603, and determines that the overflow is smaller than the 8-bit lower limit value 604. Determines that an underflow has occurred. Further, the lower-order determination unit 601 makes the same determination as the upper-order determination unit 600 on the contents of the lower 16 bits of 506 shown in FIG.
[0078]
The 32-bit determining unit 602 uses the lower 32 bits of 506 as a predetermined value, a 32-bit upper limit value 605 and a 32-bit lower limit value 606, respectively, and performs overflow in the case of 32-bit multiplication. , It is determined whether an underflow has occurred. It should be noted that since the upper-order determination unit 600 and the lower-order determination unit 601 operate separately, the determination of overflow and underflow of the upper and lower 16 bits can be performed in parallel.
[0079]
The determination signals 607 and 608 output by the higher-order determination unit 600 become “1” when the upper 16 bits of 506 overflow and underflow, respectively, and the determination signals 609 and 610 output by the lower-order determination unit 601 become When the lower 16 bits of 506 are overflow and underflow, respectively, it becomes “1”, and the determination signals 611 and 612 output by the 32-bit determination unit 602 are when the lower 32 bits of 506 are overflow and underflow, respectively. It becomes "1".
[0080]
These determination signals 607 to 612 are sent to the maximum / minimum value replacement unit 112 based on the determination results.
[0081]
FIG. 7 shows a case where 64 is used so as to be able to cope with two cases, that is, a case of a normal product-sum operation and a case of executing the parallel operation for obtaining “a1 × b1 + c1” and “a2 × b2 + c2” described above. FIG. 3 shows a configuration diagram of an aligner 110 having a function of controlling an output state of a bit adder 109 (how to extract data from 701).
[0082]
The selector 702 selects “a1 × b1 + c1” between the data 719 (data from the upper 9th bit to the upper 16th bit of 701) and the data 720 (data from the upper 33rd bit to the upper 40th bit of 701). ”And“ a2 × b2 + c2 ”, the control signal 723 becomes“ 0 ”during execution of the parallel operation, and becomes“ 1 ”during normal product-sum operation.
[0083]
Logic gates 703 to 718 (a total of 16 logic gates are shown but two are shown in the figure because of complexity) and are omitted from the control signal 723 are data 721 (lower 24 bits to lower 9 bits of 701). (Up to the first bit) is set to “0” (portion described as 0 value at 724 in the figure).
[0084]
That is, when the parallel operation of “a1 × b1 + c1” and “a2 × b2 + c2” is executed, the control signal 723 becomes “0”. First, the selector 702 selects the data 719, and the d1 part in the figure Secondly, since the logic gates 713 to 718 are AND gates, the data 721 becomes “0”. In addition, since the data 722 does not change, the output of the aligner is like 724.
[0085]
On the other hand, when the control signal 723 becomes “1” during normal product-sum operation, the selector 702 selects the data 720, and the data 721 passes through the logic gates 713 to 718 as it is. Since the data 722 does not change, the output of the aligner is 725.
[0086]
As a result, at the time of executing the parallel operation of “a1 × b1 + c1” and “a2 × b2 + c2”, the operation results d1 and d2 are packed into a 32-bit register like 724.
[0087]
Next, FIG. 8 shows the relationship between the calculation condition and the determination result of the overflow / underflow determination unit 111 and the output of the maximum / minimum value replacement unit 112.
[0088]
The following describes the output mode.
[0089]
First, in the example shown in (1) in FIG. 8, when the operations of “a1 × b1 + c1” and “a2 × b2 + c2” are executed simultaneously, and when the result on the upper side is determined to overflow, the upper output The maximum value (max) which is a predetermined value is output to 8 bits, and the lower 8 bits of the output output the operation result as it is.
[0090]
In the example shown in (2) in FIG. 8, when the upper result is determined to be an underflow, a predetermined minimum value (min) is output to the upper 8 bits of the output, The lower 8 bits of the output output the operation result as it is.
[0091]
Further, in the example shown in (3) in FIG. 8, when the result on the lower side is determined to overflow, the maximum value (max) which is a predetermined value is output to the lower 8 bits of the output, The upper 8 bits of the output output the operation result as it is.
[0092]
In the example shown in (4) of FIG. 8, when the lower result is determined to be an underflow, a predetermined minimum value (min) is output to the lower 8 bits of the output, The upper 8 bits of the output output the operation result as it is.
[0093]
Further, when it is determined that an overflow has occurred during normal product-sum execution, a maximum value that is a predetermined value is output to all 32 bits (example shown in FIG. 8 (5)), and it is determined that an underflow has occurred. In such a case, it is conceivable to output a minimum value that is a predetermined value to the entire 32 bits (FIG. 8 (6)).
[0094]
In addition, when the parallel operation of “a1 × b1 + c1” and “a2 × b2 + c2” is executed, or during normal product-sum execution, if neither overflow nor underflow is determined, the input value is output as it is. (Example of FIG. 8 (7)).
[0095]
Next, an example in which data is packed into all 32 bits, for example, an embodiment of a parallel multiply-accumulate unit that packs four 8-bit pixel data will be described with reference to FIG.
[0096]
The configuration of the present embodiment includes a partial product adder 900 for calculating and adding a partial product from four packed multiplicands a1, a2, a3, and a4 and four packed multipliers b1, b2, b3, and b4. , A "shift and selector" 901 for digit-aligning the four packed addends c1, c2, c3, and c4 with the output of the partial product adder 900; A three-input full adder sequence 902 having a function of adding the output of the adder 901 and a 64-bit adder 903 having a function of adding two outputs of the three-input full adder sequence, and the output of the adder is designated. An aligner 904 for converting to a format, an overflow / underflow determination unit 905 for determining whether or not the addition result is an overflow or an underflow; A maximum value / minimum value replacement unit 906 having a function of replacing the output of the aligner 904 with a predetermined value in accordance with predetermined rules.
[0097]
In the embodiment shown in FIG. 9, the operation of performing a plurality of product-sum operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” is performed with a data length of 32 bits. A case where four 8-bit data are packed will be described as an example.
[0098]
As shown in a data format 1000 shown in FIG. 10, the data on which the product-sum operation is performed constitutes 32-bit data by four data “a1, a2, a3, a4”.
[0099]
Similarly, a1, a2, a3, and a4, and c1, c2, c3, and c4 are also 32-bit data.
[0100]
By multiplying 32-bit data between 32-bit data packed with “a1, a2, a3, a4” and 32-bit data packed with “a1, a2, a3, a4”, multiplication of 8-bit data is performed. a1 × b1 ”,“ a2 × b2 ”,“ a3 × b3 ”, and“ a4 × b4 ”are simultaneously executed.
[0101]
At this time, with reference to FIG. 10, which part of the multiplication result of the 32-bit data corresponds to the multiplications “a1 × b1”, “a2 × b2”, “a3 × b3”, and “a4 × b4” respectively. Will be explained.
[0102]
In FIG. 10, each partial product is represented by a rectangle.
[0103]
The values of the multiplications “a1 × b1”, “a2 × b2”, “a3 × b3” and “a4 × b4” are respectively the partial products 25 to 32, the partial products 17 to 24, the partial products 9 to 16, It is obtained by adding the partial products 1 to 8. Therefore, the portions painted black in the figure are portions that become extension codes of the multiplications “a1 × b1”, “a2 × b2”, “a3 × b3”, and “a4 × b4”.
[0104]
For example, in the multiplication “a4 × b4”, the partial product 1 is from the 9th to the 15th digit, the partial product 2 is the 10th to the 15th digit, the partial product 3 is the 11th to the 15th digit, The extension code is the 12th to 15th digits for the product 4, the 13th to 15th digits for the partial product 5, the 14th to 15th digits for the partial product 6, and the 15th digit for the partial product 7. Part.
[0105]
Similarly to the above-described parallel operation of squaring, the partial products 8, 16, 24, and 32 correspond to sign bits, so that a negative number must be created.
[0106]
Eight of the 32 full adders used for the addition of one partial product include the same logic gates 2208 to 2215 and selectors 2216 to 2224 shown in FIG. With the same connection relationship as 2207, generation and addition of a partial product of a negative number can be realized by addition. The full adder to which the logic gate and the selector are added is composed of the lower 1st to 8th bits for the partial product 8, the 9th to 16th bits for the partial product 16, and the 17th bit for the partial product 24. A full adder corresponding to the 25th to 35th bits of the partial product 32 for the 24th to 24th bits.
[0107]
In the partial product addition of the 32-bit multiplication, it is necessary to prevent the propagation of the addition result between the partial products 8 and 9, the partial products 16 and 17, and the partial products 24 and 25. In the partial products 9 to 16, the lower 8 bits (shaded portion in the drawing) are set to "0", and in the partial products 17 to 24, the lower 16 bits (shaded portion in the drawing) are set to "0". In the partial products 25 to 32, the lower 24 bits (shaded portions in the drawing) are set to “0”. With these functions, the result of the partial product addition of the four multiplications does not affect the others, so that the partial product addition of the four multiplications can be performed in parallel.
[0108]
Next, FIG. 11 illustrates a part of the partial product adder in which the result of the partial product addition of the four multiplications does not affect the others.
[0109]
FIG. 11 shows a function that does not propagate the addition result of the partial product 8 to the addition of the partial product 9 and a function that sets the lower 8 bits of the partial product 9 to “0” and does not destroy the addition results of the partial products 1 to 8. An example of a circuit configuration for realizing is shown.
[0110]
The full adders 1100 to 1107 perform addition processing on the 13th to 6th bits of the partial product 8.
[0111]
In addition, full adders 1108 to 1115 perform addition processing on the 13th to 6th bits of partial product 9. The logic gates 1116 and 1120 have a function of preventing the addition results 1128 and 1129 of the partial product 8 from being input to the full adder 1108 by setting the signal 1133 to “0”. Logic gates 1117 to 1119 and 1120 to 1123 perform the same operation, and have a function of preventing the input of the addition result to the corresponding full adder.
[0112]
Note that the signal 1133 becomes “0” when the 4 multiplication is performed in parallel.
[0113]
Therefore, “0” is input to the full adder 1108 and added to the partial product 9. As a result, the result of addition of the partial product 8 cannot be used for addition from the 10th bit of the partial product 9.
[0114]
Logic gate 1124 has a function of blocking input to full adder 1112, which performs addition processing on the eighth bit of partial product 9 by signal 1142. Similarly, the logic gates 1125 to 1127 perform the same blocking operation in response to the input of the signal 1133.
[0115]
The signal 1142 becomes “0” at the time of parallel operation of quadruple multiplication. Therefore, the value lower than 8 bits of the partial product 9 is “0”.
[0116]
With these configurations, addition up to the partial product 8 and addition of the partial product 9 can be separated using the signals 1133 and 1142 and the logic gates 1016 to 1127. Similarly, the separation of the partial products 16 and 17 and the partial products 24 and 25 can be realized. Therefore, this partial product adder can execute parallel operation of partial product addition of four multiplications.
[0117]
The “shift and selector” 901 receives a control signal indicating that “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” are executed in parallel, and receives a partial product adder. For each of “a1 × b1”, “a2 × b2”, “a3 × b3”, and “a4 × b4” output every 16 digits from the higher order of the result of the above, the added value, c1, c2, c3, Make sure that the scale with c4 matches correctly.
[0118]
Therefore, as shown by 1201, c1, c2, c3, and c4 packed as shown in 1200 in FIG. 12 are converted into the 49th digit in the first bit of c1 and the 33rd digit in the first bit of c2. , C3 are shifted to the 17th digit, and c1, c2, c3 are shifted so that the first bit of c4 is the first digit. In step 1201, a value “0” is embedded in a portion where data of c1, c2, c3, and c4 does not exist. When the parallel operation of “a1 × b1 + c1” and “a2 × b2 + c2” is not performed, the packed data is not shifted as indicated by 1200.
[0119]
FIG. 13 shows the results (sum and carry) of four parallel multiplications of “a1 × b1”, “b2 × b2”, “a3 × b3”, and “a4 × b4” in 16-bit units from the most significant bit, and “shift”. A part of the configuration of a three-input full adder array 902 that adds three inputs selected by the "and selector" and obtains a sum of two outputs of a sum and a carry is shown.
[0120]
The full adder 1300 and the full adder 1301 are used for the operation of the lower two bits when obtaining the operation result of “a3 × b3 + c3”. The full adder 1302 and the full adder 1303 are used for the operation of the upper two bits when obtaining the operation result of “a4 × b4 + c4”.
[0121]
The logic element 1304 generates the digit of the full adder 1302 by the signal 1305 which becomes “0” when the parallel operation of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” is executed. The raising 1306 is blocked.
[0122]
In the figure, the configuration of the middle part of the means for calculating “a3 × b3 + c3” and “a4 × b4 + c4” is shown, but the middle part of the means for calculating “a1 × b1 + c1” and “a2 × b2 + c2”, “a2 × A logic circuit having a similar configuration is also provided at an intermediate portion of the means for calculating “b2 + c2” and “a3 × b3 + c3” to prevent carry.
[0123]
As a result, even if the parallel operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” are executed, the effect of the carry among the four operations can be eliminated. The carry generated at the boundary of each multiplication is sent to an overflow / underflow determination unit for use in determining overflow / underflow.
[0124]
FIG. 14 shows a 64-bit addition having a function of preventing carry at the boundary of each multiplied value in the product-sum operation of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4”. 2 shows a part of the configuration of the vessel. The full adders 1400 and 1401 are used for the operation of the lower two bits when obtaining the operation result of “a3 × b3 + c3”.
[0125]
The full adder 1402 and the full adder 1403 are used for the operation of the upper two bits when obtaining the operation result of “a4 × b4 + c4”. The logic gate 1404 uses the signal 1405 that becomes “0” when the parallel operation of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” is executed, to cause the full adder 1402 Block carry 1406.
[0126]
FIG. 14 shows the configuration of the intermediate part of the means for calculating “a3 × b3 + c3” and “a4 × b4 + c4”. However, the intermediate part of the means for calculating “a1 × b1 + c1” and “a2 × b2 + c2”, “a2 A logic circuit having a similar configuration is also provided at an intermediate portion of the means for calculating “× b2 + c2” and “a3 × b3 + c3” to prevent carry.
[0127]
As a result, even if the parallel operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” are executed, the effect of the carry on other operation results among the four operations Can be eliminated. Also, the carry generated at the boundary of each operation is sent to an overflow / underflow determination unit for use in determining overflow / underflow.
[0128]
Next, FIG. 15 shows a configuration of the overflow / underflow determination unit.
[0129]
1500, 1501, 1502, and 1503 are “a1 × b1 + c1 determination section”, “a2 × b2 + c2 determination section”, “a3 × b3 + c3 determination section”, and “a4 × b4 + c4 determination section”, respectively.
[0130]
1307 to 1310 are obtained by a three-input full adder sequence 902 that executes the operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” in parallel. Carry data.
[0131]
Reference numerals 1407 to 1410 denote carry between each calculation result obtained by the 64-bit adder 903 which executes the calculations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” in parallel. Data.
[0132]
Each determination unit generates a calculation result that does not limit the calculation precision to 8 bits from two carry data of the corresponding calculation and the corresponding calculation result of the output of the 64-bit adder 903, and is determined in advance. , And the upper limit value for 8 bits and the lower limit value for 8 bits to determine whether the operation result overflows or underflows, and outputs the determination result.
[0133]
For example, “a1 × b1 + c1 determination unit” 1500 adds carry 1307 and 1407.
[0134]
The addition result 1504 and the lower 16 bits 1505 of the output of the 64-bit adder are concatenated so that 1504 is higher, and an 18-bit operation result is generated.
[0135]
The newly calculated operation result 1506 is compared with a predetermined upper limit value for 8 bits and a lower limit value for 8 bits to determine overflow and underflow, and a determination result 1507 is output. Similarly, the determination units 1501, 1502, and 1503 also determine overflow and underflow, and output the determination results as 1508, 1509, and 1510, respectively.
[0136]
Further, the 32-bit determination unit compares the lower 32 bits of the output of the 64-bit adder with a predetermined upper limit value for 32 bits and a lower limit value for 32 bits, and determines overflow and underflow of the operation result, The judgment result 1511 is output.
[0137]
Next, FIG. 16 shows the case of a normal product-sum operation and the parallel operation execution of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” described above. A configuration diagram of an aligner 904 having a function of controlling the output state of a 64-bit adder 903 (how to extract data from 1601) so as to be able to cope with two cases is shown. The signal 1600 becomes “0” when the parallel operation of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” is executed, and becomes “1” during the normal product-sum operation. Signal.
[0138]
The selector 1608 selects the data 1603 when the signal 1600 is “1” among the data 1602 (the lower 56 bits to the lower 49 bits of 1601) and the data 1603 (the lower 32 bits to the lower 25 bits of 1601). When the signal 1600 is "0", the data 1602 is selected. When the signal 1600 is “1” among the data 1604 (lower 40th bit to lower 33rd bit of 1601) and data 1605 (lower 24th bit to lower 17th bit of 1601), the selector 1609 outputs the data 1605 Is selected, and when the signal 1600 is "0", the data 1604 is selected.
[0139]
Further, the selector 1610 outputs the data 1606 when the signal 1600 is “1” among the data 1605 (lower 24 bits to lower 17 bits of 1601) and data 1606 (lower 16 bits to lower 9 bits of 1601). Is selected, and when the signal 1600 is "0", the data 1605 is selected.
[0140]
Note that data 1607 (data of lower 8 bits of 1601) is not subjected to selection control by signal 1600. As a result, the signal 1600 becomes “0” during the parallel operation of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4”, so that the register areas d1 and d2 , D3, and d4, data 1602, 1604, 1605, and 1607 are stored, and 32-bit data is packed as indicated by 1611. In a normal product-sum operation, data 1603, 1605, 1606, and 1607 are stored, and 32-bit data indicated by 1612 is stored.
[0141]
The output of the 64-bit adder is an aligner shown in FIG. 16. When the signal 1600 indicates a parallel product-sum operation, that is, 1611 when the signal 1600 is “0”, and in the case of a normal 32-bit product-sum operation, When 1600 is “1”, the data is converted into 32-bit data, such as 1612.
[0142]
Next, the maximum value / minimum value replacement unit 906 receives the determination signal from the overflow / underflow determination unit 905, and receives “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4”. At the time of execution of the parallel operation of "", predetermined processing is performed on each operation result.
[0143]
As the predetermined processing, for example, if the determination result is an overflow, the calculation result is replaced with a predetermined maximum value represented by 8 bits, and if the determination result is an underflow, the calculation result is set to a predetermined value. , 8 bits, and if none of them, outputs the operation result without replacing it.
[0144]
At the time of normal product-sum operation, if the judgment result is an overflow, the operation result is replaced with a predetermined maximum value represented by 32 bits. If the judgment result is an underflow, the operation result is set at a predetermined value. Alternatively, the processing may be performed by replacing with the minimum value represented by 32 bits, and in any case, outputting the calculation result without replacing it.
[0145]
With the configuration as described above, the operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” can be performed separately, and a 32-bit general-purpose multiply-accumulate unit can be implemented. By using this, it is possible to execute the respective operations of “a1 × b1 + c1”, “a2 × b2 + c2”, “a3 × b3 + c3”, and “a4 × b4 + c4” in parallel.
[0146]
Of course, by applying the technical idea of the present invention in consideration of the number of operation bits, not only the partial product-sum operation of “32 bits × 32 bits” shown in the present embodiment, but also A product-sum operation can be performed.
[0147]
FIG. 17 shows an example of an instruction code for a microprocessor having a product-sum operation unit or a multiplier according to the present invention. The operation codes 1700 to 1703 are defined by the type of operation. The operands 1704 to 1707 specify a source register and a target register of data used for the operation.
[0148]
The opcodes 1700 and 1702 perform parallel operations, respectively, and are used when performing a plurality of multiplication or multiply-accumulate operations at the same time. Further, the operation codes 1701 and 1703 are used when performing a normal multiplication or a product-sum operation, respectively.
[0149]
Taking the parallel operation of two data as an example, the operation code 1700 “SplitMPY” is obtained by storing the data a1 stored in the source register r1 in which a1 and a2 are packed and the source register r2 in which b1 and b2 are packed. , A2, b1, and b2, the multiplication “a1 × b1” and “a2 × b2” are performed in parallel, and the result is stored in the target register r3.
[0150]
Further, the operation code 1702 “SplitMPYADD” includes a source register r1 in which a1 and a2 are packed, a source register r2 in which b1 and b2 are packed, and a source register r3 (r3 in which c1 and c2 are packed). Using the data a1, a2, b1, b2, c1, and c2 stored in the target register), a multiply-accumulate operation “a1 × b1 + c1” and “a2 × b2 + c2” are performed in parallel. This is an instruction to be stored in the register r3 also serving as a target register.
[0151]
In the parallel operation of four data, only the number of data and the number of executions of the parallel operation are different, and an instruction code can be set similarly.
[0152]
On the other hand, the operation code 1701 “ConnectMPY” performs the multiplication “R1 × R2” using the values of the registers r1 and r2 (the values are R1 and R2, respectively) shown in 1705, and stores the result in the register r2. Instruction. Also, 1703 “ConnectMPYADD” performs a product-sum operation “R1 × R2 + R3” using the values of the registers r1, r2, and r3 shown in 1707 (the values are R1, R2, and R3, respectively), and outputs the result. , An instruction to be stored in a register r3 also serving as a target register.
[0153]
In the architecture having only the operation code 1703, when executing the operations of “a1 × b1 + c1” and “a2 × b2 + c2”, it is necessary to instruct twice. However, as described above, the operation code 1702 is defined and the parallel operation is performed. This makes it possible to execute the parallel product-sum operations “a1 × b1 + c1” and “a2 × b2 + c2” with one instruction.
[0154]
Similarly, for the multiplication, the number of necessary instructions is reduced by defining the operation code 1700 as compared with the case where the operation code 1701 is used.
[0155]
As a result, the program is shortened and the program is stored in the memory.Thus, the use of these instructions makes it possible to reduce the capacity of the memory. It is effective when it becomes.
[0156]
Next, FIG. 18 shows another embodiment according to the present invention.
[0157]
FIG. 18 includes at least one of a multiplier (for example, a unit for performing an operation “a1 × b1”) and a product-sum operation unit (for example, a unit for performing an operation “a1 × b1 + c1”) according to the present invention. 1 is a configuration diagram of a system having a microprocessor 1800.
[0158]
The storage device stores a program that determines processing executed by the microprocessor 1800, necessary data, and the like. In this system, it is assumed that the microprocessor 1800 performs certain image processing according to the program. The processed image is displayed on a display device 1802 realized by a CRT or the like. Such display processing is performed by the microprocessor 1800 according to a predetermined program.
[0159]
Now, in image processing, it is necessary to frequently perform a product-sum operation, and it is assumed that data necessary for the product-sum operation is stored in the storage device 1801.
[0160]
The product-sum operation unit 1803 is a product-sum operation unit according to the present invention, and executes a plurality of product-sum operations in parallel.
[0161]
It is assumed that a register 1804 in a microprocessor performs a product-sum operation using data stored in a storage device 1801.
[0162]
When the execution of the product-sum operation is instructed by the program, the microprocessor 1800 accesses the storage device 1801 and holds data necessary for the product-sum operation in the register 1804 included in the microprocessor 1800 via the bus 1805. Only data necessary for one product-sum operation may be accessed. However, since a plurality of product-sum operations are usually performed at once, all the relevant data is held in the register 1804. Note that examples of multiplicand data (a1, a2, a3, a4), multiplier data (b1, b2, b3, b4), and addition data (c1, c2, c3, c4) held in the register 1804 are shown in FIG. Shown on the left. In the figure, one set of data for performing one product-sum operation is shown, but usually, a plurality of sets of data are held.
[0163]
Then, the product-sum operation unit is activated. First, all the data required for the product-sum operation in the register 1804 is fetched via the source bus.
[0164]
The sum-of-products arithmetic unit performs the above-described sum-of-products calculation based on the fetched data, and sequentially sends the calculation results to the empty area of the register 1804 via the target bus and holds the same. Of course, when performing image processing in which the calculation result is used later, it may be stored in the storage device 1801.
[0165]
Since the product-sum operation unit according to the present invention can simultaneously perform a plurality of types of product-sum operations, the processing speed of image processing is significantly improved.
[0166]
Since a plurality of product-sum operations can be repeatedly executed in parallel, for example, the product-sum operation is repeatedly performed, and high-speed processing can be performed even for processing such as discrete cosine transform, which is frequently performed in image processing. You.
[0167]
As described above, a microprocessor incorporating the product-sum operation unit (multiplier) according to the present invention is realized, and by using the microprocessor, for example, a system capable of performing high-speed image processing can be constructed. . Of course, the processing contents targeted by the system are not limited to image processing, and may be any processing that performs a large amount of product-sum operation.
[0168]
【The invention's effect】
As described above, according to the present invention, since a plurality of sum-of-products operations can be executed in parallel, a plurality of sum-of-products operations can be performed at an extremely high speed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment according to the present invention.
FIG. 2 is an explanatory diagram of sign extension and separation functions of multiplication.
FIG. 3 is a configuration diagram of means for realizing a sign extension function of a partial product adder.
FIG. 4 is a configuration diagram of means for realizing a separating function of a partial product adder;
FIG. 5 is an explanatory diagram of an operation of a “shift and selector”.
FIG. 6 is a configuration diagram of an overflow / underflow determination unit.
FIG. 7 is a configuration diagram of an aligner.
FIG. 8 is an explanatory diagram of a maximum value / minimum value replacement process.
FIG. 9 is a configuration diagram of another embodiment according to the present invention.
FIG. 10 is an explanatory diagram of sign extension and separation functions of multiplication.
FIG. 11 is a configuration diagram of a partial product adder.
FIG. 12 is an explanatory diagram of an operation of a “shift and selector”.
FIG. 13 is a configuration diagram of a three-input full adder array.
FIG. 14 is a configuration diagram of a 64-bit adder.
FIG. 15 is a configuration diagram of an overflow / underflow determination unit.
FIG. 16 is a configuration diagram of an aligner.
FIG. 17 is an explanatory diagram of a product-sum operation instruction.
FIG. 18 is a configuration diagram of another embodiment according to the present invention.
FIG. 19 is an explanatory diagram of a conventional multiplication process.
FIG. 20 is an explanatory diagram of a conventional partial product adder.
FIG. 21 is an explanatory diagram of an input / output relationship of a full adder.
FIG. 22 is a configuration diagram of means for realizing a negative partial product addition function.

Claims (6)

An arithmetic unit for calculating a product of an N-bit number having a plurality of multiplicands and an M-bit number having a multiplier corresponding to each of the multiplicands to obtain a multiplication result for a set of the multiplicand and the multiplier,
A plurality of 8-bit multiplicands are held, arranged under the condition that the sum of the bit lengths of each multiplicand does not exceed N (N is 32 bits) , and N bits are embedded with 0 embedded between each multiplicand. A first register for holding a number;
An 8-bit multiplier corresponding to each of the multiplicands is held, arranged under the condition that the sum of the bit lengths of the respective multipliers does not exceed M (M is 32 bits) , and 0 is embedded between the multipliers. , A second register holding the number of M bits;
A partial product processing unit for performing a process of calculating a partial product of the value held in the first register and the value held in the second register;
A sign extension unit that embeds bits obtained by expressing a result of the multiplication in 2's complement to compensate for a sign of the multiplication result of the set of the multiplicand and the multiplier in the partial product;
Means for sequentially calculating the sum of each partial product after the sign extension is performed by the sign extension unit, wherein when the sum of all partial products for a certain set of multiplicand and multiplier exceeds a predetermined value, Summing means for calculating the sum of each partial product, discarding the exceeded value when calculating the sum of partial products for the next other set of multiplicands and multipliers;
From the data of the sum value (“N + M” (bits)) obtained by the summing means, a value that is a multiplication result of each multiplicand in the first register and the corresponding multiplier in the second register is cut out, and the multiplicand A processing unit for obtaining a multiplication result corresponding to a set with a multiplier for each set. In claim 1,
Further, a plurality of addition numbers for adding a value to a multiplication result of each multiplicand in the first register and a corresponding multiplier in the second register are held, and a total sum of bit lengths of each addition number is determined in advance. A third register which is arranged on condition that the length does not exceed a predetermined length, embeds 0 between each addition number, and holds the addition number;
An arithmetic unit comprising: an adder for adding an addition number in a third register corresponding to a result of multiplication of each multiplicand in the first register and a corresponding multiplier in the second register. In any one of claims 1 and 2,
If the multiplication result of each multiplicand in the first register and the corresponding multiplier in the second register is an overflow or an underflow, a multiplication value replacement unit that sets the multiplication result to a predetermined value is provided. An arithmetic unit, comprising: An arithmetic unit for calculating a product of an N-bit number having a plurality of multiplicands and an M-bit number having a multiplier corresponding to each of the multiplicands to obtain a multiplication result for a set of a multiplicand and a multiplier,
A first register for holding a number of N bits, wherein the first register holds a plurality of multiplicands and is arranged on condition that the sum of bit lengths of each multiplicand does not exceed N;
A second register holding an M-bit number, holding a multiplier corresponding to each of the multiplicands, and arranging on condition that a sum of bit lengths of each multiplier does not exceed M;
A partial product processing unit for performing a process of calculating a partial product of the value held in the first register and the value held in the second register;
In the partial product, a sign extension unit that performs sign extension for embedding bits obtained by expressing the result of the multiplication in 2's complement to compensate for the sign of the result of the multiplication of the set of the multiplicand and the multiplier;
After calculating all partial products for a certain set of multiplicands (a bits) and multipliers (b bits), when obtaining partial products for the next other set of multiplicands and multipliers, the partial product for the set is Partial product knitting means for embedding 0 in a bit corresponding to a set before the set ;
Means for sequentially calculating the sum of each partial product, wherein when the sum of all partial products for a certain set of multiplicands and multipliers exceeds a predetermined value, the exceeded value is compared with the next other set of multiplicands. Summing means for calculating a sum value of each partial product, which is discarded when calculating a sum of partial products with respect to the multiplier;
From the data of the sum value (“N + M” (bits)) obtained by the summing means, a value that is a multiplication result of each multiplicand in the first register and the corresponding multiplier in the second register is cut out, and the multiplicand A processing unit for obtaining a multiplication result corresponding to a set with a multiplier for each set. In claim 4,
Further, a plurality of addition numbers for adding a value to a multiplication result of each multiplicand in the first register and a corresponding multiplier in the second register are held, and a total sum of bit lengths of each addition number is determined in advance. A third register for holding an addition number, which is arranged on condition that the length does not exceed a predetermined length;
An arithmetic unit comprising: an adder for adding an addition number in a third register corresponding to a result of multiplication of each multiplicand in the first register and a corresponding multiplier in the second register. An arithmetic unit according to claim 1, 2, 4, or 5,
When a predetermined instruction code is found supplied, a data input unit to provide data to the arithmetic unit,
Activating means for activating the computing unit;
A data output unit for obtaining and outputting the operation result of the operation unit.

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