KR100251547B1 - Digital signal processor - Google Patents

Abstract

PURPOSE: A digital signal processor is provided to reduce time required for rounding-processing data by performing data rounding simultaneously with processing data saturation, thereby processing signals at high speed, and to promptly perform fixed-point and integer operations by arranging bit aligners in front and rear ends of an accumulator with simplifying the construction of a circuit. CONSTITUTION: The first and second input elements(30,40) input N bit data. The first operation element(58) operates data from the first and second input elements(30,40). The second operation element(72) operates data from any one of the first operation element(58), and the first and second input elements(30,40). The third operation element operates data from the first operation element and data from the first and second input elements.

Description

Digital Signal Processor

The present invention relates to a digital signal processor (hereinafter referred to as a "DSP") for processing various digital signals by software.

DSP is a type of central processing unit (CPU) that has arithmetic functions. It was originally developed by the US electronics company "Texas Instruments" ("TI"). This DSP has recently been applied to the processing of video and audio signals, and its use has increased rapidly, especially audio compression, which has been established as an international standard by the Moving Picture Expert Group (MPEG) among various processing methods of audio signals. DSPs that implement the algorithm "Musicam" or "Dolby" 's digital audio compression and restoration algorithm "AC-3" are rapidly appearing. Many companies in the US, in particular, are spurring the development of their own DSPs to increase their profits.

The DSP for audio signal processing has a longer word length for internal operation compared to the fixed-point DSP of TI, which has been commonly used up to now. For example, the DSP of the TMS320C5x series of "TI" has a 16-bit data word length and a 32-bit Arithmatic Logic Unit ("ALU"), while the "Pacific" of MEPG The latest DSPs, developed to implement Cam and Dolby's "AC-3", have almost 20-bit data word lengths and 48-bit ALUs. More specifically, "YSS243" from "Yamaha", "DSP5600x" from "Motorola", "CS2923" from "Crystal Semicon duc to r" and "Medianics Semicon" DSPs, such as MED25201, manufactured by Ducter, Inc., all have 24 bits of word length and 56 bits of ALU to decode audio signals of "Dolby" "AC-3". In addition, DSPs such as "ZR38000" from "Zoran" and "MB86342" from Fujitsu all have a data bit length of 20 bits to decode audio signals of "AC-3" from "Dolby". It has a 48-bit ALU.

The DSPs configured as described above operate two data having a length of N bits as shown in FIG. The first and second data 10, 12 are read from the memory and multiplied by a multiplier to generate third data that is the result of the multiplication. The first and second data 10, 12 each have a length of N bits and is composed of an integer part and a fractional part. The third data 14, which is a multiplication result of the multiplier, may have a maximum length of 2N bits, and is thus temporarily stored in a 2N bit multiplication register. Subsequently, the third data 14 is shifted by the barrel shifter by the number of bits, for example, R bits, of the integer parts of the first and second data 10 and 12, and thus 2N, which is the shift result. The fourth data 16 of the bit is calculated. The fourth data 16 is logically operated by the ALU to generate the fifth data 18. Overflow may occur in the fifth data 18 that is an operation result of the ALU. In order to deal with this overflow, the fifth data 18 is saturated in a DSP such as "TMS320C5x" of "TI". In detail, when the fifth data 18 calculated by the ALU has a bit length that is difficult to be stored in the 2N bit accumulation register, that is, when an overflow occurs in the fifth data 18, the DSP of "TMS320C5x" is generated. Saturates the fifth data 18 and stores the saturated fifth data 18 in the accumulation register to alleviate the error due to overflow. In contrast, DSPs such as "DSP5600x" from Motorola, Inc. add bits to the accumulation register for overflow protection, as in FIG. In this case, both the ALU and the accumulation register have a length of "8 + 2N" bits. Applying this overflow protection bit to the "AC-3" dedicated DSPs listed above, DSPs with 24-bit data word lengths have 56-bit accumulators and 20-bit data word lengths since the data is N = 24 bits. Since DSPs have N = 20 bits, each of them has a 48-bit accumulator. The fifth data 18 to which the overflow protection bits are added is converted into sixth data 20 having the same bit length as the first and second data 10 and 12 stored in the memory by being saturated.

In order to perform the above series of operations, most DSPs had to have ALUs and cumulative registers having a large word length of 48 bits or more. These ALUs and accumulators, which have large word lengths of more than 48 bits, increase the die size on the DSP chip and increase the amount of propagation delay in the ALU. Therefore, the ALU and accumulator having a large word length not only increases the manufacturing cost of the DSP chip but also acts as a factor of decreasing the operation speed of the DSP.

Most DSPs support rounding operations before saturating the data. For example, the "Motorola" DSP converts "8 + 2N" bits of data stored in the accumulation register into "8 + N" bits by the command "rnd". This rounded data is finally saturated with "N" bits of data and then stored in memory. For these rounding operations, most DSPs consume an additional instruction or clock period. This additional consumption of instructions or clock cycles results in a large number of additional clock cycles when the rounding operation is applied to the code segment to which looping or block repeating is applied. The amount of computation is greatly increased.

In addition, DSPs such as "TMS320C5x" from "TI" use a pre-scaling shifter located in front of the ALU to shift the binary data to be computed in the ALU to the left from 0 to 16 bits. At this time, the shift operation from the "0" th bit to the "15" th bit is normally used to scale binary data, but the shift operation up to the "16" th bit is a fixed point, not an integer operation. Used when an operation is performed. This is because in the case of fixed-point arithmetic, 16-bit data read from memory must be aligned with the upper bits of the 32-bit accumulation register. Shift operations from the "0" th bit to the "15" th bit for scaling data may or may not be usefully used depending on a given algorithm, in particular, a coding method. When performing algorithms implemented in code where prescaling is not useful, the scaling shifter increases the DSP chip die size and increases propagation delay without much help. In one example, the pre-scaling shifter included in the "Motorola" DSP is to shift data one bit to the left or to the right. Instead, Motorola's DSPs offer different multiply instructions for floating-point and integer operations, absorbing the "TI" 's "TMS320C5x" shifting data left by 16 bits.

Next, in DSP, it is important to know how fast each instruction can be executed. For fast execution of instructions, the period of instructions applied to the DSP should be shortened and as many instructions as possible should be processed in parallel. Shortening the former instruction cycle is a hardware-, circuit-related problem that shortens the circuit path by eliminating unnecessary blocks (e.g., the pre-scaling shifters already mentioned) possible in the DSP. The parallelism of the latter instruction comes from the fact that DSPs are used for video / audio decoding, which requires a lot of computation, and the same sequential instruction execution method does not have the necessary computational capability. Therefore, DSPs are equipped with special instructions capable of parallel processing. For example, "DSP21020" DSP, "Analog Device", has special instructions for performing multiple complex expressions in a few clock cycles, such as a butterfly operation for FFT operations. For this purpose, the "ADSP21020" has a register file consisting of at least 12 registers associated with the operation. In addition, Zor38000 also performs many complex equations, such as butterfly for FFT, in just a few clock cycles. To this end, the ZR38000 has a register file consisting of eight registers and a structure that performs multiplication and addition and subtraction of the result in one clock cycle.

Accordingly, an object of the present invention is to provide a digital signal processing method and a DSP capable of performing a plurality of complex computational expressions in parallel.

Another object of the present invention is to provide a DSP capable of performing an operation including a scale of a logic value at a high speed.

Another object of the present invention is to provide a DSP capable of efficiently performing integer operations and fixed-point operations.

1 is a diagram schematically showing a signal processing procedure of a conventional DSP.

2 is a block diagram of a DSP according to an embodiment of the present invention.

FIG. 3 is a diagram showing a part of a circuit for performing a computation of two or more complex calculation equations in the DSP shown in FIG.

* Explanation of symbols for main parts of the drawings

30, 40, 44, 48, 64, 66, 76, 78: first through eighth registers

32, 34, 82, 84: first to fourth bit sorter

38: Guard bit addition

36, 42, 52, 54, 56, 62, 68, 70, 74, 80, 88: first to eleventh multiplexers

46: multiplier 48: beat controller

58, 72: first and second ALU 60: barrel shifter

86: rounding / saturation processor

In order to achieve the above object, the digital signal processing method according to the present invention comprises the steps of calculating the data from the first and second input lines by using a first calculation means, and the data calculated by the first calculation means. Calculating data from one of the first and second input lines using a second calculating means, and inputting the data calculated by the first calculating means to either one of the first and second input lines. Calculating data from the data using third computing means.

The digital signal processing method according to the present invention comprises the steps of computing data from the first and second input lines by using a first calculation means, data calculated by the first calculation means, and first and second input lines. And calculating data from one of the first feedback lines connected to the first register file by using the second calculating means, the data calculated by the first calculating means, and the first and second input lines; Calculating data from one of the second feedback lines connected to the second register file by using the third calculation means.

The digital signal processing method according to the present invention comprises the steps of computing data from the first and second input lines by using a first calculation means, data calculated by the first calculation means, and first and second input lines. Calculating data from any one of a first feedback line connected to a first register file and a second feedback line connected to a second register file using a second calculation means connected to the first register file. And calculating the data calculated by the first calculating means and the data from either one of the first and second input lines and the first and second feedback lines using the third calculating means connected to the second register file. It includes a step.

DSP according to the present invention includes first and second input means for inputting N bits of data, first calculation means for calculating data from the first and second input means, and data from the first calculation means. And second calculating means for calculating data from either one of the first and second input means, and third calculating means for calculating data from the first calculating means and data from the first and second input means. do.

The DSP according to the present invention comprises a first and second input means for inputting N bits of data, first computing means for calculating data from the first and second input lines, and first computing means. Second calculation means for calculating the calculated data and data from any one of the first and second input lines and the first feedback line, data calculated by the first calculation means, and first and second input lines; Third computing means for computing data from any one of the second feedback lines, a first register file connected to the first feedback line for temporarily storing data from the second computing means, and a second feedback line. And a second register file for temporarily storing data from the third computing means.

DSP according to the present invention includes first and second input lines for inputting data, first calculation means for calculating data from the first and second input lines, and data from the first calculation means. Second computing means for computing data from any one of the first and second input lines, the first feedback line and the second feedback line, data from the first calculation means, first and second input lines, and first And third computing means for computing data from any one of the second feedback lines, a first register file connected to the first feedback line for temporarily storing data from the second computing means, and a second feedback line. And a second register file for temporarily storing data from the third computing means.

DSP according to the present invention includes first and second input means for inputting N bits of data, first computing means for calculating data from the first and second input means, and first and second input means. And scaling means for scaling up data from either of the first calculation means, and a second operation for calculating data from the first calculation means and data from any one of the first and second input means and the scaling means. Means; and third computing means for computing data from the first computing means and data from either one of the first and second input means and the scaling means.

The DSP according to the present invention comprises a first and second input means for inputting N bits of data, first computing means for calculating data from the first and second input lines, and first computing means. Second calculation means for calculating the calculated data and data from any one of the first and second input lines and the first feedback line, data calculated by the first calculation means, and first and second input lines; Skating the data from any one of the first calculation means, the first and second input lines, and the first and second feedback lines; Up a scaling means, a first register file connected to the first return line to temporarily store data from the second calculation means and the scaling means, and a third register connected to the second return line from the third calculation means and the scaling means. Data temporarily And a second register file for storing a.

DSP according to the present invention includes first and second input lines for inputting data, first calculation means for calculating data from the first and second input lines, and data from the first calculation means. Second computing means for computing data from any one of the first and second input lines, the first feedback line and the second feedback line, data from the first calculation means, first and second input lines, and first And third computing means for computing data from any one of the second feedback lines, and scaling data from any one of the first computing means, the first and second input lines, and the first and second feedback lines. Up a scaling means, a first register file connected to the first return line to temporarily store data from the second calculation means and the scaling means, and a third register connected to the second return line from the third calculation means and the scaling means. Data A second register file for temporary storage is provided.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter for shifting the N-bit data from the means to the left by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the left by r bits, second calculating means for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters, and a first operation. Third-order calculation means for calculating data from the means and data from one of the first and second fixed shifters, and the upper N bits in the data from either of the first and second calculation means. An extraction means for extracting comprises a.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting the N bits of data from the first input means to the right by r bits, and a second input. A second fixed shifter for shifting the N-bit data from the means to the right by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, second operating means for calculating data from the bit adjusting means and data from either the first or second fixed shifter, and the first operation. Third operating means for computing data from the means and data from one of the first and second fixed shifters, and the lower N bits in the data from either one of the first and second computing means. An extraction means for extracting comprises a.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter shifting left by N bits to the N-bit data from the means; a third fixed shifter shifting right by r bits to the N-bit data from the first input means; and N bits from the second input means. A fourth fixed shifter shifting the data to the right by r, first selecting means for selecting data from any one of the first and third fixed shifters, and data from any one of the second and fourth fixed shifters. The second selecting means for selecting, the first calculating means for multiplying the data from the first and second input means, the data from the first calculating means by N bits and the adjusted data left by r bits. First bit adjusting means for shifting to the side, second bit adjusting means for adjusting the data from the first calculating means to N bits and shifting the adjusted data to the right by r bits, and first and second bit adjusting means. Third selecting means for selecting data from either one, second calculating means for calculating data from the third selecting means and data from any one of the first and second selecting means, and from the third selecting means. Second calculating means for calculating data and data from either one of the first and second selecting means, first extracting means for extracting only the upper N bits from data from any one of the first and second calculating means; Second extracting means for extracting only the lower N bits from data from either one of the first and second computing means, and fourth selecting means for selecting data from either one of the first and second extracting means; The rain.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter for shifting the N-bit data from the means to the left by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the left by r bits, and second computing means for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. And third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line, and second computing means connected to the first feedback line. From the first register file for temporarily storing data from the second register file, the second register file connected to the second return line for temporarily storing data from the third computing means, and the first and second register files. And extracting means for extracting only the upper N bits from the data.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting the N bits of data from the first input means to the right by r bits, and a second input. A second fixed shifter for shifting the N-bit data from the means to the right by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and second computing means for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. And third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line, and second computing means connected to the first feedback line. From the first register file for temporarily storing data from the second register file, the second register file connected to the second return line for temporarily storing data from the third computing means, and the first and second register files. And extracting means for extracting only the lower N bits from the data.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter shifting left by n bits from the N-bit data from the means, a third fixed shifter shifting right by r bits to the N-bit data from the first input means, and N from the second input means. A fourth fixed shifter shifting the bit data to the right by r bits to the right, first selecting means for selecting data from any one of the first and third fixed shifters, and from any one of the second and fourth fixed shifters. Second selection means for selecting data, first calculation means for multiplying data from the first and second input means, and adjusting the data from the first calculation means to N bits and adjusting the adjusted data to r ratio. First bit adjusting means for shifting the left side by the first bit, and second bit adjusting means for adjusting the data from the first calculating means to N bits and shifting the adjusted data to the right by r bits, and the first and second bits. Third selecting means for selecting data from either of the adjusting means, second computing means for calculating data from the third selecting means, and data from any one of the first and second selecting means and the first return line. And second computing means for computing data from the third selecting means and data from any one of the first and second selecting means and the second feedback line, and from the second computing means connected to the first feedback line. Any one of a first register file for temporarily storing data, a second register file connected to a second return line for temporarily storing data from the third continuous means, and one of the first and second register files; First extracting means for extracting only upper N bits from data from one side, second extracting means for extracting only lower N bits from data from either one of the first and second register files, and first and second extracting means. And fourth selecting means for selecting data from either one.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shift for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter for shifting the N-bit data from the means to the left by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. And bit control means for shifting the adjusted data to the left by r bits, data from the bit control means, and data from any one of the first and second fixed shifters and the first and second feedback lines. A second operation means, a third operation means for calculating data from the first operation means, data from one of the first and second fixed shifters and the first and second feedback lines, and a first feedback line A first register file for temporarily storing data from the second computing means, a second register file connected to the second return line for temporarily storing data from the third computing means, and first and second register files And extracting means for extracting only the upper N bits from the data from either one.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting the N bits of data from the first input means to the right by r bits, and a second input. A second fixed shifter for shifting the N-bit data from the means to the right by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and second computing means for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. And third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line, and second computing means connected to the first feedback line. From the first register file for temporarily storing data from the second register file, the second register file connected to the second return line for temporarily storing data from the third computing means, and the first and second register files. And extracting means for extracting only the lower N bits from the data.

The DSP according to the present invention includes first and second input means for inputting N-bit data, a first fixed shifter for shifting left by n bits to N-bit data from the first input means, and the second input. A second fixed shifter shifting left by n bits from said N-bit data from the means, a third fixed shifter shifting right by r bits to N-bit data from said first input means and from said second input means; A fourth fixed shifter shifting the N-bit data to the right by r bits, first selecting means for selecting data from any one of the first and third fixed shifters, and from any one of the second and fourth fixed shifters. Second selection means for selecting data of the first data, first calculation means for multiplying data from the first and second input means, and adjusting the data from the first calculation means with N bits and adjusting the data. First bit adjusting means for shifting the left to the left by r bits, second bit adjusting means for adjusting the data from the first calculating means to N bits and shifting the adjusted data to the right by r bits, Third selecting means for selecting data from either of the second bit adjusting means, data from the third selecting means, and data from any one of the first and second selecting means and the first and second feedback lines; Second calculation means for calculating a data, second calculation means for calculating data from the third selection means, and data from any one of the first and second selection means and the first and second feedback lines; A first register file connected to a return line for temporarily storing data from said second computing means, and a second register connected to a second feedback line for temporarily storing data from said third computing means First extraction means for extracting only the upper N bits from the data from either the stub file or the first and second register files, and extracting only the lower N bits from the data from any one of the first and second register files. Second extraction means and fourth selection means for selecting data from either one of the first and second extraction means.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shifter shifting the N-bit data from the means to the left by r bits, first computing means for multiplying data from the first and second input means, and data from the first computing means with N bits. Bit adjusting means for adjusting and shifting the adjusted data to the left by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Means, third computing means for calculating data from the bit adjusting means and data from one of the first and second fixed shifters and the second feedback line, and a second station connected to the first naturalization line. A first register file for temporarily storing data from the means, a second register file connected to a second return line for temporarily storing data from the third computing means, and first computing means, first and first. Scaling means for scaling up data from one of the second input line and the first and second feedback lines, and a first connected to the first feedback line to temporarily store data from the second computing means and the scaling means. Only the upper N bits of the register file, the second register file connected to the second feedback line to temporarily store data from the third calculation means and the scaling means, and the data from either one of the first and second register files. Extracting means for extracting is provided.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting the N bits of data from the first input means to the right by r bits, and a second input. A second fixed shifter for shifting the N-bit data from the means to the right by r bits, the first computing means for multiplying the data from the first and second input means, and the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and second computing means for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line, the bit adjusting means, the first and second fixed shifters, Scaling means for scaling up data from either of the first and second feedback lines, a first register file connected to the first feedback line for temporarily storing data from the second computing means and the scaling means, Extraction means connected to the second feedback line for temporarily storing data from the third computing means and the scaling means, and extracting means for extracting only the lower N bits from data from either one of the first and second register files; It is provided.

The DSP according to the present invention includes first and second input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the first input means, and a second input. A second fixed shift shifted to the left by n bits from the N-bit data from the means, a second fixed shifter, a third fixed shifter shifted to the right by r bits to the N-bit data from the first input means, A fourth fixed shifter for shifting right by n bits to the N-bit data from the second input means, first selecting means for selecting data from either one of the first and third fixed shifters, and second and fourth fixed means; Second selection means for selecting data from either of the shifters, first calculation means for multiplying data from the first and second input means, and adjusting the data from the first calculation means with N bits, First bit adjusting means for shifting the truncated data to the left by r bits, second bit adjusting means for adjusting the data from the first computing means to N bits and shifting the adjusted data to the right by r bits, And third selecting means for selecting data from either one of the second bit adjusting means, data from the third selecting means and from any one of the first and second selecting means and the first and second feedback lines. Second calculation means for calculating data, third calculation means for calculating data from the third selection means, and data from any one of the first and second selection means and the first and second feedback lines, and the first Scaling means for scaling up data from one of the third to third selecting means and the first and second feedback lines, and connected to the first feedback line to temporarily store data from the second computing means and the scaling means. A first register file to be stored in a second register file, a second register file connected to a second return line to temporarily store data from the third calculating means and the scaling means, and either of the first and second register files. First extraction means for extracting only the upper N bits from the data, second extraction means for extracting only the lower N bits from the data from either one of the first and second register files, and either one of the first and second extraction means. And fourth selecting means for selecting data from the apparatus.

Other objects and advantages of the present invention other than the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

2, a first register 30 for inputting N bits of data from the first external bus 31, and first and second bit aligners connected in parallel to the first register 30. Referring to FIG. A DSP in accordance with an embodiment of the present invention having (32, 34) is shown. The first external bus 31 is composed of N data lines commonly connected to a working memory (not shown), and is used as an N-bit first read data bus. The first register 30 temporarily stores N bits of data from the memory via the first external bus 31. The first and second bit sorters 32 and 34 serve to extend data from N bits to N + r bits by shifting N bits of data from the first register 30. In detail, the first bit sorter 32 shifts N bits of data to the left by r bits for fixed-point arithmetic. To this end, the first bit sorter 32 includes N-bit output lines of the first register 30 among the upper N input terminals of the first input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The second bit sorter 34 shifts N bits of data to the right by r bits for integer arithmetic. At this time, the upper r bits may be filled as sine (positive or negative) bits or filled with values of "0" according to the DSP's Sign-Extension Mode. To this end, the second bit sorter 34 has N-bit output lines of the N-bit output lines of the first multiplexer 36 of the N input terminals of the N-bit output lines of the first register 30. Wiring to be connected to each other. The upper r bits are filled with the sign bit or "0" as mentioned above. The first multiplexer 36 receives N + r bits of data on the first input port or N + r bits of data on the second input port according to the type of operation, that is, fixed-point / integer operation. ) Is supplied to the adder 38. This first guard bit adder 38 adds g bits of guard bits to N + r bits of data from the first multiplexer 36. The gbit guard bits are either all set to "0" or they extend the sign of the data. In detail, all gbit guard bits have the same logical value as the sign bit of data when the sign-extension mode is set, and all logic values of "0" when the sign-extension mode is reset. . The sign-extension mode is set or reset by a particular instruction. In order to add these g-bit guard bits to the data of the N + r bits, the first guard bit adder 38 connects the output port of the first multiplexer 36 composed of N + r terminals to the first internal bus. Among the g + N + r lines included in 35), the lower N + r lines have wirings connected to the lines.

The DSP adds a second register 40 and a multiplier 46 connected in series to the first external bus 31 and a second multiplexer 42 connected to the first and second external buses 31 and 33. It is provided with. Like the first register 30, the second register 40 is responsible for temporarily storing N-bit data from the memory input via the first external bus 31. The second external bus 33 is composed of N lines commonly connected to a program memory and a CPU (not shown) and is used as a second read-only data bus. The second multiplexer 42 includes N bit data from the first external bus 31 supplied to its first input port and N bit data from the second external bus 33 supplied to its second input port. One data is supplied to the third register 44. The third register 44 temporarily stores N-bit data from the second multiplexer 42. Multiplier 46 multiplies two data stored in second and third registers 40 and 44. The result multiplied by this multiplier 46 may have 2N bits. Accordingly, the fourth register 48 which temporarily stores data from the multiplier 46 has a length of 2N bits. The wiring controller 50 connected between the fourth register 48 and the second internal bus 37 converts 2N bits of data stored in the fourth register 48 into N + r bits of data smaller than 2N. A g-bit guard bit is added to the converted N + r-bit data.

The DSP includes third to fifth multiplexers 52 to 56 that are commonly connected to the first internal bus 35. The third multiplexer 52 has first to third input ports for inputting g + N + r bits of data from the first, second and fourth internal buses 35, 37 and 43, respectively. The third multiplexer 52 supplies any one of three data from the first, second and fourth internal buses 35, 37, and 43 to the first ALU 58. The fourth multiplexer 54 inputs g + N + r bits of data from the first input port 39 for inputting a logic value of “0” and the first and third internal buses 35 and 41, respectively. And second and third input ports. The fourth multiplexer 54 supplies the first ALU 58 with any one of three pieces of data on its first to third input ports. The first ALU 58 calculates two data from the third and fourth multiplexers 52 and 54 and supplies the calculated result to the sixth multiplexer 62. The fifth multiplexer 56 also selectively outputs g + N + r bits of data from the first internal bus 35 and g + N + r bits of data from the third internal bus 41. To feed. The barrel shifter 60 scales the logical value of the data from the fifth multiplexer 56 and supplies the scaled data to the sixth multiplexer 62. In order to scale this data, the barrel shifter 60 shifts left or right of the data from the fifth multiplexer 56 by the number of bits corresponding to the scaling amount. In addition, the barrel shift 60 can be connected in parallel with the first ALU 58 to minimize the propagation delay time of the data. Accordingly, the DSP can perform arithmetic operations, scaling and arithmetic operations including the same at high speed. The sixth multiplexer 62 selectively converts the g + N + r bits of the arithmetic data of the first ALU 58 and the scaled data from the barrel shift 60 into a fifth or sixth register 64 or 66. Supplies). Data stored in the fifth or sixth register 64 or 66 is supplied to the third internal bus 41. The fifth and sixth registers 64 and 66 form a first accumulator together with the first ALU 58 as accumulation registers. Both the fifth and sixth registers 64 and 66 have a length of g + N + r bits to temporarily store g + N + r bits of data, and the third internal bus 41 also has g + N + r bits. It consists of two lines.

The DSP also includes a seventh multiplexer 68 connected to the first internal bus 35 and the fourth internal bus 43, and an eighth multiplexer 70 connected to the first and second internal buses 35 and 37. ). The seventh multiplexer 68 inputs g + N + r bits of data from the first input port 45 and the first and fourth internal buses 35 and 43 to input a logic value of “0”, respectively. And second and third input ports. The seventh multiplexer 68 supplies any one of three pieces of data on its first to third input ports to the second ALU 72. The eighth multiplexer 70 has first and second input ports for inputting g + N + r bits of data from the first and second internal buses 35 and 37, respectively. The eighth multiplexer 70 supplies any one of two data from the first and second internal buses 35 and 37 to the second ALU 72. The second ALU 72 calculates two data from the seventh and eighth multiplexers 68 and 70 and supplies the calculated result to the ninth multiplexer 74. The ninth multiplexer 74 selects the g + N + r bits of the calculated data from the second ALU 72 and the scaled data from the barrel shifter 60 as the seventh or eighth register 76 or 78. To feed. The seventh or eighth registers 76 and 78 are supplied with data from the ninth multiplexer 74 to the fourth internal bus 43. The seventh and eighth registers 76 and 78 form a second accumulator together with the second ALU 72 as a cumulative register, and the second accumulator is connected in parallel with the first accumulator so that two or more complex equations are parallel. To be calculated as Both the seventh and eighth registers 76 and 78 have a length of g + N + r bits for temporarily storing g + N + r bits of data. In addition, the seventh and eighth registers 76 and 78 together with the fifth and sixth registers 64 and 66 allow a plurality of complex expressions to be quickly calculated.

Furthermore, the DSP is common to the tenth multiplexer 80 and the tenth multiplexer 80 for selecting two g + N + rbit data from the third and fourth internal buses 41 and 43. Third and fourth bit aligners 82 and 84 and a rounding / saturation processor 82 connected to are further provided. The tenth multiplexer 80 includes g + N + r bits of data from the fifth or sixth registers 64 and 66 via the third internal bus 41 and the fourth through the fourth internal bus 23. Any one of g + N + r bits of data from the seventh or eighth registers 76 and 78 is commonly supplied to the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86. do. The third and fourth bit sorters 82 and 84 extract only N bits from g + N + r data from the tenth multiplexer 80 to extract the extracted N bits of data of the eleventh multiplexer 88. Supply to the first and second input port respectively. In detail, the third bit sorter 82 extracts only N bits of data from the upper g + 1st bit of the g + N + r bits from the tenth multiplexer 80 to extract the N bits of the extracted N bits. Data is supplied to the first input port of the eleventh multiplexer 88. For this purpose, the third bit sorter 82 may have N terminals from the upper g + 1 th terminal among the g + N + r output terminals of the tenth multiplexer 80, that is, the upper g terminals and the lower r. Wiring for connecting the remaining N terminals except for the N terminals to the first input port of the eleventh multiplexer 88 including N terminals is provided. Only by wiring, the third bit sorter 82 converts g + N + r bits of data into N bits of data. The fourth bit sorter 84 extracts only the lower N bits of the data of g + N + r bits from the tenth multiplexer 80, and extracts the extracted N bits of data from the eleventh multiplexer 88. 2 Supply to the input port. For this purpose, the fourth bit sorter 84 may select N N terminals other than the lower N terminals, that is, the upper g + r terminals, among the g + N + r output terminals of the tenth multiplexer 80. And a wiring for connecting to the second input port of the eleventh multiplexer 88 made of terminals. The fourth bit sorter 84, together with the first to third bit sorters 32, 34, and 82, is simply constituted by wiring so that no separate circuit block is required. Accordingly, the first to fourth bit sorters 32, 34, 82, and 84 can simplify the circuit configuration of the DSP and allow both fixed-point and integer operations to be performed at high speed.

The rounding / saturation processor 86 is driven in the rounding processing mode, the saturation processing mode, or the merge mode in accordance with a command from a controller (not shown). In the rounding mode, the rounding / saturation processor 86 selects N bits of data from the r + 1st lower bits in g + N + r bits of data from the 10th multiplexer 80 to generate the 11th multiplexer 88 data. 3 Supply to the input port. Next, in the saturation mode, the rounding / saturation processor 86 processes the upper g + 1 bits of data from the g + N + r bits from the tenth multiplexer 80 according to a logical value. In detail, the rounding / saturation processor 86 performs the processing of the upper g + 1 bits (ie, g guard bits and one sign bit) in the g + N + r bit data from the tenth multiplexer 80. It is determined whether overflow occurs according to whether all logic values are the same. When the logic values of the upper g + 1 bits are all the same, the rounding / saturation processor 86 performs the remaining N bits except for the upper g bit and the lower r bit among the g + N + r bits of data from the tenth multiplexer 80. Is supplied to the third input port of the eleventh multiplexer 88 as a result of the calculation. On the contrary, when the logical values of the upper g + 1 bits are not all the same, the eight rounding / saturation processor 86 determines whether the logical value of the most significant bit of the g guard bits is “0” or “1”. When the logical value of the most significant guard bit is "0", the rounding / saturation processor 86 considers that the data from the tenth multiplexer 80 is positive data in which the overflow has occurred. The N-bit data (ie, "0111 ... 11") of the maximum value having a logic value of "0" is supplied to the third input port of the eleventh multiplexer 88. On the contrary, when the logical value of the most significant guard bit is "1", the rounding / saturation processor 86 considers the data from the tenth multiplexer 80 to be the negative data having overflowed, and thus the most significant bit. Only N-bit data (ie, "1000 ... 00") having a logic value of "1" is supplied to the third input port of the eleventh multiplexer 88. In this way, the saturation processor 86 can correctly process the saturation logic of the data calculated by the ALU 58 or 72 based on the logic values of the guard bits and the sine bits (that is, the logic value at which the overflow occurred). do. Finally, in merge mode, the rounding / saturation processor 86 performs the rounding process on g + N + r bits of data from the tenth multiplexer 80 and then rounds the rounded g + N bits of data. Saturation treatment is performed. The N-bit data rounded and saturated by the rounding / saturation processor 86 is supplied to the eleventh multiplexer 88. In this case, the rounding / saturation processor 86 performs rounding processing for the lower bits first, but does not consume a separate rounding processing time by performing the rounding and saturation processing in one clock period. Accordingly, the rounding / saturation processor 86 provides the advantage of being able to round the fixed-point calculated data without consuming extra time. The eleventh multiplexer 88 transmits any one of three N-bit data from the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86 to the third external bus 47. The third external bus 47 is composed of N lines composed of a write data bus and a write address bus.

FIG. 3 shows a circuit circuit configuration for performing a calculation of two or more complex calculation equations in parallel in the DSP shown in FIG. 3, a first accumulator comprising a first ALU 58, fifth and sixth registers 64 and 66, and a second consisting of a second ALU 72 and seventh and eighth registers 76 and 78. FIG. The accumulators are connected in parallel so that at least two or more complex equations are computed in parallel. Table 1 shows four complex equations and a process in which these four complex equations are computed in parallel. Referring to Table 1, four complex equations such as Equation 1 to Equation 4 are computed in parallel to be completed in a period corresponding to nine clock cycles.

In Table 1, D, T, M, P, X0, X2, X1 and X3 represent data stored in the first to eighth registers 30, 40, 44, 48, 64, 66, 76, and 78, respectively. Indicates. As such, the DSP can compute two complex equations in parallel using a pair of accumulators connected in parallel. Accordingly, the DSP can complete the operation of multiple complex equations in a relatively small number of clock cycles.

As described above, the DSP of the present invention can shorten the lengths of the ALU and the accumulation register by adjusting the number of bits (i.e., word length) of data supplied to the ALU by wiring. In addition, the DSP according to the present invention can eliminate the time required for the rounding process of the data by performing the rounding of the data at the same time during the data saturation processing. Accordingly, the DSP according to the present invention can speed up signal processing.

In addition, in the DSP according to the present invention, since the bit sorters implemented as wirings are disposed at the front and rear ends of the accumulator, fixed-point and integer operations are performed quickly, and the circuit configuration is simplified.

Furthermore, the DSP according to the present invention can minimize the propagation delay time by connecting the barrel shifter to the ALU in parallel and can reduce the number of clocks required for the calculation. Accordingly, the DSP according to the present invention can perform calculations, scaling, and calculations including the same at high speed.

The DSP according to the present invention can compute a plurality of complex equations at high speed by computing two complex equations in parallel using a pair of ALUs connected in parallel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (39)

Calculating data from the first and second input lines using a first calculating means, and converting the data calculated by the first calculating means from one of the first and second input lines. Calculating data using a second calculating means; calculating data calculated by the first calculating means using data from one of the first and second input lines using a third calculating means. Digital signal processing method comprising the step of. The digital signal processing method according to claim 1, wherein the first operation means multiplies data from the first and second input lines. The digital signal processing method according to claim 1 or 2, wherein the first and second multiplication means perform an addition operation. Calculating data from the first and second input lines by using a first calculation means, and connecting the data calculated by the first calculation means to the first and second input lines and a first register file. Calculating data from any one of the first feedback lines, using a second calculation means, and calculating the data calculated by the first calculation means and the first and second input lines and the second register file. And computing data from any one of the connected second feedback lines by using a third calculation means. The digital signal processing method according to claim 4, wherein the first operation means multiplies the data from the first and second input lines. 6. The digital signal processing method according to claim 4 or 5, wherein the first and second calculation means perform an addition operation. Calculating data from the first and second input lines using a first calculating means, connecting the data calculated by the first calculating means to the first and second input lines and a first register file; Calculating data from one of the first feedback line and the second feedback line connected to the second register file using a second calculation means connected to the first register file; And calculating the data calculated by the data and data from any one of the first and second input lines and the first and second feedback lines using a third calculation means connected to a second register file. Digital signal processing method characterized in that. 8. The digital signal processing method according to claim 7, wherein said first operation means multiplies data from said first and second input lines. The digital signal processing method according to claim 7 or 8, wherein the first and second calculation means perform an addition operation. First and second input means for inputting N-bit data, respectively, first calculation means for calculating data from the first and second input means, data from the first calculation means and the first And second computing means for computing data from either of the second input means, and third computing means for calculating data from the first computing means and data from the first and second input means. Digital signal processor, characterized in that. 11. The digital signal processor according to claim 10, wherein said first operation means multiplies data from said first and second input lines. 12. The digital signal processor as claimed in claim 10 or 11, wherein the first and second multiplication means perform an addition operation. First and second input means for inputting N bits of data, first calculation means for calculating data from the first and second input lines, data calculated by the first calculation means, and Second calculation means for calculating data from one of the first and second input lines and the first feedback line, data calculated by the first calculation means, and the first and second input lines and first Third calculating means for calculating data from one of the two feedback lines, a first register file connected to said first feedback line for temporarily storing data from said second calculating means, and said second feedback And a second register file connected to a line for temporarily storing data from said third calculating means. The digital signal processor as claimed in claim 13, wherein the first operation means multiplies data from the first and second input lines. 15. The digital signal processor according to claim 13 or 14, wherein the first and second calculation means perform an addition operation. First and second input lines for inputting data, first calculation means for calculating data from the first and second input lines, data from the first calculation means, and the first and second input lines. Second calculation means for calculating data from one of a second input line and one of a first feedback line and a second feedback line, data from the first calculation means, the first and second input lines, and the first And third computing means for computing data from any one of the second feedback lines, a first register file connected to said first feedback line for temporarily storing data from said second computing means, and And a second register file connected to the two feedback lines for temporarily storing data from the third calculating means. 17. The digital signal processor of claim 16, wherein the first operation means multiplies data from the first and second input lines. 18. The digital signal processor according to claim 16 or 17, wherein the first and second calculation means perform an addition operation. First and second input means for inputting N bits of data, first computing means for calculating data from the first and second input means, and the first and second input means and the first input means. Scaling means for scaling-up data from either of the calculating means, and second operation for calculating data from the first calculating means and data from any one of the first and second input means and the scaling means. Means, and third computing means for computing data from said first computing means and data from any one of said first and second input means and said scaling means. 20. The digital signal processor of claim 19, wherein the first operation means multiplies data from the first and second input lines. 21. The digital signal processor as claimed in claim 19 or 20, wherein the first and second multiplication means perform an addition operation. First and second input means for inputting N-bit data, respectively, first calculation means for calculating data from the first and second input means, data calculated by the first calculation means and the Second calculation means for calculating data from one of the first and second input lines and the first feedback line, data calculated by the first calculation means, and the first and second input lines and second Scaling data from any one of the first calculation means, the first calculation means, the first and second input lines, and the first and second feedback lines, for calculating data from any one of the feedback lines; -Scaling means for up, a first register file connected to said first feedback line for temporarily storing data from said second computing means and said scaling means, and said third operation connected to said second feedback line; Number And a digital signal processor, characterized in that it comprises a second register file for temporarily stored in the data from said scaling means. 23. The digital signal processor of claim 22, wherein the first operation means multiplies data from the first and second input lines. 24. The digital signal processor as claimed in claim 22 or 23, wherein the first and second calculation means perform an addition operation. First and second input lines for inputting data, first calculation means for calculating data from the first and second input lines, data from the first calculation means, and the first and second input lines. Second calculation means for calculating data from one of a second input line and one of a first feedback line and a second feedback line, data from the first calculation means, the first and second input lines, and the first And third computing means for computing data from any one of the second feedback lines, data from any one of the first computing means, the first and second input lines, and the first and second feedback lines. A scaling means for scaling-up a second register, a first register file connected to said first feedback line for temporarily storing data from said second calculating means and said scaling means, and connected to said second feedback line, And a second register file for temporarily storing data from said scaling means and said third calculating means. 26. The digital signal processor of claim 25, wherein the first operation means multiplies data from the first and second input lines. 27. The digital signal processor as claimed in claim 25 or 26, wherein the first and second calculation means perform an addition operation. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N bit data to the left by r bits, first computing means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. And bit adjusting means for shifting the adjusted data to the left by r bits, second computing means for calculating data from the bit adjusting means and data from either one of the first and second fixed shifters; Third calculation means for calculating data from the first calculation means and data from one of the first and second fixed shifters, and either one of the first and second calculation means. And extracting means for extracting only the upper N bits from the data from the digital signal processor. First and second input means for inputting N-bit data, respectively, a first fixed shifter for shifting the N-bit data from the first input means to the right by r bits, and from the second input means. A second fixed shifter shifting the N-bit data to the right by r bits, first calculating means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, second computing means for calculating data from the bit adjusting means and data from either one of the first and second fixed shifters; Third calculation means for calculating data from the first calculation means and data from one of the first and second fixed shifters, and either one of the first and second calculation means. And extracting means for extracting only the lower N bits from the data from the digital signal processor. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N-bit data to the left by r bits, a third fixed shifter shifting the N-bit data to the right by the n bits from the first input means, and the second input shifter from the second input means. A fourth fixed shifter shifting the N bit data to the right by r bits, first selecting means for selecting data from any one of the first and third fixed shifters, and among the second and fourth fixed shifters. Second selection means for selecting data from either one, first calculation means for multiplying data from the first and second input means, and data from the first calculation means. First bit adjusting means for adjusting to N bits and shifting the adjusted data to the left by r bits, and second for adjusting the data from the first computing means to N bits and shifting the adjusted data to the right by r bits. Bit adjusting means, third selecting means for selecting data from one of the first and second bit adjusting means, and data from the third selecting means and from one of the first and second selecting means. Second calculation means for calculating data of the second data, second calculation means for calculating data from the third selecting means and data from any one of the first and second selection means, and the first and second operations. First extracting means for extracting only the upper N bits from data from either of the means, and extracting only the lower N bits from the data from either of the first and second computing means. And second selecting means and fourth selecting means for selecting data from either one of said first and second extracting means. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N bit data to the left by r bits, first computing means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the left by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Computing means, third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line; A first register file connected to a first return line for temporarily storing data from said second calculating means and a second register file connected to said second return line for temporarily storing data from said third calculating means And extracting means for extracting only the upper N bits from data from either of the first and second register files. First and second input means for inputting N-bit data, respectively, a first fixed shifter for shifting the N-bit data from the first input means to the right by r bits, and from the second input means. A second fixed shifter shifting the N-bit data to the right by r bits, first calculating means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Computing means, third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line; A first register file connected to a first return line for temporarily storing data from said second calculating means and a second register file connected to said second return line for temporarily storing data from said third calculating means And extracting means for extracting only the lower N bits from data from either of the first and second register files. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N-bit data to the left by r bits, a third fixed shifter shifting the N-bit data to the right by the n bits from the first input means, and the second input shifter from the second input means. A fourth fixed shifter shifting the N bit data to the right by r bits, first selecting means for selecting data from any one of the first and third fixed shifters, and among the second and fourth fixed shifters. Second selection means for selecting data from either one, first calculation means for multiplying data from the first and second input means, and data from the first calculation means. First bit adjusting means for adjusting to N bits and shifting the adjusted data to the left by r bits, and second for adjusting the data from the first computing means to N bits and shifting the adjusted data to the right by r bits. Bit adjusting means, third selecting means for selecting data from one of the first and second bit adjusting means, data from the third selecting means, the first and second selecting means, and first feedback Second operation means for calculating data from one of the lines, second operation means for calculating data from the third selecting means and data from any one of the first and second selecting means and the second feedback line. Means, a first register file connected to said first return line for temporarily storing data from said second calculation means, and a third calculated water connected to said second return line. A second register file for temporarily storing data from the first register, first extraction means for extracting only the upper N bits from data from either of the first and second register files, and the first and second register files And second extraction means for extracting only the lower N bits from data from either one, and fourth selection means for selecting data from either one of the first and second extraction means. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N bit data to the left by r bits, first computing means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. And bit adjusting means for shifting the adjusted data to the left by r bits, data from the bit adjusting means, and data from any one of the first and second fixed shifters and the first and second feedback lines. A third operation means for computing a second operation means, data from the first operation means, and data from one of the first and second fixed shifters and the first and second feedback lines. And a first register file connected to said first feedback line to temporarily store data from said second computing means, and temporarily connected to said second feedback line to temporarily store data from said third computing means. And extracting means for extracting only the upper N bits from data from either the second register file or the first and second register files. First and second input means for inputting N-bit data, respectively, a first fixed shifter for shifting the N-bit data from the first input means to the right by r bits, and from the second input means. A second fixed shifter shifting the N-bit data to the right by r bits, first calculating means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Computing means, third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line; A first register file connected to a first return line for temporarily storing data from said second calculating means and a second register file connected to said second return line for temporarily storing data from said third calculating means And extracting means for extracting only the lower N bits from data from either of the first and second register files. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N-bit data to the left by r bits, a third fixed shifter shifting the N-bit data to the right by the n bits from the first input means, and the second input shifter from the second input means. A fourth fixed shifter shifting the N bit data to the right by r bits, first selecting means for selecting data from any one of the first and third fixed shifters, and among the second and fourth fixed shifters. Second selection means for selecting data from either one, first calculation means for multiplying data from the first and second input means, and data from the first calculation means. First bit adjusting means for adjusting to N bits and shifting the adjusted data to the left by r bits, and second for adjusting the data from the first computing means to N bits and shifting the adjusted data to the right by r bits. Bit adjusting means, third selecting means for selecting data from one of said first and second bit adjusting means, data from said third selecting means, said first and second selecting means, and first and Second calculation means for calculating data from either of the second feedback lines, data from the third selection means, and data from any one of the first and second selection means and the first and second feedback lines. A second operation means for computing a, a first register file connected to said first feedback line to temporarily store data from said second operation means, and connected to said second feedback line. A second register file for temporarily storing data from the third computing means, first extraction means for extracting only the upper N bits from data from either one of the first and second register files, and the first and the first and second register files. And second extraction means for extracting only the lower N bits from data from either one of the two register files, and fourth selection means for selecting data from either one of the first and second extraction means. Digital Signal Processor. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N bit data to the left by r bits, first computing means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the left by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Computing means, third computing means for computing data from the bit adjusting means and data from one of the first and second fixed shifters and the second feedback line; A first register file connected to a first return line for temporarily storing data from said second computing means, and a second register connected to said second return line for temporarily storing data from said third computing means Scaling means for scaling up data from a file, said first calculation means, said first and second input lines and said first and second feedback lines, and said first feedback line connected to said first feedback line. A first register file for temporarily storing data from the second computing means and the scaling means, and a second register connected to the second feedback line for temporarily storing the data from the third computing means and the scaling means. And extracting means for extracting only the upper N bits from the data from either one of the first and second register files. A digital signal processor that. First and second input means for inputting N-bit data, respectively, a first fixed shifter for shifting the N-bit data from the first input means to the right by r bits, and from the second input means. A second fixed shifter shifting the N-bit data to the right by r bits, first calculating means for multiplying the data from the first and second input means, and adjusting the data from the first computing means to N bits. Bit adjusting means for shifting the adjusted data to the right by r bits, and a second operation for calculating data from the bit adjusting means and data from any one of the first and second fixed shifters and the first feedback line. Computing means, third computing means for computing data from the first computing means and data from one of the first and second fixed shifters and the second feedback line; Scaling means, scaling means for scaling up data from any one of the first and second fixed shifters and the first and second feedback lines, connected to the first feedback line, and the second operation means and the scaling. A first register file for temporarily storing data from the means, a second register file connected to the second feedback line for temporarily storing data from the third computing means and the scaling means, and the first and second register files. And extracting means for extracting only the lower N bits from data from either one of the second register files. First and second input means for inputting N-bit data respectively, a first fixed shifter shifting left by n bits to the N-bit data from the first input means, and from the second input means. A second fixed shifter shifting the N-bit data to the left by r bits, a third fixed shifter shifting the N-bit data to the right by the n bits from the first input means, and the second input shifter from the second input means. A fourth fixed shifter shifting the N bit data to the right by r bits, first selecting means for selecting data from any one of the first and third fixed shifters, and among the second and fourth fixed shifters. Second selection means for selecting data from either one, first calculation means for multiplying data from the first and second input means, and data from the first calculation means. First bit adjusting means for adjusting to N bits and shifting the adjusted data to the left by r bits, and second for adjusting the data from the first computing means to N bits and shifting the adjusted data to the right by r bits. Bit adjusting means, third selecting means for selecting data from one of said first and second bit adjusting means, data from said third selecting means, said first and second selecting means, and first and Second calculation means for calculating data from either of the second feedback lines, data from the third selection means, and data from any one of the first and second selection means and the first and second feedback lines. Third computing means for computing a; and scaling means for scaling up data from any one of the first to third selecting means and the first and second feedback lines, and to the first feedback line. A first register file for temporarily storing data from said second computing means and said scaling means, and temporarily connected to said second feedback line for temporarily storing data from said third computing means and said scaling means. First extraction means for extracting only the upper N bits from data from either the second register file, the first and second register files, and the lower N from the data from any one of the first and second register files. And second extracting means for extracting only bits, and fourth selecting means for selecting data from either one of said first and second extracting means.

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