KR100251546B1 - Digital signal processor - Google Patents

Abstract

PURPOSE: A digital signal processor is provided to reduce time required for rounding-processing data by performing data rounding simultaneously with processing data saturation, thereby processing signals at high speed, and to promptly perform fixed-point and integer operations by arranging bit aligners in front and rear ends of an accumulator with simplifying the construction of a circuit. CONSTITUTION: Input elements(30,40,44,48,64,66,76,78) input N bit data. Operation elements(58,72) operate data from the input element and data from a return loop. A memory(30,40) stores data from the operation elements(58,72) temporarily and is connected with the return loop. A scaling element scales data from the input element (30,40,44,48,64,66,76,78). A selecting element selectively transmits data from the scaling element and data from the operation elements(58,72) to the memory.

Description

Digital Signal Processor

The present invention relates to a digital signal processor (hereinafter referred to as "DSP") for processing various digital signals by software.

DSP is a type of central processing unit (CPU) with arithmetic functions, originally led by the US electronics company "Texas Instruments" (TI). This DSP has recently been applied to the processing of video and audio signals, and its use has increased rapidly, especially among the various processing methods of audio signals, which has been set internationally by MPEG (Moving Picture Expert Group). DSPs that implement the audio compression algorithm "Musicam" and "Dolby" digital audio compression and restoration algorithm "AC-3" are rapidly emerging. Companies, especially in the West, are spurring the development of their own DSPs to increase their profits.

The DSP for audio signal processing has a longer Word Length for internal calculations than the fixed-point DSP of TI, which has been commonly used up to now. For example, the "TI" TMS320C5x series DSPs have a 16-bit data word length and a 32-bit Arithmetic Logic Unit ("ALU"), while the MEPG "music" The latest DSPs developed to implement Cam and Dolby's "AC-3" have nearly 20-bit data word length and 48-bit ALU. More specifically, "YSS243" from "Yamaha" and "DSP5600x" from "Motorola". DSPs such as "CS2923" from "Crystal Semiconductor" and MED25201 from "Medianix Semiconducer" both decode audio signals of "Dolby" "AC-3". It has a 24-bit data word length and a 56-bit ALU. Also, DSPs such as "ZR38000" from "Zoran" and "MB86342" from "Fujitsu" are all 20-bit data word lengths for decoding audio signals of "AC-3" from "Dolby". And 48 bit ALU.

The DSPs configured as described above operate two data having a length of N bits as shown in FIG. The first and second data 10, 12 are read from the memory and multiplied by a multiplier to generate third data that is the result of the multiplication. The first and second data 10, 12 each have a length of N bits and are composed of an integer part and a fractional part. The third data 14, which is a multiplication result of the multiplier, may have a maximum length of 2N bits, and is thus temporarily stored in a 2N bit multiplication register. Subsequently, the third data 14 is shifted by the barrel shifter by the number of bits of the integer part of the first and second data 10, 12, for example, R bits, and 2N as the result of the shift. The fourth data 16 of the bit is calculated. The fourth data 16 is logically operated by the ALU to generate the fifth data 18. Overflow may occur in the fifth data 18 that is an operation result of the ALU. In order to deal with this overflow, the fifth data 18 is saturated in a DSP such as "TMS320C5x" of "Tl". In detail, when the fifth data 18 calculated by the ALU has a bit length that is difficult to be stored in the 2N bit accumulation register, that is, when an overflow occurs in the fifth data 18, the " TMS32 0C5x " The DSP saturates the fifth data 18 and stores the saturated fifth data 18 in the accumulation register to alleviate errors due to overflow. In contrast, DSPs such as "DSP5600x" from Motorola, Inc. add 8 bits to the accumulation register for overflow protection, as in FIG. In this case, both the ALU and the accumulation register have a length of "8 + 2N" bits. Applying this overflow protection bit to the "AC-3" dedicated DSPs listed above, DSPs with 24-bit data word lengths have 56-bit accumulators and 20-bit data word lengths since the data is N = 24 bits. Since DSPs have N = 20 bits, each of them has a 48-bit accumulator. The fifth data 18 to which the overflow protection bits are added is converted into sixth data 20 having the same bit length as the first and second data 10 and 12 stored in the memory by being saturated.

In order to perform the above-described series of operations, most DSPs had to have ALUs and cumulative registers having a large word length of more than 48 bits. These ALUs and accumulators with more than 48 bits of cone length increase the die size on the DSP chip and increase the amount of propagation delay in the ALU. Therefore, the ALU and accumulator having a large word length not only increases the manufacturing cost of the DSP chip but also acts as a factor of decreasing the operation speed of the DSP.

Most DSPs support rounding operations before saturating the data. For example, the "Motorola" DSP converts the data of "8 + 2N" bits stored in the accumulation register into "8 + N" bits by the command "rnd". This rounded data is finally saturated with "N" bits of data and then stored in memory. For these rounding operations, most DSPs consume an additional instruction or clock period.

This additional consumption of instructions or clock cycles results in a lot of additional clock cycles when the rounding operation is applied to the code segment to which looping or block repeating is applied. The amount of computation is greatly increased.

In addition, DSPs, such as "TMS320C5x" from "TI", use a pre-scaling shifter located in front of the ALU to shift the binary data to be calculated in the ALU to the left from 0 to 16 bits. At this time, the shift operation from the "0" th bit to the "15" th bit is normally used to scale binary data, but the shift operation up to the "16" th bit is a fixed point, not an integer operation. ) Is used when the operation is performed. This is because in the case of fixed-point arithmetic, 16-bit data read from memory must be aligned with the upper bits of the 32-bit accumulation register. Shift operations from the "0" th bit to the "15" th bit for scaling data may or may not be usefully used depending on a given algorithm, in particular, a coding method. When performing algorithms implemented in code where prescaling is not useful, the scaling shifter increases the die age and increases propagation delay of the DSP chip without much help. In one example, the pre-scaling shifter included in the "Motorola" DSP is designed to shift data one bit down to the left or to the right. Instead, Motorola's DSPs offer different multiply instructions for floating-point and integer operations, absorbing the "TI" 's "TMS320C5x" shifting data left by 16 bits.

In a nutshell, it is important in DSP how fast each instruction can be executed. For fast execution of instructions, the period of instructions applied to the DSP should be shortened and as many instructions as possible should be processed in parallel. Shortening the former instruction cycle is a hardware-, circuit-related problem that shortens the circuit path by eliminating unnecessary blocks (e.g., the pre-scaling shifters already mentioned) possible in the DSP. The parallelism of the latter instruction comes from the fact that DSPs are used for video / audio decoding, which requires a lot of computation, and the sequential instruction execution method of the past does not have the necessary computational capability. Therefore, DSPs are equipped with special instructions capable of parallel processing. For example, "DSP21020", a DSP of "Analog Device", has special instructions for performing multiple complex expressions in a few plug cycles, such as a butterfly operation for FFT operations. For this purpose, the "ADSP2102 0" has a register file consisting of at least 12 registers associated with the operation. In addition, Zor38000 also performs many complex equations, such as butterfly for FFT, in just a few clock cycles. To this end, the ZR38000 has a register file consisting of eight registers and a structure that performs multiplication and addition and subtraction of the result in one clock cycle.

Accordingly, an object of the present invention is to provide a DSP capable of performing a computation including a scale of data at a high speed.

Another object of the present invention is to provide a DSP capable of efficiently performing integer operations and fixed-point operations.

1 is a diagram schematically showing a signal processing procedure of a conventional DSP.

2 is a block diagram of a DSP according to an embodiment of the present invention.

FIG. 3 is a diagram showing a portion of the DSP shown in FIG. 2 for performing an operation including scaling.

* Explanation of symbols for main parts of the drawings

30,40,44,48,64,66,76,78: first through eighth registers

32, 34, 82, 84: first to fourth bit sorter

38: Guard bit addition

36,42,52,54,56,62,68,70,74,80,88: first to eleventh multiplexers

46: multiplier 38: beat controller

58, 72: first and second ALU 60: barrel shifter

86: rounding / saturation processor

In order to achieve the above object, the DSP according to the present invention temporarily stores input means for inputting N bits of data, computing means for data from the input means and data from the feedback loop, and data from the computing means. And a memory coupled to the feedback loop, scaling means for scaling data from the input means, and selecting means for selectively transferring data from the scaling means and data from the computing means to the memory.

The DSP according to the present invention calculates input means for inputting N bits of data, a fixed shifter shifting left by n bits to the N bit data from the input means, data from the fixed shifter and data from the feedback loop. Means for temporarily storing data from the computing means and associated with a feedback loop, scaling means for scaling the data from the fixed shifter, and selectively transferring data from the scaling means and data from the computing means to the memory. And selecting means for extracting only the upper N bits from the data from the memory.

The DSP according to the present invention calculates input means for inputting N bits of data, a fixed shifter for shifting right by n bits from the N bit data from the input means, data from the fixed shifter and data from the feedback loop. Means for temporarily storing data from the computing means and associated with a feedback loop, scaling means for scaling the data from the fixed shifter, and selectively transferring data from the scaling means and data from the computing means to the memory. Selection means and extraction means for extracting the lower N bits from the data from the memory.

The DSP according to the present invention has an input means for inputting N bits of data, a first fixed shifter for shifting left by n bits to N bits of data from the input means, and r bits for N bits of data from the input means. A second fixed shifter shifting to the right, first selecting means for selecting data from either one of the first and second fixed shifters, data from the first selecting means and data from the feedback loop; Memory for temporarily storing data from the computing means and connected to the feedback loop, scaling means for scaling the data from the first selection means, and selectively transferring data from the scaling means and data from the computing means to the memory. Second selection means, first extraction means for extracting only the upper N bits from data from the memory, and arithmetic means; And a second extracting means for extracting only the low order N bits of data in and from the first and the third selection means for sintaek data from any of the second extracting means to one side.

Other objects and advantages of the present invention will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

Referring to FIG. 2, a first register 30 for inputting N bits of data from the first external bus 31 and first and second bit aligners connected in parallel to the first register 30 is shown. A DSP in accordance with an embodiment of the present invention having (32, 34) is shown. The first external bus 31 is composed of N data lines commonly connected to a working memory (not shown) and is used as an N-bit first read-only data bus. The first register 30 temporarily stores N bits of data from the memory via the first external bus 31. The first and second bit aligners 32 and 34 serve to extend the N bits from the data N bits to the N + r bits by shifting the N bits of data from the first register 30. In detail, the first bit sorter 32 shifts N bits of data by 1 bit to the left for fixed-point arithmetic. To this end, the first bit sorter 32 includes N-bit output lines of the first register 30 of the upper N input terminals of the first input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The second bit sorter 34 shifts N bits of data to the right by r bits for integer arithmetic. At this time, the upper r bits may be filled as sine (positive or negative) bits or filled with values of "0" according to the DSP's Sign-Extension Mode. To this end, the second bit sorter 34 has N-bit output lines of the N-bit output line of the first multiplexer 36 having N + r terminals of the N-bit output lines of the first register 30. Wiring to be connected to each other. The upper r bits are filled with the sign bit or "0" as mentioned above. The first multiplexer 36 receives N + r bits of data on the first input port or N + r bits of data on the second input port according to the type of operation, that is, fixed-point / integer operation. ) Is supplied to the adder 38. This first guard bit adder 38 adds g bits of guard bits to the N + r bits of data from the first multiplexer 36. The g bits of the g bits are all set to "0" or they extend the sign of the data. In detail, all g-bit guard bits have the same logic value as the sign bit of data when the sign-extension mode is set, and all logic values of "0" when the sign-extension mode is reset. . The sign-extension mode is set or reset by a particular instruction. In order to add these g-bit guard bits to the N + r bit data, the first guard bit adder 38 connects the output port of the first multiplexer 36 consisting of N + r terminals to the first internal bus. The wirings are connected to the lower N + r lines among the g + N + r lines included in (35).

The DSP adds a second register 40 and a multiplier 46 connected in series to the first external bus 31 and a second multiplexer 42 connected to the first and second external buses 31 and 33. It is provided with. Like the first register 30, the second register 40 temporarily stores N-bit data from the memory input via the first external bus 31. The second external bus 33 is composed of N lines commonly connected to a program memory and a CPU (not shown) and is used as a second read-only data bus. The second multiplexer 42 includes N bit data from the first external bus 31 supplied to its first input port and N bit data from the second external bus 33 supplied to its second input port. One data is supplied to the third register 44. The third register 44 temporarily stores the N bit data from the second multiplexer 42.

Multiplier 46 multiplies two data stored in second and third registers 40 and 44. The result multiplied by this multiplier 46 may have 2N bits. Accordingly, the fourth register 48 which temporarily stores data from the multiplier 46 has a length of 2N bits. The wiring controller 50 connected between the fourth register 48 and the second internal bus 37 converts 2N bits of data stored in the fourth register 48 into N + r bits of data smaller than 2N. A g-bit guard bit is added to the converted N + r-bit data.

The DSP includes third to fifth multiplexers 52 to 56 that are commonly connected to the first internal bus 35. The third multiplexer 52 has first to third input ports for inputting g + N + r bits of data from the first, second and fourth internal buses 35, 37 and 43, respectively. The third multiplexer 52 supplies any one of three data from the first, second and fourth internal buses 35, 37 and 43 to the first ALU 58. The fourth multiplexer 54 inputs g + N + r bits of data from the first input port 39 for inputting a logic value of “0” and the first and third internal buses 35 and 41, respectively. And second and third input ports. The fourth multiplexer 54 supplies the first ALU 58 with any one of three pieces of data on its first to third input ports.

The first ALU 58 computes two data from the third and fourth multiplexers 52 and 54 and supplies the calculated result to the sixth multiplexer 62. The fifth multiplexer 56 also selectively outputs g + N + r bits of data from the first internal bus 35 and g + N + r bits of data from the third internal bus 41. To feed. The barrel shifter 60 scales the logical value of the data from the fifth multiplexer 56 and supplies the scaled data to the sixth multiplexer 62. In order to scale this data, the barrel shifter 60 shifts left or right of the data from the fifth multiplexer 56 by the number of bits corresponding to the scaling amount. In addition, since the barrel shifter 60 is connected in parallel with the first ALU 58, the propagation delay time of data can be minimized. Accordingly, the DSP can perform arithmetic operations, scaling and arithmetic operations including the same at high speed. The sixth multiplexer 62 selectively converts the g + N + r bits of the arithmetic data of the first ALU 58 and the scaled data from the barrel shifter 60 into a fifth or sixth register 64. Or 66). Data stored in the fifth or sixth register 64 or 66 is supplied to the third internal bus 41. The fifth and sixth registers 64 and 66 constitute a first accumulator together with the first ALU 58 as accumulation registers. Both the fifth and sixth registers 64 and 66 have a length of g + N + r bits to temporarily store g + N + r bits of data, and the third internal bus 41 also uses g + N +. It consists of r lines.

In addition, the DSP includes a seventh multiplexer 68 connected to the first internal bus 35 and the fourth internal bus 43, and an eighth multiplexer 70 connected to the first and second internal buses 35 and 37. ). The seventh multiplexer 68 inputs g + N + r bits of data from the first input port 45 and the first and fourth internal buses 35 and 43 to input a logic value of “0”, respectively. And second and third input ports. The seventh multiplexer 68 supplies any one of three pieces of data on its first to third input ports to the second ALU 72. The eighth multiplexer 70 has first and second input ports for inputting g + N + r bits of data from the first and second internal buses 35 and 37, respectively. The eighth multiplexer 70 supplies any one of two data from the first and second internal buses 35 and 37 to the second ALU 72. The second ALU 72 computes two data from the seventh and eighth multiplexers 68 and 70 and supplies the calculated result to the ninth multiplexer 74. The ninth multiplexer 74 selectively stores the calculated data of the g + N + r bits from the second ALU 72 and the scaled data from the barrel shifter 60 to the seventh or eighth register 76 or 78. Supply. The seventh or eighth registers 76 and 78 are supplied with data from the ninth multiplexer 74 to the fourth internal bus 43. The seventh or eighth registers 76 and 78 form a second accumulator together with the second ALU 72 as a cumulative register, and the second accumulator is connected in parallel with the first accumulator so that two or more complex equations are parallel. To be calculated as Both the seventh and eighth registers 76 and 78 have a length of g + N + r bits to temporarily store g + N + r bits of data. In addition, the seventh and eighth registers 76, 78, together with the fifth and sixth registers 64,66, allow multiple complex equations to be computed quickly.

Furthermore, the DSP is common to the tenth multiplexer 80 and the tenth multiplexer 80 for selecting two g + N + r bit data from the third and fourth internal buses 41 and 43. And a third and fourth bit sorter 82,84 and a rounding / saturation processor 82 connected to each other. The tenth multiplexer 80 includes g + N + r bits of data from the fifth or sixth registers 64 and 66 via the third internal bus 41 and the fourth through the internal bus 23. Either g + N + r bits of data from the seventh or eighth registers 76,78 are commonly supplied to the third and fourth bit sorters 82,84 and the rounding / saturation processor 86. do. The third and fourth bit sorters 82 and 84 extract only N bits from g + N + r bits of data from the tenth multiplexer 80 to extract the extracted N bits of data from the eleventh multiplexer 88. Gig supply to the first and second input ports. In detail, the third bit sorter 82 extracts only N bits of data from the upper g + 1 th bit of the g + N + r bits from the tenth multiplexer 80 to extract the N bits of the extracted N bits. Data is supplied to the first input port of the eleventh multiplexer 88. For this purpose, the third bit sorter 82 may have N terminals from the upper g + 1 th terminal among the g + N + r output terminals of the tenth multiplexer 80, that is, the upper g terminals and the lower r. Wiring for connecting the remaining N terminals except for the N terminals to the first input port of the eleventh multiplexer 88 including N terminals is provided. Only by wiring, the third bit sorter 82 converts data of g + N + r bits into N bits of data. The fourth bit sorter 84 extracts only the lower N bits of the data of the g + N + r bits from the tenth multiplexer 80, and extracts the extracted N bits of data from the eleventh multiplexer 88. 2 Supply to the input port. For this purpose, the fourth bit sorter 84 N-N other than the lower N terminals of the g + N + r output terminals of the tenth multiplexer 80, that is, the upper g + 1 dyn N terminals. And a wiring for connecting to the second input port of the eleventh multiplexer 88 composed of four terminals. The fourth bit sorter 84, together with the first to third bit sorters 32, 34 and 82, is simply configured by wiring so that no separate circuit block is required. Accordingly, the first to fourth bit aligners 32, 34, 82, and 84 can simplify the circuit configuration of the DSP and allow both fixed-point and integer operations to be performed at high speed.

The rounding / saturation processor 86 is driven in the rounding processing mode, the saturation processing mode, or the merge mode in accordance with a command from a controller (not shown). In the rounding mode, the rounding / saturation processor 86 selects N bits of data from the r + 1st lower bits in the g + N + r bits of data from the 10th multiplexer 80 to select the 11th multiplexer. Supply to the third input port of (88). Next, in the saturation mode, the rounding / saturation processor 86 processes the data according to the logical value of the upper g + 1 bits in the g + N + r bits of the data from the tenth multiplexer 80. In detail, the rounding / saturation processor 86 performs the processing of the upper g + 1 bits (ie, g guard bits and one sign bit) in the g + N + r bits of data from the tenth multiplexer 80. It is determined whether overflow occurs according to whether all logic values are the same.

When the logic values of the upper g + 1 bits are all the same, the rounding / saturation processor 86 performs the remaining N bits except for the upper g bit and the lower r bit among the g + N + r bits of data from the tenth multiplexer 80. Is supplied to the third input port of the eleventh multiplexer 88 as a result of the calculation. In contrast, when the logic values of the upper g + 1 bits are not all the same, the rounding / saturation processor 86 determines whether the logical value of the most significant bit of the g guard bits is “0” or “1”. When the logical value of the most significant guard bit is "0", the rounding / saturation processor 86 considers that the data from the tenth multiplexer 80 is positive data in which the overflow has occurred. The N-bit data (ie, "0111 ... 11") of the maximum value having a logic value of "0" is supplied to the third input port of the eleventh multiplexer 88. On the contrary, when the logical value of the most significant guard bit is "1", the rounding / saturation processor 86 considers the data from the tenth multiplexer 80 to be the negative data having overflowed, and thus the most significant bit. Only N-bit data (ie, "1000 ... 00") having a logic value of "1" is supplied to the third input port of the eleventh multiplexer 88. In this way, the saturation processor 86 can correctly process the saturation logic of the data calculated by the ALU 58 or 72 based on the logic values of the guard bits and the sine bits (that is, the logic value at which the overflow occurred). do. Finally, in merge mode, rounding / saturation processor 86 performs the rounding process on g + N + r bits of data from tenth multiplexer 80 and then rounds the g + N bits of data. The saturation treatment is performed on. The N-bit data rounded and saturated by the rounding / saturation processor 86 is supplied to the eleventh multiplexer 88. In this case, the rounding / saturation processor 86 performs rounding processing for the lower bits first, but does not consume a separate rounding processing time by performing the rounding and saturation processing in one clock period. Accordingly, the rounding / saturation processor 86 provides an advantage of rounding the data that has been fixed point operation without consuming extra time. The eleventh multiplexer 88 transmits one of the three N-bit data from the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86 to the third external bus 47. The third external bus 47 is composed of N lines composed of a write data bus and a write address bus.

FIG. 3 shows a circuit configuration for performing arithmetic operations including scaling among the DSPs shown in FIG. In FIG. 3, the barrel shifter 60 is connected in parallel with the first ALU 58 to shorten the length of the data path from the first external bus 31 to the third external bus 47. This means that the number of clock circuit elements connected between the first external bus 31 and the third external bus 47 is three (i.e., two registers and one barrel shifter and ALU). Two registers and one ALU). In detail, the data is transferred from the first external bus 31 to the first register 30, the third multiplexer 52, the first ALU 58, the sixth multiplexer 62, the fifth register 64 and the eleventh. Proceed to the third external bus 47 via the multiplexer 88 or from the first external bus 31, the first register 30, the fifth multiplexer 56, the barrel shifter 60, and the sixth multiplexer. Proceed to the third external bus 47 via 62, the fifth register 64 and the eleventh multiplexer 88, or from the first external bus 31, the first register 30, the fifth multiplexer. (56), the barrel shifter (60), the seventh register (76) and the eleventh multiplexer (88) proceed to the third external bus (47). Since the barrel shifter 60 is connected in parallel with the first ALU 58, the DSP can minimize the propagation delay time and can also reduce the number of clocks required for the calculation. Accordingly, the DSP can perform normal operations, scaling, and calculations including the same at high speed.

As described above, the DSP of the present invention can shorten the lengths of the ALU and the accumulation register by adjusting the number of bits (i.e., word length) of data supplied to the ALU by wiring. In addition, the DSP according to the present invention can eliminate the time required for the rounding process of the data by performing the rounding of the data at the same time during the data saturation processing. Accordingly, the DSP according to the present invention can speed up signal processing.

In addition, in the DSP according to the present invention, since the bit sorters implemented as wirings are disposed at the front and rear ends of the accumulator, fixed-point and integer operations are performed quickly, and the circuit configuration is simplified.

Furthermore, the DSP according to the present invention can minimize the propagation delay time by connecting the barrel shifter to the ALU in parallel and can reduce the number of clocks required for the calculation. Accordingly, the DSP according to the present invention can perform calculations, scaling, and calculations including the same at high speed.

The DSP according to the present invention can compute a plurality of complex equations at high speed by computing two complex equations in parallel using a pair of ALUs connected in parallel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (18)

Input means for inputting N bits of data, computing means for calculating data from the input means and data from the feedback loop, a memory for temporarily storing data from the computing means and connected to the feedback loop, the input And scaling means for scaling data from the means, and selecting means for selectively transferring data from said scaling means and data from said computing means to said memory. 2. The digital signal processor as claimed in claim 1, further comprising second selecting means for selectively supplying data from the input means and data from the feedback loop to the scaling means. 2. The digital signal processor according to claim 1, further comprising second selecting means for selectively supplying data from said input means and data from said feedback loop to said calculating means. Input means for inputting N bits of data, a fixed shifter shifting left by n bits to the N bit data from the input means, computing means for calculating data from the fixed shifter and data from the feedback loop; A memory coupled to the feedback loop for temporarily storing data from the computing means, scaling means for scaling data from the fixed shifter, data from the scaling means and data from the computing means, selectively And extracting means for extracting only the upper N bits from the data from the memory. 5. The digital signal processor according to claim 4, further comprising a second selection means for selectively supplying data from said fixed shifter and data from said feedback loop to said scaling means. 5. The digital signal processor according to claim 4, further comprising second selecting means for selectively supplying data from said fixed shifter and data from said feedback loop to said calculating means. The digital signal processor according to any one of claims 4 to 6, wherein the fixed shifter wiring is implemented. The digital signal processor according to any one of claims 4 to 6, wherein said extracting means is implemented by wiring. Input means for inputting N bits of data, a fixed shifter which shifts right by r bits to the N bit data from the input means, computing means for calculating data from the fixed shifter and data from the feedback loop; A memory coupled to the feedback loop for temporarily storing data from the computing means, scaling means for scaling data from the fixed shifter, data from the scaling means and data from the computing means, selectively And extracting means for extracting the lower N bits from the data from the memory. 10. The digital signal processor according to claim 9, further comprising second selecting means for selectively supplying data from said fixed shifter and data from said feedback loop to said scaling means. 10. The digital signal processor according to claim 9, further comprising second selecting means for selectively supplying data from said fixed shifter and data from said feedback loop to said calculating means. 12. The digital signal processor according to any one of claims 9 to 11, wherein the fixed shifter is implemented by wiring. The digital signal processor according to any one of claims 9 to 11, wherein said extracting means is implemented by wiring. Input means for inputting N bits of data, a first fixed shifter shifting left by n bits to the N bits of data from the input means, and r bits to the N bits of data from the input means to the right A second fixed shifter for shifting, first selecting means for selecting data from any one of said first and second fixed shifters, computing means for calculating data from said first selecting means and data from a feedback loop, Selectively storing data from the computing means and storing a memory connected to the feedback loop, scaling means for scaling data from the first selection means, data from the scaling means and data from the computing means. Second selecting means for transferring to said memory and an upper N in data from said memory; First extracting means for extracting only bits, second extracting means for extracting only the lower N bits from said data from said computing means, and third selection for selecting data from either of said first and second extracting means; And a means for providing a digital signal processor. 15. The digital signal processor according to claim 14, further comprising: fourth selecting means for selectively supplying data from the first suntec means and data from the feedback loop to the scaling means. 15. The digital signal processor according to claim 14, further comprising: fourth selecting means for selectively supplying data from said first selecting means and data from said feedback loop to said calculating means. 17. The digital signal processor according to any one of claims 14 to 16, wherein said first and second fixed shifters are implemented by wiring. The digital signal processor according to any one of claims 15 to 16, wherein the first and second extraction means are implemented by wiring.

Images