KR100297544B1 - Digital signal processor - Google Patents

Abstract

PURPOSE: A digital signal processor is provided to rapidly process signals by simultaneously performing a rounding of data in case that the saturation process of the data are performed, and by removing the time for processing the rounding of the data. CONSTITUTION: The first register(30) inputs N-bit data from the first external bus(31). The first and the second bit alignment device(32, 34) shift the N-bit data inputted from the first register from N-bit to N+r bit(30). The first multiplexer(36) provides N+r bit data on the first input port or the second input port to the first guard bit adder(38). The second register(40) temporarily stores N-bit data inputted via the first external bus(31). The second multiplexer(42) provides N-bit data from the first external bus(31) provided to the first input port(39) to the third register(44). The third register(44) temporarily stores N-bit data from the second multiplexer(42). A multiplier(46) multiplies data stored in the second and the third register(40, 44). A wiring adjuster(50) connected between the fourth register(48) and the second external bus(37) converts 2N-bit data stored in the fourth register(48) into N+r bit data. The third multiplexer(52) or the fifth multiplexer(56) is equipped in the first internal bus(35). A barrel shifter(60) performs a scaling of logic values of data from the fifth multiplexer(56). The barrel shifter(60) is connected with the first ALU(Arithmetic Logic Unit)(58) in parallel. A rounding/saturation processor(86) selects N-bit data from the r+1th lower bit among g+N+r bit data from the tenth multiplexer(80). The rounding/saturation processor(86) performs the rounding of g+N+r bit data from the tenth multiplexer(80).

Description

Digital Signal Processor

The present invention relates to a digital signal processor (hereinafter referred to as "DSP") that processes various digital signals by software.

DSP is a kind of central processing unit (CPU) with arithmetic function. Originally, the electronics company of the United States "Texas Instruments" ("TI") "DSP5600x ", Developed under the leadership of" CS2923 "and" Medianix Semiconductor "of" Crystal Semiconductor. "These DSPs have recently been applied to the processing of video and audio signals, and their use has dramatically increased. In particular, among the various processing methods of audio signals, the audio compression algorithm "Musicam" or "Dolby", which is an international compression algorithm established by the Moving Picture Expert Group (MPEG), has been developed. DSPs that implement digital audio compression and restoration algorithms, such as the "AC-3", have emerged rapidly, so that some of the world's leading companies (especially those in the West) can increase their profits. A situation that spurred the development of its own proprietary DSP's.

The DSP for audio signal processing has a longer word length for internal operation compared to the fixed-point DSP of TI, which has been commonly used up to now. For example, the "TI" TMS320C5x series DSPs have 16-bit (Bits) data word lengths and 32-bit Arithmetic Logic Units (hereinafter referred to as "ALU"), while MEPG's "music" The latest DSPs, developed to implement Cam and Dolby's "AC-3", almost all have a data word length of more than 20 bits and an ALU of more than 48 bits. More specifically, DSPs such as Yamaha's "YSS243" and "Motorola" 's Med25201, etc., are all 24 bits to decode "Dolby"' s "AC-3" audio signal. It has a word length of 56 and an ALU of 56 bits. Also, DSPs such as "ZR38000" from "Zoran" and "MB86342" from "Fujitsu" are all 20-bit data word lengths for decoding audio signals of "Dolby" "AC-3". And 48 bit ALU.

The DSPs configured as described above operate two data having a length of N bits as shown in FIG. The first and second data 10, 12 are read from the memory and multiplied by a multiplier to generate third data that is the result of the multiplication. The first and second data 10, 12 both have a length of N bits and consist of an integer part and a fractional part. The third data 14, which is the result of multiplication of the multiplier, may have a maximum length of 2N bits, and is thus temporarily stored in a multiplication register of 2N bits. Subsequently, the third data 14 is shifted by the barrel shifter by the number of bits, for example, R bits, of the integer parts of the first and second data 10 and 12, which is a result of the shift. The fourth data 16 of 2N bits is calculated. The fourth data 16 is logically operated by the ALU to generate the fifth data 18. Overflow may occur in the fifth data 18 that is an operation result of the ALU. In order to deal with this overflow, in a DSP such as "TMS320C5x" of "TI", when the fifth data 18 has a bit length that is difficult to be stored in a 2N bit accumulation register, i.e., the fifth data 18 When an overflow occurs, the DSP of "" TMS320C5x "saturates the fifth data 18 and stores the saturated fifth data 18 in the accumulation register to mitigate the error due to the overflow. DSPs such as Motorola's "DSP5600x" add 8 bits to the accumulator register for overflow protection, as shown in Figure 1. In this case, both the ALU and the accumulator register have a length of "8 + 2N" bits. Applying this overflow protection bit to the "AC-3" dedicated DSPs listed above, DSPs with a 24-bit data word length have a 56-bit accumulator and a 20-bit data word because the data is N = 24 bits. Length Since DSPs have N = 20 bits, each of them has a 48-bit accumulator, and the fifth data 18 to which overflow protection bits are added is saturated and thus, the first and second data (stored in the memory) are stored. 6th data 20 having a bit length equal to 10, 12).

In order to perform the above series of operations, most DSPs had to have ALUs and cumulative registers having a large word length of 48 bits or more. They had to have these ALUs and cumulative registers with large word lengths of more than 48 bits. These ALUs and accumulators, which have large word lengths of 48 bits, increase the die size on the DSP chip and increase the amount of propagation delay in the ALU. Therefore, the ALU and accumulator having a large word length not only increases the manufacturing cost of the DSP chip but also acts as a factor of decreasing the operation speed of the DSP.

Most DSPs support rounding operations before saturating the data. For example, the "Motorola" DSP converts "8 + 2N" bits of data stored in the accumulation register into "8 + N" bits by the command "rnd". This rounded data is finally saturated with "N" bits of data and then stored in memory. For these rounding operations, most DSPs consume an additional instruction or clock period. This additional consumption of instructions or clock cycles results in a lot of additional clock cycles when the rounding operation is applied to the code segment to which looping or block repeating is applied. The amount of computation is greatly increased.

In addition, DSPs such as "TMS320C5x" from "TI" use a pre-scaling shifter located in front of the ALU to shift the binary data to be calculated in the ALU to the left from 0 to 16 bits. At this time, the shift operation from the "0" th bit to the "15" th bit is normally used to scale binary data, but the shift operation up to the "16" th bit is a fixed point, not an integer operation. ) Is used when the operation is performed. This is because in the case of fixed-point arithmetic, 16-bit data read from memory must be aligned with the upper bits of the 32-bit accumulation register. The shift operation of the "0" th bit to the "15" th bit for scaling data may or may not be usefully used depending on a given algorithm, in particular, a coding method. When performing algorithms implemented in code where prescaling is not useful, the scaling souper increases the DSP chip die size and increases propagation delay without much help. In one example, the pre-scaling shifter included in the "Motorola" DSP is to shift data one bit to the left or to the right. Instead, Motorola's DSPs offer different multiply instructions for floating-point and integer operations, absorbing the "TI" 's "TMS320C5x" shifting data left by 16 bits.

Next, in DSP, it is important to know how fast each instruction can be executed. For fast execution of instructions, the period of instructions applied to the DSP should be shortened and as many instructions as possible should be processed in parallel. Shortening the former instruction cycle is a hardware-, circuit-related problem that shortens the circuit path by eliminating unnecessary blocks (e.g., the pre-scaling shifters already mentioned) possible in the DSP. The parallelism of the latter instruction comes from the fact that DSPs are used for video / audio decoding, which requires a lot of computation, and the sequential instruction execution method of the past does not have the necessary computational capability. Therefore, DSPs are equipped with special instructions capable of parallel processing. For example, "DSP21020", a DSP of "Analog Device", has special instructions for performing multiple complex expressions in a few clock cycles, such as a butterfly operation for FFT operations. For this purpose, the "ADSP21020" has a register file consisting of at least 12 registers associated with the operation. In addition, Zor38000 also performs many complex equations, such as butterfly for FFT, in just a few clock cycles. To this end, the ZR38000 has a register file consisting of eight registers and a structure that performs multiplication and addition and subtraction of the result in one clock cycle.

Accordingly, an object of the present invention is to provide a DSP having a short word length accumulation register and an ALU.

Another object of the present invention is to provide a DSP that does not additionally consume clock periods for rounding data.

It is another object of the present invention to provide a DSP capable of performing a computation including a scaling of data at a high speed.

1 is a diagram schematically showing a signal processing procedure of a conventional DSP.

2 is a block diagram of a DSP in accordance with an embodiment of the present invention.

FIG. 3 is a view for explaining a fixed-point arithmetic process in which the rounding bit number is reduced to r smaller than the bit number N of data by the rounding / saturation processor 86 shown in FIG.

Explanation of symbols on the main parts of the drawings

30,40,44,48,64,66,76,78: first through eighth registers

32, 34, 82, 84: first to fourth bit sorter 38: guard bit adder

36,42,52,54,56,62,68,70,74,80,88: first to eleventh multiplexers

46: Multiplier 50: Wiring controller

58, 72: 1st and 2nd ALU 60: barrel shifter

86: rounding / saturation processor

In order to achieve the above object, the DSP according to the present invention provides data input means for inputting N bits of data, and rounding bit generation means for generating rounding bits of r bits smaller than N in the N bit data from the data input means. And guard bit adding means for adding g-bit guard bits to the upper bits of the data from the rounding bit generating means, arithmetic means for computing data from the guard bit adding means, and rounding processing for the data from the arithmetic means. Rounding / saturation processing means for selectively performing saturation processing and merging processing thereof.

DSP according to the present invention includes data input means for inputting N bits of data, rounding bit addition means for adding a rounding bit of r bits smaller than N to N bit data from the data input means, and rounding bit addition means. Guard bit adding means for adding a g-bit guard bit to an upper bit of data from the data source, operation logic means for calculating data from the guard bit adding means and data from the feedback loop, and data from the operation logic means. A memory for storing data and connected with a feedback loop, scaling means for scaling data from the guard bit adding means, selection means for selectively transferring data from the scaling means and data from the operation logic means to the memory, and Rounding, saturation and merging of these data The optionally provided with a rounding / saturation processing means for performing a.

The DSP according to the present invention includes data input means for inputting N bits of data, rounding bit addition means for adding r-bit rounding bits smaller than N to N-bit data from the data input means, and rounding bit addition means. A guard bit adding means for adding a g-bit guard bit of an upper bit of data of the data, a storage means for storing a product of two N-bit data, and deriving g + N + r bits of data from a product value from the storage means. A wiring controller, calculation means for calculating two of the data from the wiring controller and the guard bit adding means and an accumulated value, rounding means for rounding the data from the calculation means, and data from the rounding means And saturation processing means for saturating according to the logical value of the upper g + 1 bits.

Other objects and advantages of the present invention other than the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

Referring to Fig. 2, a first register 30 for inputting N bits of data from a first external bus 31, and first and second bit aligners connected in parallel to the first register 30, A DSP in accordance with an embodiment of the present invention having 32, 34 is shown. The first external bus 31 is composed of N data lines commonly connected to a working memory (not shown) and is used as an N-bit first read data bus. The first register 30 temporarily stores N bits of data from the memory via the first external bus 31. The first and second bit sorters 32 and 34 serve to extend data from N bits to N + r bits by shifting N bits of data from the first register 30. In detail, the first bit sorter 32 shifts N bits of data to the left by r bits for fixed-point arithmetic. To this end, the first bit aligner 32 has N-bit output lines of the first register 30 of the upper N input terminals of the first input port consisting of N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The second bit sorter 34 shifts N bits of data to the right by r bits for integer arithmetic. At this time, the upper r bits may be filled as sine (positive or negative) bits or filled with values of "0" depending on the DSP's Sign-Extension Mode. To this end, the second bit aligner 34 outputs N-bit output lines of the first register 30 to the lower N input terminals of the second input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The upper r bits are filled with the sign bit or "0" as mentioned above. The first multiplexer 36 stores N + r bits of data on the first input port or N + r bits of data on the second input port according to the type of operation, that is, fixed-point / integer operation. ) Is supplied to the adder 38. This first guard bit adder 38 adds g bits of guard bits to the N + r bits of data from the first multiplexer 36. The gbit guard bits are either all set to "0" or they extend the sign of the data. In detail, all g-bit guard bits have the same logical value as the sign bit of data when the sign-extension mode is set, and all logic values of "0" when the sign-extension mode is reset. . The sign-extension mode is set or reset by a particular instruction. In order to add these g-bit guard bits to the N + r bit data, the first guard bit adder 38 connects the output port of the first multiplexer 36, which consists of N + r terminals, to the first internal bus. A wiring is connected to the lower N + r lines among the g + N + r lines included in (35).

The DSP adds a second register 40 and a multiplier 46 connected in series to the first external bus 31 and a second multiplexer 42 connected to the first and second external buses 31 and 33. It is provided with. Like the first register 30, the second register 40 is responsible for temporarily storing N-bit data from the memory input via the first external bus 31. The second external bus 33 is composed of N lines commonly connected to a program memory and a CPU (not shown) and is used as a second read-only data bus. The second multiplexer 42 includes N bit data from the first external bus 31 supplied to its first input port and N bit data from the second external bus 33 supplied to its second input port. One data is supplied to the third register 44. The third register 44 temporarily stores N-bit data from the second multiplexer 42. Multiplier 46 multiplies two data stored in second and third registers 40 and 44. The result multiplied by this multiplier 46 may have 2N bits. As a result, the fourth register 48 that temporarily stores data from the multiplier 46 has a length of 2N bits. The wire controller 50 connected between the fourth register 48 and the second internal bus 37 converts 2N bits of data stored in the fourth register 48 into N + r bits of data smaller than 2N. A g-bit guard bit is added to the converted N + r-bit data.

The DSP includes third to fifth multiplexers 52 to 56 that are commonly connected to the first internal bus 35. The third multiplexer 52 has first to third input ports for inputting g + N + r bits of data from the first, second and fourth internal buses 35, 37 and 43, respectively. The third multiplexer 52 supplies any one of three data from the first, second and fourth internal buses 35, 37 and 43 to the first ALU 58. The fourth multiplexer 54 inputs g + N + r bits of data from the first input port 39 for inputting a logic value of “0” and the first and third internal buses 35 and 41, respectively. And second and third absorptive ports. The fourth multiplexer 54 supplies any one of three pieces of data on its first to third input ports to the first ALU 58. The first ALU 58 calculates two data from the third and fourth multiplexers 52 and 54 and supplies the calculated result to the sixth multiplexer 62. The fifth multiplexer 56 also selectively outputs g + N + r bits of data from the first internal bus 35 and g + N + r bits of data from the third internal bus 41 to the barrel shifter 60. To feed. The barrel shifter 60 scales the logical value of the data from the fifth multiplexer 56 and supplies the scaled data to the sixth multiplexer 62. In order to scale this data, the barrel shifter 60 shifts left or right of the data from the fifth multiplexer 56 by the number of bits corresponding to the scaling amount. In addition, since the barrel shifter 60 is connected in parallel with the first ALU 58, the propagation delay time of data can be minimized. Accordingly, the DSP can perform arithmetic operations, scaling and arithmetic operations including the same at high speed. The sixth multiplexer 62 selectively stores the g + N + r bits of the arithmetic data of the first ALU 58 and the scaled data from the barrel shifter 60 to the fifth or sixth register 64. Or 66). Data stored in the fifth or sixth register 64 or 66 is supplied to the third internal bus 41. The fifth and sixth registers 64 and 66 constitute a first accumulator together with the first ALU 58 as accumulation registers. Both the fifth and sixth registers 64 and 66 have a length of g + N + r bits to temporarily store g + N + r bits of data, and the third internal bus 41 also has g + N + r bits. It consists of two lines.

In addition, the DSP includes a seventh multiplexer 68 connected to the first internal bus 35 and the fourth internal bus 43, and an eighth multiplexer 70 connected to the first and second internal buses 35 and 37. ). The seventh multiplexer 68 inputs g + N + r bits of data from the first input port 45 and the first and fourth internal buses 35 and 43 to input a logic value of “0”, respectively. And second and third input ports. The seventh multiplexer 68 supplies one of three pieces of data on its first to third input ports to the second ALU 72. The eighth multiplexer 70 has first and second input ports for inputting g + N + r bits of data from the first and second internal buses 35 and 37, respectively. The eighth multiplexer 70 supplies either of the two data from the first and second internal buses 35, 37 to the second ALU 72. The second ALU 72 calculates two data from the seventh and eighth multiplexers 68 and 70 and supplies the calculated result to the ninth multiplexer 74. The ninth multiplexer 74 selectively stores the g + N + r bits of the computed data from the second ALU 72 and the scaled data from the barrel shifter 60 to the seventh or eighth register 76 or 78. To feed. The seventh or eighth registers 76 and 78 are configured to supply data from the ninth multiplexer 74 to the fourth internal bus 43. The seventh or eighth registers 76 and 78 constitute a second accumulator together with the second ALU 72 as a cumulative register, and the second accumulator is connected in parallel with the first accumulator so that two or more complex equations are added. To be computed in parallel. Both the seventh and eighth registers 76, 78 have a length of g + N + r bits to temporarily store g + N + r bits of data. In addition, the seventh or eighth registers 76, 78, together with the fifth and sixth registers 64,66, allow multiple complex expressions to be computed quickly.

Furthermore, the DSP is common to the tenth multiplexer 80 and the tenth multiplexer 80 for selecting two g + N + r bit data from the third and fourth internal buses 41 and 43. And third and fourth bit sorters 82,84 and a rounding / saturation processor 86 connected to each other. The tenth multiplexer 80 stores the data of g + N + r bits from the fifth or sixth registers 64 and 66 via the third internal bus 41 and the fourth internal bus 23. Commonly supply any of the g + N + r bits of data from the seventh or eighth registers 76,78 to the third and fourth bit sorters 82,84 and the rounding / saturation processor 86 do. The third and fourth bit aligners 82 and 84 extract only N bits from g + N + r bits of data from the tenth multiplexer 80 to extract the extracted N bits of data from the eleventh multiplexer 88. Supply to the first and second input ports respectively. In detail, the third bit sorter 82 extracts only N bits of data from the upper g + 1 th bit of the g + N + r bits from the tenth multiplexer 80 to extract the N bits of the extracted N bits. Data is supplied to the first input port of the eleventh multiplexer 88. To this end, the third bit sorter 82 may have N terminals, i.e., the upper g terminals and the lower r, from the upper g + 1 th terminal among the g + N + r output terminals of the tenth multiplexer 80. Wiring for connecting the remaining N terminals other than the N terminals to the first input port of the eleventh multiplexer 88 consisting of N terminals is provided. Only by wiring, the third bit sorter 82 converts data of g + N + r bits into N bits of data. The fourth bit sorter 84 extracts only the lower N bits of the data of g + N + r bits from the tenth multiplexer 80, and extracts the extracted N bits of data from the eleventh multiplexer 88. 2 Supply to the input port. For this purpose, the fourth bit sorter 84 may select N N terminals other than the lower N terminals, that is, the upper g + r terminals, among the g + N + r output terminals of the tenth multiplexer 80. And a wiring for connecting to the second input port of the eleventh multiplexer 88 consisting of four terminals. The fourth bit sorter 84, together with the first to third bit sorters 32, 34 and 82, is simply configured by wiring so that no separate circuit block is required. Accordingly, the first to fourth bit sorters 32, 34, 82, and 84 can simplify the circuit configuration of the DSP and allow both fixed-point and integer operations to be performed at high speed.

The rounding / saturation processor 86 is driven in the rounding processing mode, the saturation processing mode, or the merge mode in accordance with a command from a controller (not shown). The rounding / saturation processor 86 selects N bits of data from the r + 1 th lower bits in the g + N + r bits of the data from the tenth multiplexer 80 to generate the 11th multiplexer 88 data. 3 Supply to the input port. Next, in the saturation mode, the rounding / saturation processor 86 processes the data according to the logical value of the upper g + 1 bits in the g + N + r bits of the data from the tenth multiplexer 80. In detail, the rounding / saturation processor 86 performs the processing of the upper g + 1 bits (ie, g guard bits and one sign bit) in the g + N + r bits of data from the tenth multiplexer 80. It is determined whether overflow occurs according to whether all logic values are the same. When the logic values of the upper g + 1 bits are all the same, the rounding / saturator 86 performs the remaining N bits except for the upper g bit and the lower r bit among the g + N + r bits of data from the tenth multiplexer 80. Is supplied to the third input port of the eleventh multiplexer 88 as a result of the calculation. On the contrary, when the logic values of the upper g + 1 bits are not the same, the rounding / saturation processor 86 determines whether the logical value of the most significant bit of the g guard bits is “0” or “1”. When the logical value of the most significant guard bit is "0", the rounding / saturation processor 86 considers that the data from the tenth multiplexer 80 is positive data having overflowed, so that only the most significant bit is present. The N-bit data of the maximum value (ie, "0111 ... 11") having a logic value of "0" is supplied to the third input port of the eleventh multiplexer 88. In contrast, the logic value of the most significant guard bit is When " 1 ", the rounding / saturation processor 86 considers the data from the tenth multiplexer 80 to be negative data having overflowed, so that only the most significant bit of the rounding / saturation processor 86 has a logical value of " 1 " The branch supplies N bits of data (ie, “1000… 00”) to the third input port of the eleventh multiplexer 88. In this way, the saturation processor 86 supplies the logical values of the guard bits and the sine bits. The saturation logic of the data computed by the ALU 58 or 72 based on Finally, in merge mode, the rounding / saturation processor 86 performs the rounding process on g + N + r bits of data from the tenth multiplexer 80 and then rounds the rounded g. The N-bit data rounded and saturated by the rounding / saturation processor 86 is supplied to the eleventh multiplexer 88. In this case, rounding is performed. The saturation processor 86 performs the rounding process for the lower bits first, but does not consume separate rounding processing time by performing the rounding and saturation processing in one clock period, and thus, the rounding / saturation processor 86 ) Provides the advantage of rounding the fixed-point computed data without consuming extra time, and the eleventh multiplexer 88 can be used to round the third and fourth bitaligners 82 and 84. Saturation One of the three N-bit data from the recorder 86 is transferred to the third external bus 47. The third external bus 47 is a write data bus and a write address bus. It consists of N lines composed of Address Bus).

3 shows a fixed-point arithmetic process in which the rounding / saturation processor 86 shown in FIG. 2 reduces the number of rounding bits to r, which is smaller than the number of bits N of the data. In Fig. 3, the first and second data 90 and 92 are each sequentially read from a memory (not shown) and have a length of N bits, respectively. The most significant bit of the first and second data 90,92 also includes one bit of a sign bit indicating whether the logic value is negative or positive. These first and second data 90,92 are calculated by the multiplier 46 shown in Fig. 2 to generate third data 94 having a length of 2N bits. This third data 94 is converted into fourth data 96 by the wiring controller 50 shown in Fig. 2, and then g + N + r is added to the adjusted data with g bits of guard bits. The fourth data 96 of bits is changed. Where g is the number of guard bits and r is the number of rounding bits. The logical value of these guard bits and rounding bits may have any logical value other than "0" by operation and / or shift. The fifth data 98 is obtained by cutting the s-bit lower bits from the fourth data 96 and is used as input data of the ALUs 54 and 72. In addition, the fifth data 98 is temporarily stored in the accumulation register 64 or 76 or 66 or 78 having a length of g + N + r bits via the ALU 58 or 72. The fifth data 98 stored in the accumulation register 64 or 76 or 66 or 78 is processed by the rounding / saturation processor 86 shown in FIG. 2 to have sixth data 100 having a length of N bits. ). At this time, the fifth data 98 is first rounded to be converted into data of g + N bits, and then logical values of the upper g + 1 bits (that is, g guard bits and one sign bit) are added. Depending on whether the same and most significant guard bits are "1" or "0", they are processed in different ways and finally converted to N bits of data. When the logical values of the upper g + 1 bits are the same, the fifth data 98 is replaced with the sixth data 100 having the remaining N bits except the upper g bit and the lower r bit among the g + N + r bits. When the logical values of the upper g + 1 bits are not the same and the most significant bit is "0", the fifth data 98 is regarded as the positive data in which the overflow has occurred, and only the most significant bit has a logical value of "0". The branch is replaced with N bits of sixth data 100, that is, "0111 ... 11". In contrast, when the logic values of the upper g + 1 bits are not the same and the most significant bit is "1", the fifth data 98 is regarded as negative data having overflowed, so that only the most significant bit is " N-bit sixth data 100 having a logic value of 1 " 00 ". The sixth data 100 calculated by the calculation process as a whole has an approximate value where the error is minimized as much as possible.

As described above, the DSP of the present invention can shorten the lengths of the ALU and the accumulation register by adjusting the number of bits (i.e., word length) of data supplied to the ALU by wiring. In addition, the DSP according to the present invention can eliminate the time required for the rounding process of the data by performing the rounding of the data at the same time during the data saturation processing. Accordingly, the DSP according to the present invention can speed up signal processing.

In addition, in the DSP according to the present invention, since the bit sorters implemented as wirings are disposed at the front and rear ends of the accumulator, fixed-point and integer operations are performed quickly, and the circuit configuration is simplified.

Furthermore, the DSP according to the present invention can minimize the propagation delay time by connecting the barrel shifter to the ALU in parallel and can reduce the number of clocks required for the calculation. Accordingly, the DSP according to the present invention can perform calculations, scaling, and calculations including the same at high speed.

The DSP according to the present invention can compute a plurality of complex equations at high speed by computing two complex equations in parallel using a pair of ALUs connected in parallel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (13)

Data input means for inputting N bits of data, Rounding bit generating means for generating a rounding bit of r bits smaller than N in said N bit data from said data input means; Guard bit adding means for adding a g bit guard bit to an upper bit of data from the rounding bit generating means; Calculating means for calculating data from the guard bit adding means; And rounding / saturating processing means for selectively performing rounding processing, saturation processing, and merging processing thereof on the data from the computing means. The method of claim 1, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 1, The rounding / saturation processing means has N bits of data having only a logical value of "0" and only most significant bits of "1" when the logical values of the upper g + 1 bits of data from the calculating means are different. And digitally generating N bits of data having a logic value. The method of claim 1, The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "0" when the logical value of the most significant bit of the data from the computing means is "0" and the logical value of the most significant bit. And " 1 ", the digital signal processor characterized by generating only N bits of data having a logical value of " 1 ". The method of claim 1, And said rounding bit adding means is implemented by wiring. The method of claim 1, And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data, Rounding bit adding means for adding a round bit of r bits smaller than N to said N bit data from said data input means; Guard bit adding means for adding a g-bit guard bit to an upper bit of data from the rounding bit adding means; Arithmetic logic means for computing data from said guard bit adding means and data from a feedback loop; A memory for temporarily storing data from said operational logic means and connected to said feedback loop; Scaling means for scaling data from the guardbit adding means; Selecting means for selectively transferring data from the scaling means and data from the arithmetic logic means to the memory; And rounding / saturating processing means for selectively performing rounding processing, saturation processing, and merging processing thereof on the data from the memory. The method of claim 7, wherein The rounding / saturation processing means processes the data differently according to the logical value of the upper g + 1 bits of data from the memory during saturation processing, and the data from the memory is logic of the upper g + 1 bits of the data. And saturating only if the values differ. The method of claim 7, wherein The rounding / saturation processing means is configured such that if the logical values of the upper g + 1 bits of the data from the memory are different, only the most significant bit has a logic value of "0" and only the most significant bit has a logic of "1". And digitally generating N bits of data having a value. The method of claim 7, wherein The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the memory is "1", and the logical value of the most significant bit is And " 0 ", wherein only the most significant bit generates N bits of data having a logic value of " 0 ". The method of claim 7, wherein And said rounding bit adding means is implemented by wiring. The method of claim 7, wherein And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data, Rounding bit adding means for adding a round bit of r bits smaller than N to the N bit data from the data input means; Guard bit adding means for adding a g-bit guard bit to an upper bit of data from the rounding bit adding means; Storage means for storing a product of two N-bit data; A wiring controller for deriving data of g + N + r bits from the product value from the storage means; Calculating means for calculating two of the data from the wiring controller and the guard bit adding means and an accumulated value; Rounding means for rounding the data from said computing means; And saturation processing means for saturating the data from the rounding means according to the logical value of the upper g + 1 bits of the data.

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