KR100315303B1 - Digital signal processor - Google Patents

Abstract

PURPOSE: A digital signal processor is provided to execute an integer calculation and a fixed-point calculation effectively. CONSTITUTION: The first external bus(31) is used as the first read data bus of n-bit. The first register(30) temporarily stores 'n' bit data from a memory through the first external bus(31). The first and second bit aligners(32,34) shift the 'n' bit data from the first register(30), and extend the data from 'n' bit to 'N+r' bit. The first multiplexer(36) supplies data of "N+r" bit on the first input port or data of "N+r" bit on the second input port to the first guard bits attaching unit(38) in accordance with a fixed-point/integer calculation. The first guard bits attaching unit(38) attaches a guard bit to the "N+r" bit data from the first multiplexer(36). The guard bit is set as '0' all or extends a sign of data. The second register(40) temporarily stores 'n' bit data from a memory being inputted through the first external bus(31). The second external bus(33) is used as the second read data bus. The second multiplexer(42) supplies one of the data out of n' bit data from the first external bus(31) being supplied to the first input port and n' bit data from the second external bus(33) being supplied to the second input port to the third register(44). The third register(44) temporarily stores the 'n' bit data from the second multiplexer(42). A multiplier(46) multiplies two of the data stored in the second and third registers(40,44).

Description

Digital Signal Processor

The present invention relates to a digital signal processor (hereinafter referred to as a "DSP") for processing various digital signals by software.

DSP is a type of central processing unit (CPU) with arithmetic functions. It was originally developed by the US electronics company, Texas Instruments (TI). In recent years, the DSP has been applied to the processing of video and audio signals, and its use has increased rapidly.In particular, among the various processing methods of audio signals, audio compression has been established as an international standard by the Moving Picture Expert Group (MPEG). DSPs that implement the algorithm "Musicam" or "Dolby" 's digital audio compression and restoration algorithm "AC-3" are rapidly emerging. Many companies in the US, in particular, are spurring the development of their own DSPs to increase their profits.

The DSP for audio signal processing has a longer word length for internal operation compared to the fixed-point DSP of TI, which has been commonly used up to now. For example, the DSP of the TMS320C5x series from "TI" has a 16-bit data word length and a 32-bit Arithmetic Logic Unit (hereinafter referred to as "ALU"), while the MEPG "music" The latest DSPs, developed to implement Cam and Dolby's "AC-3", almost all have a data word length of more than 20 bits and an ALU of more than 48 bits. More specifically, "YSS243" from "Yamaha", "DSP5600x" from "Motorola", "CS2923" from "Crystal Semiconductor" and "Medianix Semiconductor (Medianix) Semiconductors, Inc.'s MED25201 and the like all have a 24-bit dada word length and a 56-bit ALU to decode the audio signal of "Dolby's" AC-3 ". Also, DSPs such as "ZR38000" from "Zoran" and "MB86342" from "Fujitsu" are all 20-bit data word lengths for decoding audio signals of "AC-3" from "Dolby". And 48 bit ALU.

The DSPs configured as described above operate two data having a length of N bits as shown in FIG. The first and second data 10, 12 are read from the memory and multiplied by a multiplier to generate third data that is the result of the multiplication. The first and second data 10, 12 both have a length of N bits and consist of an integer part and a fractional part. The third data 14, which is the result of multiplication of the multiplier, may have a maximum length of 2N bits, and is thus temporarily stored in a multiplication register of 2N bits. Subsequently, the third data 14 is shifted by a barrel shifter by the number of bits of the integer parts (eg, R bits) of the first and second data 10, 12, for example, R bits, and the shift result is 2N. A fourth data 16 of bits is to be calculated. The fourth data 16 is logically operated by the ALU to generate the fifth data 18. Overflow may occur in the fifth data 18 that is an operation result of the ALU. In order to deal with this overflow, the fifth data 18 is saturated in a DSP such as "TMS320C5x" by "TI". In detail, when the fifth data 18 calculated by the ALU has a bit length that is difficult to be stored in the 2N bit accumulation register, that is, when an overflow occurs in the fifth data 18, the DSP of "TMS320C5x" is generated. Saturates the fifth data 18 and stores the saturated fifth data 18 in an accumulation register to mitigate errors due to overflow. In contrast, DSPs such as "DSP5600x" from Motorola, Inc. add 8 bits to the accumulation register for overflow protection as shown in FIG. In this case, both the ALU and the accumulation register have a length of "8 + 2N" bits. Applying this overflow protection bit to the "AC-3" dedicated DSPs listed above, DSPs with 24-bit data word lengths have 56-bit accumulators and 20-bit data word lengths since the data is N = 24 bits. Since DSPs have N = 20 bits, each of them has a 48-bit accumulator. The fifth data 18 to which the overflow protection bits are added is converted into sixth data 20 having the same bit length as the first and second data 10 and 12 stored in the memory by being saturated.

In order to perform the above series of operations, most DSPs had to have ALUs and cumulative registers having a large word length of 48 bits or more. These ALUs and accumulators, which have large word lengths of 48 bits or more, increase the die size on the DSP chip and increase the amount of propagation delay in the ALU. Therefore, the ALU and accumulator having a large word length not only increases the manufacturing cost of the DSP chip but also acts as a factor of decreasing the operation speed of the DSP.

Most DSPs support rounding operations before saturating the data. For example, the "Motorola" DSP converts the data of "8 + 2N" bits stored in the accumulation register into "8 + N" bits by the command "rnd". This rounded data is finally saturated with "N" bits of data and then stored in memory. For these rounding operations, most DSPs consume an additional instruction or clock period.

This additional consumption of instructions or clock cycles results in a lot of additional clock cycles when the rounding operation is applied to the code segment to which looping or block repeating is applied. The amount of computation is greatly increased.

In addition, DSPs such as "TMS320C5x" from "TI" use a pre-scaling shifter located in front of the ALU to shift the binary data to be calculated in the ALU to the left from 0 to 16 bits. At this time, the shift operation from the "0" th bit to the "15" th bit is normally used to scale binary data, but the shift operation up to the "16" th bit is a fixed point, not an integer operation. ) Is used when the operation is performed. This is because in the case of fixed-point arithmetic, 16-bit data read from memory must be aligned with the upper bits of the 32-bit accumulation register. Shift operations from the "0" th bit to the "15" th bit for scaling data may or may not be usefully used depending on a given algorithm, in particular, a coding method. When performing algorithms implemented in code where prescaling is not useful, the scaling shifter increases the DSP chip die size and increases propagation delay without much help. In one example, the pre-scaling shifter included in the "Motorola" DSP is to shift data one bit to the left or to the right. Instead, Motorola's DSPs offer different multiply instructions for floating-point and integer operations, absorbing the "TI" 's "TMS320C5x" shifting data left by 16 bits.

Next, in DSP, it is important to know how fast each instruction can be executed. For fast execution of instructions, the period of instructions applied to the DSP should be shortened and as many instructions as possible should be processed in parallel. Shortening the former instruction cycle is a hardware-, circuit-related problem that shortens the circuit path by eliminating unnecessary blocks (e.g., the pre-scaling shifters already mentioned) possible in the DSP. The parallelism of the latter instruction comes from the fact that DSPs are used for video / audio decoding, which requires a lot of computation, and the sequential instruction execution method of the past does not have the necessary computational capability. Therefore, DSPs are equipped with special instructions capable of parallel processing. For example, "DSP21020", a DSP from "Analog Device", has special instructions for performing multiple complex expressions in a few clock cycles, such as a butterfly operation for FFT operations. For this purpose, the "ADSP21020" has a register file consisting of at least 12 registers associated with the operation. In addition, Zor38000 also performs many complex equations, such as butterfly for FFT, in just a few clock cycles. To this end, the ZR38000 has a register file consisting of eight registers and a structure that performs multiplication and addition and subtraction of the result in one click cycle.

Accordingly, an object of the present invention is to provide a DSP capable of efficiently performing integer operations and / or fixed point operations.

Another object of the present invention is to provide a DSP such that a click period is not added to the rounding of the data so that a clock period is not additionally added to the rounding of the additional data.

It is still another object of the present invention to provide a DSP capable of performing an operation including a scale of a logic value at a high speed.

1 is a diagram schematically showing a signal processing procedure of a conventional DSP.

2 is a block diagram of a DSP in accordance with an embodiment of the present invention.

3 is a block diagram illustrating a fixed point arithmetic operation and an integer arithmetic operation in FIG.

<Description of the code | symbol about the principal part of drawing>

30,40,44,48,64,66,76,78: first through eighth registers

32, 34, 82, 84: first to fourth bit sorter 38: guard bit adder

36,42,52,54,56,62,68,70,74,80,88: first to eleventh multiplexers

46: multiplier 38: beat controller

58,72: first and second ALU 60: barrel shifter

86: rounding / saturation processor

In order to achieve the above object, a DSP according to the present invention includes an input means for inputting N bits of data, a fixed shifter for shifting the N bit data from the input means to the left by r bits, and data from the fixed shifter. Calculating means for calculating and extracting means for extracting only the upper N bits from the data from the calculating means.

The DSP according to the present invention includes an input means for inputting N bits of data, a fixed shifter for shifting right by n bits to N bit data from the input means, an operation means for calculating data from the fixed shifter, and Extracting means for extracting only the lowest N bits from the data from the means.

The DSP according to the present invention has an input means for inputting N bits of data, a first fixed shifter that shifts left by n bits to N bits of data from the input means, and r bits in N bits of data from the input means. A second fixed shifter shifting to the right, first selecting means for selecting data from any one of the first and second fixed shifters, computing means for calculating data from the first selecting means, and First extracting means for extracting only upper N bits from data, second extracting means for extracting only lower N bits from data from arithmetic means, and second selecting means for data from either one of the first and second extracting means; Selection means is provided.

The DSP according to the present invention has an input means for inputting N bits of data, a fixed shifter for shifting the N bit data from the input means to the left by r bits smaller than N, and g in the upper bits of the data from the fixed shifter. Guard bit adding means for adding guard bits of bits, calculating means for calculating data from the guard bit adding means, extraction means for extracting N bits from the upper g + 1 bits of data from the calculating means, and calculating Rounding / saturation processing means for performing rounding and saturation of data from the means, and selection means for selecting data from either of the extraction means and the rounding / saturation processing means.

The DSP according to the present invention has an input means for inputting N bits of data, a fixed shifter for shifting the N bit data from the input means to the right by r bits smaller than N, and g in the upper bits of the data from the fixed shifter. Guard bit adding means for adding guard bits of bits, arithmetic means for computing data from the guard bit adding means, extracting means for extracting the lower N bits of data from the computing means, and data from the computing means. Rounding / saturation processing means for performing rounding and saturation processing, and selection means for selecting data from any one of extraction means and rounding / saturation processing means.

The DSP according to the present invention has an input means for inputting N bits of data, a first fixed shifter shifting left by n bits to N bits of data from the input means, and r bits in N bits of data from the input means. G-bit guard bits are added to the second fixed shifter shifting to the right, the first selecting means for selecting data from any one of the first and second fixed shifters, and the upper bits of the data from the first selecting means. The guard bit adding means, the calculating means for calculating the data from the guard bit adding means, the first extracting means for extracting the lower N bits from the data from the calculating means, and the upper g + 1th bit in the data from the calculating means. Second extracting means for extracting N bits from the lower side, and rounding / saturation processing for performing rounding and saturation of data from the computing means. Means, and second selection means for selecting data from any one of the first and second extraction means and the rounding / saturation processing means,

The DSP according to the present invention is a data input means for inputting N bits of data, a fixed shifter shifting left by n bits to N bit data from the input means, and g bits in the upper bits of the data from the fixed shifter. A guard bit adding means for adding guard bits of; a computing means for calculating data from the guard bit rich means and data from the feedback loop; a memory temporarily storing data from the computing means and connected to the feedback loop; Scaling means for scaling data from the bit appending means, first selecting means for selectively transferring data from the scaling means and data from the computing means into a memory, and the upper g + 1th bit in the data from the computing means; Extracting means for extracting N bits downward from Rounding / saturation processing means for performing rounding and saturation of the data, and second selection means for selecting data from any one of the extraction means and the rounding / saturation processing means.

The DSP according to the present invention is a data input means for inputting N bits of data, a fixed shifter for shifting right by n bits to N bit data from the input means, and g bits in the upper bits of the data from the fixed shifter. A guard bit adding means for adding guard bits of a; a computing means for calculating data from the guard bit adding means and data from the feedback loop; a memory temporarily storing data from the computing means and connected to the feedback loop; Scaling means for scaling the data from the bit appending means, first selecting means for selectively transferring the data from the scaling means and the data from the computing means into the memory, and extracting the lower N bits from the data from the memory; Means for performing rounding and saturation of data from memory. Has rounding / saturation processing means and second selection means for selecting data from either of the extraction means and the rounding / saturation processing means.

The DSP according to the present invention provides data input means for inputting N bits of data, a first fixed shifter shifting left by n bits to N bit data from the input means, and r bits in the N bit data from the input means. A second fixed shifter shifting to the right by a number, first selecting means for selecting data from either one of the first and second fixed shifts, and a g-bit guard bit in an upper bit of the data from the first selecting means. Guard bit adding means for adding the data, a computing means for calculating data from the guard bit adding means and data from the feedback loop, a memory temporarily storing data from the computing means and connected to the feedback loop, and guard bit adding means. Scaling means for scaling data from the data and from the data and computing means Second selecting means for selectively transferring data to the memory, first extracting means for extracting the lower N bits from the data from the memory, and lower N bits from the upper g + 1 th bit from the data from the memory; Second extracting means, rounding / saturating processing means for rounding and saturating data from the memory, and first and second extracting means and data for selecting data from any one of the rounding / saturating processing means. Three selection means are provided.

Other objects and advantages of the present invention other than the above object will be apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to Figures 2 and 4 attached to an embodiment of the present invention will be described in detail.

Hereinafter, with reference to Figures 2 and 3 attached to an embodiment of the present invention will be described in detail.

Referring to Fig. 2, a first register 30 for inputting N bits of data from a first external bus 31, and first and second bit aligners connected in parallel to the first register 30, A DSP in accordance with an embodiment of the present invention having 32, 34 is shown. The first external bus 31 is composed of N data lines commonly connected to a working memory (not shown) and is used as an N-bit first read data bus. The first register 30 temporarily stores N bits of data from the memory via the first external bus 31. The first and second bit sorters 32 and 34 serve to extend data from N bits to N + r bits by shifting N bits of data from the first register 30. In detail, the first bit sorter 32 shifts N bits of data to the left by r bits for fixed-point arithmetic. To this end, the first bit sorter 32 connects the N-bit output lines of the first register 30 to the upper N input terminals of the first input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The second bit sorter 34 shifts N bits of data to the right by r bits for integer arithmetic. At this time, the upper r bits may be filled as sine (positive or negative) bits or filled with values of "0" according to the DSP's Sign-Extension Mode. To this end, the second bit sorter 34 connects N-bit output lines of the first register 30 to the lower N input terminals of the second input port including N + r terminals of the first multiplexer 36. Wiring to be connected to each other. The upper r bits are filled with the sign bit or "0" as mentioned above. The first multiplexer 36 receives N + r bits of data on the first input port or N + r bits of data on the second input port according to the type of operation, that is, fixed-point / integer operation. ) Is supplied to the adder 38. This first guard bit adder 38 adds g bits of guard bits to the N + r bits of data from the first multiplexer 36. Guard bits of g bits are all set to "0" or extend the sign of the data. In detail, all g-bit guard bits have the same logic value as the sign bit of data when the sign-extension mode is set, and all logic values of "0" when the sign-extension mode is reset. . The sign-extension mode is set or reset by a specific instruction. In order to add these g-bit guard bits to the N + r bit data, the first guard bit adder 38 is divided into N + r terminals. The output port of the first multiplexer 36 is connected to the lower N + r lines among the g + N + r lines included in the first internal bus 35.

The DSP adds a second register 40 and a multiplier 46 connected in series to the first external bus 31 and a second multiplexer 42 connected to the first and second external buses 31 and 33. It is provided with. Like the first register 30, the second register 40 is responsible for temporarily storing N-bit data from the memory input via the first external bus 31. The second external bus 33 is composed of N lines commonly connected to a program memory and a CPU (not shown) and is used as a second read-only data bus. The second multiplexer 42 includes N bit data from the first external bus 31 supplied to its first input port and N bit data from the second external bus 33 supplied to its second input port. Any data is supplied to the third register 44, which temporarily stores the N bit data from the second multiplexer 42. Multiplier 46 multiplies two data stored in second and third registers 40 and 44. The result multiplied by this multiplier 46 may have 2N bits. Accordingly, the fourth register 48 that temporarily stores data from the multiplier 46 has a length of 2N bits. The wiring controller 50 connected between the fourth register 48 and the second internal bus 37 converts 2N bits of data stored in the fourth register 48 into N + r bits of data smaller than 2N. A g-bit guard bit is added to the converted N + r-bit data.

The DSP includes third to fifth multiplexers 52 to 56 that are commonly connected to the first internal bus 35. The third multiplexer 52 has first to third input ports for inputting g + N + r bits of data from the first, second and fourth internal buses 35, 37 and 43, respectively. The third multiplexer 52 supplies any one of three data from the first, second and fourth internal buses 35, 37 and 43 to the first ALU 58. The fourth multiplexer 54 inputs g + N + r bits of data from the first input port 39 for inputting a logic value of “0” and the first and third internal buses 35 and 41, respectively. And second and third input ports. The fourth multiplexer 54 supplies any one of three pieces of data on its first to third input ports to the first ALU 58. The first ALU 58 computes two data from the third and fourth multiplexers 52 and 54 and supplies the calculated result to the sixth multiplexer 62. The fifth multiplexer 56 also selectively outputs g + N + r bits of data from the first internal bus 35 and g + N + r bits of data from the third internal bus 41 to the barrel shifter 60. To feed. The barrel shifter 60 scales the logical value of the data from the fifth multiplexer 56 and supplies the scaled data to the sixth multiplexer 62. In order to scale this data, the barrel shifter 60 shifts left or right of the data from the fifth multiplexer 56 by the number of bits corresponding to the scaling amount. In addition, since the barrel shifter 60 is connected in parallel with the first ALU 58, the propagation delay time of data can be minimized. Accordingly, the DSP can perform arithmetic operations, scaling and arithmetic operations including the same at high speed. The sixth multiplexer 62 selectively selects the g + N + r bits from the first ALU 58 and the scaled data from the barrel shifter 60 to the fifth or sixth register 64. Or 66). Data stored in the fifth or sixth register 64 or 66 is supplied to the third internal bus 41. The fifth and sixth registers 64 and 66 constitute the first accumulator together with the first ALU 58 as accumulation registers. Both the fifth and sixth registers 64 and 66 have a length of g + N + r bits to temporarily store g + N + r bits of data, and the third internal bus 41 also has g + N + r bits. It consists of two lines.

In addition, the DSP includes a seventh multiplexer 68 connected to the first internal bus 35 and the fourth internal bus 43, and an eighth multiplexer 70 connected to the first and second internal buses 35 and 37. ). The seventh multiplexer 68 inputs g + N + r bits of data from the first input port 45 and the first and fourth internal buses 35 and 43 to input a logic value of “0”, respectively. And second and third input ports. The seventh multiplexer 68 supplies any one of three pieces of data on its first to third input ports to the second ALU 72. The eighth multiplexer 70 has first and second input ports for inputting g + N + r bits of data from the first and second internal buses 35 and 37, respectively. The eighth multiplexer 70 supplies any one of two data from the first and second internal buses 35, 37 to the second ALU 72. The second ALU 72 calculates two data from the seventh and eighth multiplexers 68 and 70 and supplies the calculated result to the ninth multiplexer 74. The ninth multiplexer 74 selectively stores the g + N + r bits of the computed data from the second ALU 72 and the scaled data from the barrel shifter 60 to the seventh or eighth register 76 or 78. To feed. The seventh or eighth registers 76 and 78 are supplied with data from the ninth multiplexer 74 to the fourth internal bus 43. The seventh and eighth registers 76 and 78 constitute a second accumulator together with the second ALU 72 as a cumulative register. To be computed in parallel. Both the seventh and eighth registers 76, 78 have a length of g + N + r bits to temporarily store g + N + r bits of data. In addition, the seventh and eighth registers 76 and 78, together with the fifth and sixth registers 64 and 66, allow multiple complex expressions to be computed quickly.

Furthermore, the DSP is common to the tenth multiplexer 80 and the tenth multiplexer 80 for selecting two g + N + r bit data from the third and fourth internal buses 41 and 43. Third and fourth bit aligners 82 and 84 and a rounding / saturation processor 82 connected to are further provided. The tenth multiplexer 80 stores the data of g + N + r bits from the fifth or sixth registers 64 and 66 via the third internal bus 41 and the fourth internal bus 23. Commonly supplies any of the g + N + r bits of data from the seventh or eighth registers 76,78 to the third and fourth bit sorters 82,84 and the rounding / saturation processor 86. do. The third and fourth bit sorters 82 and 84 extract only N bits from g + N + r bits of data from the tenth multiplexer 80 to extract the extracted N bits of data from the eleventh multiplexer 88. Supply to the first and second input ports respectively. In detail, the third bit sorter 82 extracts only N bits of data from the upper g + 1 th bit of the g + N + r bits from the tenth multiplexer 80 to extract the N bits of the extracted N bits. Data is supplied to the first input port of the eleventh multiplexer 88. For this purpose, the third bit sorter 82 may have N terminals from the upper g + 1 th terminal among the g + N + r output terminals of the tenth multiplexer 80, that is, the upper g terminals and the lower r. Wiring for connecting the remaining N terminals except for the N terminals to the first input port of the eleventh multiplexer 88 including N terminals is provided. Only by wiring, the third bit sorter 82 converts data of g + N + r bits into N bits of data. The fourth bit sorter 84 extracts only the lower N bits of the data of the g + N + r bits from the tenth multiplexer 80, and extracts the extracted N bits of data from the eleventh multiplexer 88. 2 Supply to the input port. To this end, the fourth bit sorter 84 may select N N terminals other than the lower N terminals, that is, the upper g + r terminals, among the g + N + r output terminals of the tenth multiplexer 80. And a wiring for connecting to the second input port of the eleventh multiplexer 88 consisting of four terminals. The fourth bit sorter 84, together with the first to third bit sorters 32, 34 and 82, is simply configured by wiring so that no separate circuit block is required. Accordingly, the first to fourth bit sorters 32, 34, 82, and 84 can simplify the circuit configuration of the DSP and allow both fixed-point and integer operations to be performed at high speed.

The rounding / saturation processor 86 is driven in the rounding processing mode, the saturation processing mode, or the merge mode in accordance with a command from a controller (not shown). In the rounding mode, the rounding / saturation processor 86 selects N bits of data from the r + 1 th lower bits in the g + N + r bits of data from the 10th multiplexer 80 to select the 11th multiplexer. It is supplied to the 3rd input port of (88). Next, in the saturation mode, the rounding / saturation processor 86 processes the data according to the logical value of the upper g + 1 bits in the g + N + r bits of the data from the tenth multiplexer 80. In detail, the rounding / saturation processor 86 performs the processing of the upper g + 1 bits (ie, g guard bits and one sign bit) in the g + N + r bits of data from the tenth multiplexer 80. It is determined whether overflow occurs according to whether all logic values are the same. When the logic values of the upper g + 1 bits are all the same, the rounding / saturation processor 86 performs the remaining N bits except for the upper g bit and the lower r bit among the g + N + r bits of data from the tenth multiplexer 80. Is supplied to the third input port of the eleventh multiplexer 88 as a result of the calculation. On the contrary, when the logic values of the upper g + 1 bits are not the same, the rounding / saturation processor 86 determines whether the logical value of the most significant bit of the g guard bits is “0” or “1”. When the logical value of the most significant guard bit is "0", the rounding / saturation processor 86 considers that the data from the tenth multiplexer 80 is positive data having overflowed, so that only the most significant bit is present. A maximum value of N bits of data having a logical value of "0" (that is, "0111 ... 11") is supplied to the third input port of the eleventh multiplexer 88. In contrast, when the logical value of the most significant guard bit is "1", the rounding / saturation processor 86 considers the data from the tenth multiplexer 80 to be the negative (0) data from which the overflow occurred. Only N-bit data (ie, "1000 ... 00") having a logic value of "1" is supplied to the third input port of the eleventh multiplexer 88. In this way, the saturation processor 86 can correctly process the saturation logic of the data calculated by the ALU 58 or 72 based on the logic values of the guard bits and the sine bits (that is, the logic value at which the overflow occurred). do. Finally, in merge mode, the rounding / saturation processor 86 performs the rounding process on the g + N + r bits of data from the tenth multiplexer 80 and then rounds the rounded g + N bits of data. Saturation treatment is performed. The N-bit data rounded and saturated by the rounding / saturation processor 86 is supplied to the eleventh multiplexer 88. In this case, the rounding / saturation processor 86 performs rounding processing for the lower bits first, but does not consume a separate rounding processing time by performing the rounding and saturation processing in one clock period. Accordingly, the rounding / saturation processor 86 provides an advantage of rounding the data that has been fixed point operation without consuming extra time. The eleventh multiplexer 88 transmits any one of three N-bit data from the third and fourth bit sorters 82 and 84 and the rounding / saturation processor 86 to the third external bus 47. The third external bus 47 is composed of N lines composed of a write data bus and a write address bus.

FIG. 3 is a block diagram illustrating a fixed point arithmetic operation and an integer arithmetic operation in FIG. 2. In Fig. 3, the register 100 temporarily stores N bits of data from a memory not shown. The first bit sorter 102 scales up the N-bit data by shifting the N-bit data from the register 102 to the left by an arbitrary number of bits r smaller than N by wiring. Similarly, the second bit sorter 104 also scales down the N-bit data by shifting the N-bit data from the register 102 to the right by an arbitrary number of bits r smaller than N by wiring. Then, the accumulator 106 performs fixed-point accumulation by accumulating N + r bits of data sequentially input from the first bit sorter 102 or sequentially from the second bit sorter 104. Integer accumulation is performed by accumulating N + r bits of data. The third bit sorter 108 transfers only the upper N bits of the data of the N + r bits accumulated by the accumulator 106 to the near memory using a wiring structure. As a result, the first and third bit sorters 108 shift the data by wiring so that fixed-point arithmetic operations are performed at high speed. The fourth bit sorter 110 transfers only the lower N bits of data of the N + r bits accumulated by the accumulator 106 to the memory using a wiring structure. As a result, the second and fourth bit sorters 104 and 110 shift the data by wiring so that integer operations are performed at high speed. By shifting data by wiring in this way, the DSP does not require a separate circuit block such as a shifter, and can also perform fixed-point and integer operations quickly.

As described above, the DSP of the present invention can shorten the length of the ALU and the accumulation register by adjusting the number of bits (i.e., word length) of data supplied to the ALU by wiring. In addition, the DSP according to the present invention can eliminate the time required for the rounding process of the data by performing the rounding of the data at the same time during the data saturation processing. Accordingly, the DSP according to the present invention can speed up signal processing.

In addition, in the DSP according to the present invention, since the bit sorters implemented as wirings are disposed at the front and rear ends of the accumulator, fixed-point and integer operations are performed quickly, and the circuit configuration is simplified.

Furthermore, the DSP according to the present invention can minimize the propagation delay time by connecting the barrel shifter to the ALU in parallel and can reduce the number of clocks required for the calculation. Accordingly, the DSP according to the present invention can perform calculations, scaling, and calculations including the same at high speed.

The DSP according to the present invention can compute a plurality of complex equations at high speed by computing two complex equations in parallel using a pair of ALUs connected in parallel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (51)

Input means for inputting N bits of data, A fixed shifter for shifting the N-bit data from the input means to the left by r bits; Calculating means for calculating data from the fixed shifter; And extracting means for extracting only upper N bits from said data from said calculating means. The method of claim 1, Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. The method according to claim 1 or 2, And the extraction means is implemented by wiring. Input means for inputting N bits of data, A fixed shifter for shifting the N-bit data from the input means to the right by r bits; Calculating means for calculating data from the fixed shifter; And extracting means for extracting only the lower N bits from said data from said calculating means. The method of claim 4, wherein Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. The method according to claim 4 or 5, And the extraction means is implemented by wiring. Input means for inputting N bits of data, A first fixed shifter for shifting the N-bit data from the input means to the left by r bits; A second fixed shifter for shifting the N-bit data from the input means to the right by r bits; First selecting means for selecting data from either one of said first and second fixed shifters; Calculating means for calculating data from said first selecting means; First extracting means for extracting only the upper N bits from the data from the computing means; Second extraction means for extracting only the lower N bits from the data from the computing means; And second selection means for selecting data from either one of said first and second extraction means. The method of claim 7, wherein And the first and second fixed shifters are implemented by wiring. The method according to claim 7 or 8, And the first and second extraction means are implemented by wiring. Input means for inputting N bits of data, A fixed shifter for shifting the N-bit data from the input means to the left by r bits smaller than N; Guard bit adding means for adding a g bit guard bit to an upper bit of data from said fixed shifter; Calculating means for calculating data from the guard bit adding means; Extraction means for extracting N bits from an upper g + 1 bit of data from said computing means; Rounding / saturation processing means for rounding and saturating data from the computing means; And a selection means for selecting data from either the extraction means or the rounding / saturation processing means. The method of claim 10, And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 11, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 12, The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the computing means is "1" and the data from the computing means. And when the logical value of the most significant bit is " 0 ", only the most significant bit generates N bits of data having a logic value of " 0 ". The method according to any one of claims 10 to 13, Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. The method of claim 14, And the extraction means is implemented by wiring. The method of claim 14, And the guard bit adding means is implemented by wiring. Input means for inputting N bits of data, A fixed shifter for shifting the N bit data from the input means to the right by r bits smaller than N; Guard bit adding means for adding a g bit guard bit to an upper bit of data from the fixed shifter; Calculating means for calculating data from the guard bit adding means; Extraction means for extracting the lower N bits of the data from the calculation means; Rounding / saturating processing means for performing rounding and saturation processing on the data from said computing means according to a logic value of upper g + 1 bits of the data; And selection means for selecting data from either the extraction means or the rounding / saturation processing means. The method of claim 17, And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 18, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 19, The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the computing means is "1" and the data from the computing means. And when the logical value of the most significant bit is " 0 ", only the most significant bit generates N bits of data having a logic value of " 0 ". The method according to any one of claims 17 to 20, Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. The method of claim 21, And the extraction means is implemented by wiring. The method of claim 22, And the guard bit adding means is implemented by wiring. Input means for inputting N bits of data, A first fixed shifter for shifting the N-bit data from the input means to the left by r bits; A second fixed shifter for shifting the N-bit data from the input means to the right by r bits; First selecting means for selecting data from either one of said first and second fixed shifters; Guard bit adding means for adding g bits of guard bits to the upper bits of data from said first selecting means; Calculating means for calculating data from the guard bit adding means; First extracting means for extracting a lower N bit from data from said computing means; Second extracting means for extracting N bits downward from an upper g + 1 th bit in said data from said computing means; Rounding / saturation processing means for rounding and saturating data from the computing means; And second selection means for selecting data from any one of the first and second extraction means and the rounding / saturation processing means. The method of claim 24, And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 25, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 26, The rounding / saturation processing means generates N bits of data having a logical value of "1" when only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from to the calculating means is from the calculating means. And when the logical value of the most significant bit of the data is " 0 ", only the most significant bit generates N bits of data having a logical value of " 0 ". The method according to any one of claims 24 to 27, And the first and second fixed shifters are implemented by wiring. The method of claim 28, And the first and second extraction means are implemented by wiring. The method of claim 28, And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data; A fixed shifter for shifting the N-bit data from the input means to the left by r bits; Guard bit adding means for adding g bits of guard bits to the upper bits of the data from the fixed shift; Calculating means for calculating data from the guard bit adding means and data from the feedback loop; A memory for temporarily storing data from said computing means and connected to said feedback loop; Scaling means for scaling data from the guardbit adding means; First selecting means for selectively transferring data from the scaling means and data from the computing means to the memory; Extraction means for extracting N bits downward from an upper g + 1 th bit in said data from said computing means; Rounding / saturation processing means for performing rounding and saturation processing of data from said computing means; And second selection means for selecting data from either the extraction means or the rounding / saturation processing means. The method of claim 31, wherein And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 32, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 33, wherein The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the computing means is "1" and the data from the computing means. And when the logical value of the most significant bit of " 0 " is " 0 " The method according to any one of claims 31 to 34, wherein Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. 36. The method of claim 35 wherein And the extraction means is implemented by wiring. 36. The method of claim 35 wherein And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data; A fixed shifter for shifting right by the N bit data r bits from the input means; Guard bit adding means for adding g bits of guard bits to the upper bits of the data from the fixed shift; Calculating means for calculating data from the guard bit adding means and data from the feedback loop; A memory for temporarily storing data from said computing means and connected to said feedback loop; Scaling means for scaling data from the guardbit adding means; First selecting means for selectively transferring data from the scaling means and data from the computing means to the memory; Extraction means for extracting a lower N bit from the data from the memory; Rounding / saturating processing means for rounding and saturating data from the memory; And second selection means for selecting data from either the extraction means or the rounding / saturation processing means. The method of claim 38, And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 39, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 40, The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the computing means is "1" and the data from the computing means. And when the logical value of the most significant bit of " 0 " is " 0 " The method according to any one of claims 38 to 41, Digital signal processor, characterized in that the fixed shifter is implemented by a wiring. The method of claim 42, And the extraction means is implemented by wiring. The method of claim 42, And the guard bit adding means is implemented by wiring. Data input means for inputting N bits of data; A first fixed shifter for shifting the N-bit data from the input means to the left by r bits; A second fixed shifter for shifting the N-bit data from the input means to the right by r bits; First selecting means for selecting data from either one of said first and second fixed shifts; Guard bit adding means for adding g-bit guard bits to upper bits of data from said selecting means; Calculating means for calculating data from the guard bit adding means and data from the feedback loop; A memory for temporarily storing data from said computing means and connected to said feedback loop; Scaling means for scaling data from the guardbit adding means; Second selecting means for selectively transferring data from said scaling means and data from said computing stage to said memory; First extracting means for extracting a lower N bit from the data from the memory; Second extraction means for extracting a lower N bit from an upper g + 1 th bit in the data from the memory; Rounding / saturating processing means for rounding and saturating data from the memory; And third selecting means for selecting data from any one of said first and second extracting means and said rounding / saturation processing means. The method of claim 45, And said rounding / saturation processing means selectively performs said rounding processing, said saturation processing, and a merging processing thereof on data from said computing means. The method of claim 46, And said rounding / saturation processing means processes said data differently according to a logic value of upper g + 1 bits of data from said computing means during saturation processing. The method of claim 47, The rounding / saturation processing means generates N bits of data in which only the most significant bit has a logic value of "1" when the logical value of the most significant bit of the data from the computing means is "1" and the data from the computing means. And when the logical value of the most significant bit is " 0 ", only the most significant bit generates N bits of data having a logic value of " 0 ". 49. The method of any of claims 45-48, And the first and second fixed shifters are implemented by wiring. The method of claim 49, And the first and second extraction means are implemented by wiring. The method of claim 49, And the guard bit adding means is implemented by wiring.

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