JP3288074B2 - Address generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generation circuit and, more particularly, to an address generation circuit for generating an address of a data memory of a signal processing device which handles time-series data such as audio signals.

[0002]

2. Description of the Related Art Conventionally, an address generation circuit for generating a data memory address in a signal processing device which handles time-series data such as audio signal processing has a pointer for holding an address, one system for each memory area. Or 2
It had only strains.

[0003] As an example of time series data processing, an audio data processing apparatus will be described here.

In audio data processing, one set of audio data is input every sampling period, processing is performed in synchronization with this sampling period, and calculation is performed in synchronization with the input data during the next sampling period. Output the result. The main processing operation is filter operation processing. In the filter operation, the input data or the data in the middle of the operation is held for several sampling cycles, the held data is read out, the operation is performed on the newly input data, and the new input data is newly used as the data in the middle of the operation. This is realized by an operation of holding (updating). Usually though these data holding means data memory is used, data is read, how allows the use of efficient data memory by generating method addresses when writing came taken.

[0005] For example, as shown in FIG. 4, a memory map of a data memory of an apparatus for performing audio signal processing when realizing by combining the second-order IIR filters 10a to 10c is shown in FIG. According to these drawings, the data memory 20
Will be described.

FIG. 4 is a signal flow chart of the second-order IIR filter unit at time n, where 10a, 10b,
A three-stage cascade configuration of a secondary IIR filter composed of 10c is adopted. Data on the non-feedback side of the secondary IIR filter 10a is A1n, and data on the feedback side is B1n. Here A1
The 1 in n indicates that it is the first second-order IIR filter 10a, and the n indicates that it is data at time n. Similarly, in the second-order IIR filter 10b, each data is stored in A2
n, B2n, and A3n, B3n in the filter 10c.

Now, at time n, the secondary IIR shown in FIG.
The operation of the filter 10a is performed. At this time, the data memory 20
Is m. First, in order to calculate the data of the node N1, data A1 (n-
2) is read, and at the same time, the value of the address pointer is incremented by +1
I do. Next, to calculate the data of the node N2, (m +
1) The data A1 (n-1) stored at the address is read out, and at the same time, the value of the address pointer is incremented by +1. Next, the data A1n calculated from the input data is stored in the address (m +
2), and at the same time, increment the value of the address pointer by +1.
I do. Similarly, data reading and writing are sequentially performed.

From address (m + 3) to B1 (n-2),
B1 (n-1) is read from address (m + 4), and B1n is written to address (m + 5). Address (m +
6), A2 (n−2) is read, and the address (m +
7), A2 (n-1) is read out, and the address (m +
8) A2n is written. From address (m + 9) to B2
(N-2) is read, and B2 is read from the address (m + 10).
Read (n-1) and write to address (m + 11). A3 (n-2) is read from address (m + 12), A3 (n-1) is read from address (m + 13), and A3n is written to address (m + 14). B3 (n-2) is read from the address (m + 15), B3 (n-1) is read from the address (m16), B3n is written into the address (m + 17), and a series of filter operations ends.

Next, at the time (n + 1), when performing the filter operation again, the same operation as described above can be realized by executing the initial operation of the memory address at the address (m + 1). That is, A1 (n-1) is read from address (m + 1), A1n is read from address (m + 2), and A1 (n +) is read from address (m + 3).
Write 1).

By performing the same operation as in the case of time n, a filter operation of time (n + 1) can be performed.

However, in order to obtain the initial value of the address of the memory at the time n and the initial value of the address of the memory at the time (n + 1) (m + 1), m Alternatively, it is necessary to hold the value of (m + 1). Therefore, usually, the value of m or (m + 1) is temporarily saved in data holding means different from the data pointer, and the value is read out at time (n + 1). A method has been adopted in which +1 is added for each operation cycle, the data is temporarily transferred to the other pointer, and this pointer is operated to generate a memory address.

Separately from this, the data pointer is doubled, and one of the pointers holds initial value data incremented by one in each of the above-described filter operation cycles, and an offset from the initial value data on the instruction code. There is also a method of instructing the amount, adding the initial value data each time, writing the data to the other data pointer, and reading and writing the data. For example, at time n, when m is held as the initial value, A1 (n-2) is read from (m + 0), A1 (n-1) is read from (m + 1), and (m
+1) is written in A1n. This "0", "1",
Fixed data such as “2” is set on the instruction code.
In the case of time (n + 1), the initial data is updated to (m + 1), and similarly, m + 1 + 0 = m + 1 to A1 (n−
1) is read, A1n is read from m + 1 + 1 = m + 2, and A1n is written to m + 1 + 2 = m + 3. Hereinafter, a series of filter operations are performed by the same operation.

Next, a case will be described in which double-precision arithmetic is performed only on some data.

In the second-order IIR filter operation shown in FIG. 4, B1 (n-1), B2 (n-1), B3 (n-
Consider a case where an operation is performed with double precision only on data corresponding to 1). For B1 (n-1), the upper (H) and lower (h) are read from addresses (m + 10) and (m + 11), respectively, and then B1nH is written to address (m + 12) and B1nL is written to address (m + 13). In the case of the single-precision operation, that is, when the data shown in FIG. 5 is held, when overwriting B1n, writing was performed to the address where A2 (n−3) was written. Since it is necessary to hold the data on the lower side, A2
An empty area is required between (n-3) and A2 (n-2). Therefore, when writing A2n data,
It is necessary to write A2n with an empty area next to A2 (n-1). Also, at time (m + 1), B
The data of 1 (n-1) L is unnecessary, but this area is also a wasteful area. In the case of the single precision operation, as shown in FIG. 5, a memory area of 18 words is necessary. However, when any one data is operated in double precision, as shown in FIG. The memory area is equivalent to 38 words, which significantly reduces the efficiency of memory use.

[0015]

In this conventional address generation circuit, an address is described in an instruction code because a memory address is specified by a value held by a data pointer. For example, when the access is performed, it is necessary to rewrite the value of the program counter. Therefore, there is a problem that the value held by the program counter is destroyed.

Further, of the operation data stored in the memory,
If an attempt is made to perform the operation with double precision only for some data, it is necessary to secure an area for holding lower-order data when performing double precision even for data for which double precision operation is not performed. There has been a problem of remarkable reduction.

Further, for the pointer updated for each of the above series of processing units, an offset amount to each data is described on an instruction code and added to or calculated with a value held in the pointer. In the method of generating an address, an area for holding a calculation result of a base pointer value and an offset amount, and an address value at the time of performing a subroutine or the like in a subroutine when the programming is performed in the subroutine, in the subroutine. Another address holding area is required to use as the basic address, and in the conventional address generation circuit, when performing a subroutine in this method, the start address for each processing unit is transferred to another data holding area. ， Need to save, leading to lower processing efficiency.

[0018]

SUMMARY OF THE INVENTION An address generation circuit according to the present invention is updated in each cycle of signal processing executed in a predetermined cycle, and holds and outputs a start address of a data memory in each cycle. Address holding means, second address holding means for holding and outputting addresses sequentially updated for each data access in each cycle, and third address holding means for holding and outputting specific addresses updated at a specific timing. Address holding means, and the first, second, and third
Select one of the output addresses of the address holding means
A selection circuit for outputting a selection address, the selection 択A <br/> first before Symbol by adding a predetermined value to dress, second, third address holding means updates address to adder outputs When,
Said data memory holds the output address of the adder
And fourth address holding means for outputting as an output address .

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

[0021] This embodiment includes a first A <br/> drain scan to be updated for each cycle of the signal processing performed at every predetermined period to hold the start address of the data memory in the each cycle output A register 1 of the holding means, a register 2 of the second address holding means for holding and outputting addresses sequentially updated in each cycle, and a third register for holding and outputting a specific address updated at a specific timing The register 3 of the address holding means, the selection circuit 4 for selecting one of the output addresses of the registers 1, 2, and 3 of the first, second, and third address holding means, and selection by the selection circuit 4 address in adding a predetermined value to the output register 1, 2, an adder 5, 3 updates the address, the fourth a to output as the address AD of the held data memory output address of the adder 5 It is configured to have a register 6 in less holding means.

Next, the operation of this embodiment will be described.

Normally, in digital audio signal processing, time-series data is provided as an input, and a series of processing is periodically repeated on the time-series data. The register 1 is a register whose value is updated for each processing unit (per cycle) in this column, and holds a start address when a series of processing is started. Register 2 is updated each time the data memory is accessed. That is, the address is updated when the address held in the register 2 is read.

Next, the operation of the address generation circuit when performing the operation of the second-order IIR filter shown in FIG. 4 will be described. FIG. 5 is used for the data in the data memory 20.

It is assumed that an address "m" is held in the register at time n. First, data A1 (n
To read -2), the address "m" is read from the register 1 and transferred to the register 6 to be the address AD of the data memory 20. At the same time, this data is also taken into the register 2. Next, in order to read data A1 (n-1), the address "m" is read from the register 2, "+1" is added by the adder 5, and "m + 1" is transferred to the register 6 to be the address AD of the data memory 20. At the same time, "m + 1" is also taken in the register 2. Similarly, an address “m + 2” is generated, A1n is written to the data memory 20, access to the data memory 20 is continued, and data B3n is written to the address “m + 17”. Next, data “m” is read from the register 1 again,
To “+1”, and the address “m +
A series of processing at the writing time n is ended.

At time (n + 1), the same operation as at time n is performed, so that data A1
Starting from reading (n-1), a series of filter operation processes can be executed.

In this embodiment, apart from the registers 1, 2, and 3 for holding the address value at each timing, the adder 5 for holding the address AD for actually instructing the data memory 20 is provided. When the fixed data (ND) written in the instruction code or the like is loaded, the result of addition of this data is written to the register 6, so that the values of the registers 1, 2, and 3 are not destroyed.

Next, when performing a double precision operation, efficient data memory can be used by storing data as in the memory map shown in FIG. The operation of the address generation circuit at this time will be described below. The double precision data is B1 (n
Only data corresponding to -1) is used.

It is assumed that at time n, register 1 holds address "m". First, address “m”
From the register 1 and transferred to the register 6 and the register 2.

Thus, the data A1 (n-2) is read from the data memory 20. Next, the address “m” is read from the register 2, “+1” is added by the adder 5, transferred to the registers 2 and 6, and the data A 1 is read from the data memory 20.
Read (n-1). Reading and writing of the data memory 20 are sequentially performed in the same procedure. When the value of the register 2 is “m + 3”, “+1” is added by the adder 5 and “m + 3”
+4 "is transferred to the registers 2 and 6, and the data of B1 (n-1) H is read out. Next," m "is read out again from the register 1 and added by the adder 5 to the fixed data ND" 18 ". The data B1 (n-1) L is read from the address "m + 18".

In the next step, the register 2 is read,
The address data "m + 1 + 1 = m + 5" is transferred to the registers 2 and 6, and B1nH is written to the address "m + 5".

In the next step, the register 3 is read, the address data "m + 18 + 1 = m + 19" is transferred to the registers 3 and 6, and B1nL is written at the address "m + 19". Thereafter, the same operation is performed, and finally, the read value of the register 1 is updated again to “m + 1”, and the processing at the time n is completed.

At time (n + 1), a series of filtering processes can be performed by performing exactly the same operation.

Further, when a subroutine call is performed in a method of sequentially inputting the offset amount from the basic address by the fixed data ND and specifying the address, first, the data of the register 1 is transferred to the registers 2 and 6 and the value of the register 2 is fixed. By transferring the data (ND) and the operation result only to the register 6, the basic addresses registers 1, 2
Is retained. Only at the time of a subroutine call, the offset value in the subroutine can be specified by transferring the operation result of the register 2 and the fixed data ND to both the registers 2 and 6.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

This embodiment has a configuration in which a register 7 is provided for inputting data ND of the first embodiment.

In the first embodiment, when double precision arithmetic is performed, it is necessary to load fixed data "18" in order to specify an area for storing lower-order data. In the second embodiment, by setting this "18" in the register 7 at the time of initial setting, double precision operation can be performed in a closed type inside the address generation circuit.

The other operations are the same as those of the first embodiment, and the detailed description is omitted.

[0039]

As described above, the present invention is provided with a register for holding an address corresponding to a use, all of which are connected in parallel to select an output thereof, and for holding an output address to a data memory. A separate register is provided, so even if a fixed address is loaded and an address is specified, the address data to be retained is not destroyed, so that the operation of saving the address data becomes unnecessary, and the data memory is not used when performing double precision arithmetic. The use efficiency is improved, and there is no need to perform a data saving operation at the time of a subroutine call when the offset amount from the basic address is specified by fixed data, so that the number of program steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a memory map of the data memory for explaining an addressing operation of the data memory according to the embodiment shown in FIG. 1 when double precision operations are mixed.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a signal flowchart of a host system to which a conventional address generation circuit is applied.

FIG. 5 is a memory map of a data memory for explaining an address designation operation by a conventional address generation circuit.

FIG. 6 is a memory map of a data memory for explaining an address designation operation by a conventional address generation circuit when double precision operations are mixed.

[Explanation of symbols]

 1-3 registers 4 selection circuit 5 adder 6,7 registers 10a-10c secondary IIR filter 20 data memory

Claims (2)

(57) [Claims] 1. A first address holding means which is updated in each cycle of signal processing executed in a predetermined cycle and holds and outputs a start address of a data memory in each cycle, and data in each cycle. a second address holding means for holding an address which is sequentially updated for each access output, a third address holding means for holding the particular address to be updated at the timing when the double precision operation is specified output, the Before the start of calculation within a predetermined period and at the start of double-precision calculation
Selecting the output address of the first address holding means,
The second address is held during the operation except when the operation is started.
Select the output address of the means, and
During the double precision operation, the output of the third address holding means is excluded.
A selection circuit for selecting an input address and outputting the selected address as a selected address;
Address generation, comprising: an adder for outputting as an update address of a third address holding unit; and a fourth address holding unit for holding an output address of the adder and outputting the output address of the data memory. circuit. 2. A data holding means for holding a value to be added to the selected address and supplying the value to the adder.
Address generation circuit as described.