JP3232717B2 - Circuit description synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit description synthesizing apparatus suitable for synthesizing a desired circuit by registering basic circuits in advance and combining these basic circuits.

[0002]

2. Description of the Related Art A complicated circuit can usually be expressed as a combination of basic circuits. Basic circuits, for example, flip-flops, addition circuits, subtraction circuits, A / D converters, etc., are registered in advance in a circuit description language such as circuit description A, circuit description B, circuit description C, and circuit description D, respectively. Keep it. The required basic circuits are expressed using the above-described circuit description language, and information specifying the connection relation and arrangement of those circuits is defined as a synthesis control instruction, and the circuit description language and the synthesis control instruction are defined as a program. A circuit description synthesizing method for automatically designing a desired circuit by inputting has been attempted.

[0003]

In the conventional circuit description synthesizing apparatus, since modules of all sizes are stored, for example, different word lengths and different word lengths are used for circuit description modules of arithmetic circuits such as multipliers. There is a problem in that separate modules must be facilitated and managed in accordance with different circuit schemes, and the number of modules becomes enormous. As the number of modules increases, the management thereof becomes complicated, and the problem of increasing the storage capacity is encountered.

In order to solve the above-mentioned problem, the present applicant has proposed a circuit description synthesizing apparatus capable of synthesizing a circuit description of an arbitrary size with a smaller data amount (for example, an application filed on July 10, 1991, In "Circuit Description Synthesizer". FIG. 8 is a configuration diagram of a circuit description synthesizing apparatus as such prior art. This circuit description synthesizing apparatus includes an input file 1, a decoder 2, a buffer memory 11, a duplicator 12, a selector 13, a main file 3, a module file 5, a size conversion block 14, a case processing block 15, a module management file 16, a circuit description It has an automatic synthesizing unit 6 and a data bus 200. To the input file 1, an input program including a circuit description language and a synthesis control instruction indicating a dimension parameter is input.
The circuit description language is a circuit program language (circuit description language) that parametrically describes a noise filter, an A / D converter, and the like, which are basic components necessary for a circuit to be synthesized. The synthesis control instruction is an instruction specified by a circuit description language and used for synthesizing a basic circuit with another basic circuit. The synthesis control command includes a repetition command, a dimension parameter, a case selection command, a module name selection command, and the like.

[0005] The decoder 2 decodes the circuit description language and the synthesis control instruction input to the input file 1. Decoder 2
, Decodes the circuit description language, outputs it to the buffer memory 11, repeatedly uses the duplicator 12 a specified number of times, and stores it in the main file 3 via the selector 13. When the decoder 2 decodes the dimension parameter in the synthesis control instruction, the size conversion block 14 performs a conversion process of the size of the circuit description. Decoder 2
Decodes the case classification selection command, the case classification processing block 15 selects the case classification of the circuit description. When the decoder 2 decodes the module name selection, the module management file 16 performs module management. These processing results are stored in the module file 5 via the data bus 200. The circuit description automatic synthesis unit 6 edits data stored in the main file 3 and the module file 5 to synthesize a circuit.

The operation of the circuit description synthesizing apparatus when the following input program 1 is input to the input file 1 will be described. Input program 1 1 #Repeat 3 times Circuit description A 2 Circuit description B 3 #Filter [size (2) FIR] 4 Circuit description C The first and third lines starting with the # mark indicate synthesis control instructions and have no # mark. The second and fourth lines indicate the circuit description language. In this example, the circuit description A shows a noise filter, the circuit description B shows an A / D converter, and the circuit description C
1 shows an / A converter.

The first line means that the circuit description A is repeated three times. This instruction is decoded by the decoder 2 and the circuit description A is stored in the buffer memory 11.
Is input to the duplicator 12 and 3
Times, the circuit description A is repeated. After that, the contents of the circuit description A repeated three times by the duplicator 12 are written into the main file 3 via the selector 13. The decoder 2 decodes “circuit description B” in the second row. Since “Circuit Description B” is a circuit description language, it is directly output to the selector 13 without passing through the buffer memory 11 and the duplicator 12, and the selector 13 is controlled by the selector selection signal S 2 L output via the terminal L of the decoder 2. Then, the contents of the circuit description B are written to the main file 3. The third line indicates a macro instruction. When the decoder 2 decodes that the circuit module is a filter and inputs it to the size conversion block 16, the circuit description data of the module name [Filter] is obtained from the module management file 16. Is read out, the size is taken out from the size conversion block 14, and this size and the module name are stored in the module file 5 via the data bus 200. The size conversion block 14 uses the signal from the module management file 16 to execute the statement on the third line: # Filter [size (2) FIR]
Is read, the circuit description size is converted, and the circuit description information obtained by connecting two filters in series is stored in the module file 5.
Write to. When [description of circuit C] on the fourth line is decoded by the decoder 2, the selector 13 is operated to record data indicating the D / A converter which is the content of the circuit description C in the main file 3. By the above processing, module file 5
In accordance with the circuit description information written in the main file 3, the circuit description automatic synthesizing unit 6 performs a circuit editing operation.

In the above-described prior art circuit description synthesizing apparatus, a basic circuit described parametrically and having regularity includes:
In a circuit configuration such as a filter or a D / A converter, description or management can be performed by a unified module. However, a circuit that is not described parametrically and has no regularity, such as a fixed coefficient multiplier, etc. When using the arithmetic circuit described above as a circuit description module, it has been found that the circuit description cannot be validated because the circuit forms to be configured differ depending on the coefficient values. Further, in the circuit description synthesizing apparatus according to the prior art, it has been found that it is difficult to manage a circuit configuration having regularity and a circuit configuration having no regularity with a single module. .

Accordingly, it is an object of the present invention to provide a circuit description synthesizing apparatus which solves the above-mentioned problems in the prior art and further provides an improved circuit description synthesizing apparatus.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention describes a repetitive context or a case-by-case context of a circuit description in a circuit description language while maintaining a good state of documentability. In addition to describing the above-mentioned basic circuit described in a parametric manner and having regularity as an internal module, a circuit described in a parametric manner and having no regularity is described as an external module and coexist to enable processing.

According to the present invention, there is provided a circuit description synthesizing apparatus for implementing the method for editing the synthesizing circuit. The circuit description synthesizing apparatus includes a circuit description parametrically described and having a regularity, a circuit description parametrically described and having no regularity, and a circuit design program defined by a circuit description language and a synthesis control instruction. Means for decoding the decoded circuit description language, a first storage means for storing the decoded circuit description language, and a first storage means for generating data corresponding to the decoded circuit description described in the parametric and having regularity.
Data generating means, second data generating means for generating data corresponding to the decoded circuit description having no regularity not described in the parametric, and data generated by the first and second data generating means. And a means for editing the data stored in the first and second storage means to synthesize a circuit.

[0012]

The composition circuit is described based on a circuit description language described by a circuit description language and a composition control instruction, and this language is edited to generate a desired composition circuit. As this language, a circuit description which is described parametrically and has regularity and a circuit description which is described parametrically and have no regularity are defined in advance. Circuit descriptions with regularity are edited in the same way as proposed in the prior art,
For a circuit description having no regularity, a partially synthesized circuit as a combination of the circuit modules having the regularity is described according to a predetermined procedure according to the specified circuit description having no regularity. Generate new data. The new data is a set of data based on a circuit description having regularity, and can be edited consistently with data based on a circuit description having regularity.

Preferably, a circuit description which does not have regularity is defined in advance by using a predetermined factor, and a circuit having regularity is synthesized with a partial synthesis circuit according to the factor. As a result, 1
With one instruction and one processing method, it is possible to edit various aspects of the partial synthesis circuit based on the same circuit idea specified by the factor.

[0014]

FIG. 1 is a block diagram showing a first embodiment of a circuit description synthesizing apparatus according to the present invention. This circuit description synthesizing apparatus includes an input file 1, a decoder 2, a buffer memory 1 shown in FIG.
1, duplicator 12, selector 13, main file 3, module file 5, size conversion block 1
4. In addition to a case processing block 15, a module management file 16, and a circuit description automatic synthesis unit 6, a data storage block 17 and an external module call block 18 are added. Module management file 1
6, a data storage block 17, an external module call block 18, a case processing block 15, and a size conversion block 14 are mutually connected via a data bus 100, and are connected to the module file 5.

The input file 1 receives an input program consisting of a circuit description language and a synthesis control instruction. In this embodiment, a circuit having a regularity described parametrically is described as an internal module, and a circuit which is described parametrically and having no regularity is described as an external module. FIG. 2 shows an example of an internal module that is described parametrically and has regularity, together with a circuit description language.
(A) to (D) and Table 1 show.

Table 1 Circuit No. Circuit Name Circuit Description Language FIG. 2 (A) Noise Filter Circuit Description A FIG. 2 (B) A / D Converter Circuit Description B FIG. 2 (C) D / A Converter Circuit Description B ′ Fig. 2 (D) Buffer circuit Circuit description C

The external module is generally shown in FIG.
This is represented by the expression illustrated in FIG. FIG. 3 shows an example of an adder circuit as a detailed circuit example. Although the details will be described later, the following circuit description (statement): Ext When add (α) exists, the following adder circuit α = 3, the adder circuit α = 4 in FIG. 3A, the adder circuit α = 5 in FIG. Describe the addition circuit of C). In other words, the external modules shown in FIGS. 5A to 5C each represent a moving average processing circuit. However, since the addition is performed in a tree structure, the configuration changes irregularly with respect to the parameter α, and is not described parametrically. An irregular circuit description.

When a program consisting of the above-described circuit description language and synthesis control command is input to the input file 1, the program is output to the decoder 2, and the decoder 2 decodes the input program, and the terminals L, M, N, C , P, respectively, output a selector selection signal S2L, a circuit description language signal S2M, a repetition instruction signal S2K, a module name signal S2N, a case selection signal S2C, and a dimension parameter signal S2P. The decoding operation of the decoder 2 and the operation of each unit of the circuit description synthesizing device will be described. When the decoder 2 decodes the input program into a circuit description language, the decoder 2
3 outputs a circuit description language signal S2M. Also, the selector 13 outputs the selector selection signal S2L to the selector 13 so that the selector 1
3 is stored in the main file 3 as it is. When the decoder 2 decodes the input program as a repetition sentence, it outputs a repetition instruction signal S2K to the buffer memory 11 and causes the circuit description language to be repeated the number of times specified via the duplicator 12. Repeated circuit description language is selector 1
3 and stored in the main file 3.

When the decoder 2 decodes the circuit description language in the input program and specifies that the internal module name is specified, it outputs a module name signal S2N to extract the corresponding internal module data from the module management file 16,
It is stored in the module file 5 via the data bus 100. When the decoder 2 decodes the circuit description language in the input program and specifies that the external module name is specified, the decoder 2 outputs a module name signal S2N and outputs the module management file 1
6, the corresponding external module data is extracted as the data storage instruction signal S16b, and the parameter for calling the external module is written in the data storage block 17. Next, the data storage instruction signal S16b is output to the external module calling block 18 via the module management file 16, and the specified external module is selected from the external module calling block 18, and the selected external module is stored in the data storage block 17. The data is converted into a module having a size specified by a parameter, and written into the module file 5 via the data bus 100. When the decoder 2 decodes the input program as a case-based selection designation, the decoder 2 outputs a case-based selection signal S2C to the case-based processing block 15 to select a required circuit configuration and to transmit the data bus 100.
To the module file 5 via Decoder 2
Decodes the input program and determines that it is a dimensional parameter, outputs a dimensional parameter signal S2P to the size conversion block 14, and converts the circuit description language described parametrically into a module of the specified size using a normal description language. , To the module file 5 via the data bus 100.

As described above, the circuit description language is stored in the main file 3, and the module file 5 includes the module management file 16, the data storage block 17, the external module call block 18, and the case processing block 1.
5, and the data processed by the size conversion block 14 are stored. The circuit description automatic synthesizing section 6 edits the data generated in this way to create, for example, a synthetic circuit shown in FIG. The filter circuit 22 in FIG. 4 is based on an external module, and a detailed circuit example thereof is shown in FIG.

An example of combining the circuits shown in FIGS. 4 and 5 will be described. An input program 2 shown below is input to the input file 1. Input program 2 1 # Repeat 2 times Circuit description A 2 Circuit description B 3 # Filter [size = 2, Add] Circuit description C 4 Circuit description B In ^the program 2, the first and third lines starting with the # mark are synthesis control. Instructions are shown, and the second and fourth lines without the # mark indicate a circuit description language. Table 1 and FIG. 2 (A)
As shown in ~ (D), the circuit description A noise filter, the circuit description B are A / D converter, circuit description ^B, the D / A
3 shows a converter. The program on the first line is a circuit description A
(Noise filter) is specified to be repeated twice. Program on the third line: Circuit description C is a macro instruction, and specifies a filter as an external module.

The processing decoder 2 in the first line decodes the instructions in the first line, repeats the circuit description language of the noise filter twice through the buffer memory 11 and the duplicator 12, and stores the data in the main file 3. To memorize. The processing decoder 2 on the second line decodes the command statement on the second line, and stores the circuit description language of the A / D converter: “circuit description B” directly in the main file 3 via the selector 13. Write the contents of the circuit description B to the main file 3. The processing decoder 2 on the third line decodes the program: macro instruction on the third line and operates the above-described processing for the external module, that is, the module management file 16, the data storage block 17, and the external module call block 18. A series of processing is performed, and the circuit description data of the external module name [Filter] is stored in the circuit description automatic synthesis unit 6 via the data bus 100. The details will be described later. The processing decoder 2 in the fourth row is a circuit description language for the D / A converter:
“Circuit description B ′” is directly stored in the main file 3 via the selector 13.

The details of the processing for the external module on the third line will be described. The decoder 2 decodes the program on the third line: #Filter [size = 2, Add] Decodes [Filter] of the circuit description C, outputs the module name signal S2N to the module management file 16, and outputs the module name signal S2N from the module management file 16 to the external module. Name: Extract the circuit description of [Filter]. Table 2 shows the processing results in the module management file 16.

[Table 1]

Statement: "size = 2 circuit description C"
Is a size conversion instruction. The size conversion block 14 converts the circuit description C into two circuit descriptions connected in series, and the result shown in Table 3 is sent to the data storage block 17.

[Table 2]

In the data storage block 17, Table 3
The data storage statement on the third line shown in #: #Data α = 3 Processes. That is, the input parameter of the external module is set to 3 and written in the data storage block 17. Table 4 shows the results.

[Table 3]

Next, the decoder 2 selects the case-based processing statement: if [Type = Add] shown in Table 4, and operates the case-based processing block 15 to execute the processing in Table 4.
The statement that is the description part of the Add (addition circuit) method is: #Call _- Ext add [α]). The case processing block 15 processes this as an external module read command. Here, data on the external module stored in the data storage block 17 is read in advance, and an adder (Add) is generated as the external module as a dimension parameter. Then
The output data of the data storage block 17 is stored in the module file 5. Table 5 shows the case processing block 15
Table 6 shows the external module call block 1
8 shows the processing result.

[Table 4]

[Table 5] When the decoder 2 terminates the processing on the third row, the decoder 2 shifts to the processing on the fourth row.

In this example, the statement in the second row of Table 5 is Ext _- add [3]. That is, since the factor α indicating the number of input data to the basic adder is 3, the data indicating the partial combining adder shown in FIG. 3A is internally edited according to a procedure registered in advance. That is, FIG. 3A shows that the data input to the two basic adders add1 and add2
This indicates that three lines are input from 1, 102, and 103. The registers R1 and R2 are automatically determined according to the basic circuit description. If it is specified that α = 4, the data indicating the partial combining and adding circuit shown in FIG. 3B is edited. In other words, this example uses three basic adders
The data sequentially input to add1, add2 and add3 is line 10
It indicates that there are four lines input from 1, 102, 103 and 104. The registers R1, R2, R3 are automatically determined according to the basic circuit description. The partial combining and adding circuit shown in FIG. 3C is based on the same idea.

As is clear from the circuit configuration illustrated in FIG. 3, it is not handled as the basic circuit illustrated as the internal module illustrated in FIGS. 2A to 2C.
It can be expressed as a combination of basic circuits such as an adder circuit and a register. Therefore, when a circuit that is originally represented as an external module having no regularity is analyzed, it can be represented as a partial synthesis circuit obtained by combining basic circuits. There is no difference between the internal module and the external module in the editing work in the circuit description automatic synthesis section 6. therefore,
The circuit description automatic synthesizing unit 6 can process the internal module and the external module in the same manner. Such external modules can be individually specified as a combination of ordinary internal modules, but the circuit description becomes complicated. Also,
If the details of the circuit in FIG. 3A are illustrated as a circuit to be treated as one circuit having a certain function as the filter circuit 22 in FIG. 4, the entire synthesis circuit becomes very complicated. That is, it is very convenient that the partial synthesis circuit illustrated in FIGS. 3A to 3C can be generated only by specifying the factor α as the external module. The circuit illustrated in FIG. 3 has a philosophy unified into a basic circuit configuration. By registering a processing procedure based on this philosophy, the desired partial synthesis circuit can be internally designated only by specifying the factor α. Can be generated.

Table 6 shows the data stored in the main file 3 based on the above-described processing, and Table 7 shows the data stored in the module file 5. Table 8 shows the data edited by the circuit description automatic synthesis unit 6. Table 6 1 Circuit description A 2 Circuit description A 3 Circuit description B 4 Circuit description B 'Table 7 1 Filter [size, Add] 2 Circuit description C 3 Ext add [3] Table 8 1 Circuit description A 2 Circuit description A 3 Circuit description B 4 Filter [size, Add] 5 Circuit description B '

When the result is edited in the circuit description automatic synthesizing unit 6 and illustrated in Table 8, the synthesized circuit illustrated in FIG. 4 is obtained. That is, the synthesis circuit includes two noise filters 19 and 20, an A / D converter 21, an external filter circuit 22, and a D / A converter 23 connected in series. The detailed circuit configuration of the external filter circuit 22 is shown in FIG.
Shown in This filter circuit 22 includes a buffer circuit 22
a, Statement: Ext This is a circuit configuration illustrated in FIG. 5A specified by add (α = 3).

As described above, a circuit that is described parametrically and has no regularity is defined as an external module, and by performing the above-described processing, a composite circuit that matches the internal module can be edited. In particular,
Even when the value of the factor α changes as illustrated in FIG. 3 without parametric description and regularity, processing can be performed with regularity. Such an external module is not limited to the addition circuit illustrated in FIG. 3, but may be applied to other circuits, for example, an arithmetic circuit such as a fixed coefficient multiplier. Therefore, according to the circuit description synthesizing device of the present invention, it is possible to edit a desired synthesizing circuit without restriction of application of an external module. Further, in this circuit description synthesizing apparatus, it is easy to manage as a unified module.

The configuration of the circuit description synthesizing apparatus illustrated in FIG. 1 does not require all the illustrated components. For example, the external module call block 18 and the data storage block 17 need to be provided together, but the size conversion block 14, the case processing block 15, and the external module call block 18 need not always be provided at the same time. These blocks 14, 15, 18 can be arbitrarily selected and provided according to the contents.

Further, the circuit description synthesizing device does not need to have the configuration illustrated in FIG. FIG. 6 shows the configuration of a second embodiment of the circuit description synthesizing apparatus according to the present invention. This circuit description synthesizing apparatus includes a module management file 16, a data storage block 17, an external module calling block 1 shown in FIG.
8, case processing block 15, size conversion block 1
4 shows a configuration in which blocks related to data flow and control are connected to each other, instead of the data bus 100 that allows the module 4 and the module file 5 to communicate with each other. In this circuit description synthesizing apparatus, the module name signal S2N is output from the decoder 2 to the module management file 16, the case selection signal S2C is output to the case processing block 15, and the dimension parameter signal S2P is output to the size conversion block 14. Have been. Further, the external module call instruction signal S16a is output from the module management file 16 to the external module call block 18, and the data storage instruction signal S16b is output to the data storage block 17. Further, the data of the module management file 16 is applied to the data storage block 17, the data of the data storage block 17 is applied to the external module calling block 18, and the data of the external module calling block 18 is applied to the case processing block 15,
The data of the case processing block 15 is applied to the size conversion block 14 and stored in the circuit description automatic synthesis unit 6. The processing contents of each of the illustrated components are substantially the same as those in the circuit description synthesizing apparatus illustrated in FIG.

FIG. 7 shows a circuit description synthesizing apparatus according to a third embodiment. In this circuit description synthesizing apparatus, the connection from the decoder 2 to the module management file 16, the size conversion block 14, the case processing block 15, and the connection from the module management file 16 to the data storage block 17 and the external module call block 18 6 is the same as that illustrated in FIG. 6, but the order of the data path from the module management file 16 to the module file 5 is
Module management file 16, size conversion block 1
4, data storage block 17, case processing block 1
5. Replaced with the external module call block 18.

The circuit description synthesizing apparatus illustrated in FIGS. 1, 6 and 7 includes, for example, an input file 1, a decoder 2,
Although the apparatus configuration in which the size conversion block 14 and the like perform processing by combining modules each having an independent processing function such as a microcomputer has been exemplified, the processing of the above-described circuit description synthesizing apparatus is processed by software using a general-purpose computer. You can also.

[0036]

According to the present invention, since the repetitive context and the case-specific context of the circuit description are described in the circuit description language, not only the basic circuit which can be described parametrically but also has no regularity. The basic circuit can also be edited at the same time, and a desired circuit can be synthesized. In the present invention, furthermore, a basic circuit which can be described parametrically and which originally has no regularity is processed so as to have regularity.
Various complicated circuits can be internally synthesized with a small amount of data, and the synthesized circuit as a whole can be edited by combining the synthesized circuit with a circuit having regularity. In the present invention, a circuit having regularity and a circuit having no regularity can be processed homogeneously, so that processing with consistency can be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a circuit description synthesis device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a basic circuit as an internal module used for the circuit description of the present invention.

FIG. 3 is a circuit diagram showing an example of a partial synthesis circuit as an external module used for the circuit description of the present invention.

FIG. 4 is a circuit diagram showing a synthesis circuit edited by the circuit description automatic synthesis device of FIG. 1;

FIG. 5 is a detailed partial synthesis circuit diagram of the filter circuit illustrated in FIG. 4;

FIG. 6 is a configuration diagram of a second embodiment of the circuit description synthesizing apparatus according to the present invention.

FIG. 7 is a configuration diagram of a third embodiment of the circuit description synthesizing apparatus according to the present invention.

FIG. 8 is a configuration diagram showing an example of a circuit description synthesis device as a prior art.

[Description of Signs] 1 ・ ・ ・ Input File 2 ・ ・ ・ Decoder 3 ・ ・ ・ Main File 5 ・ ・ ・ Module File 6 ・ ・ ・ Circuit Description Automatic Synthesis Unit 11 ・ ・ ・ Buffer Memory 12 ・ ・ ・ Duplicator 13 ・··· Selector 14 ··· Size conversion block 15 ··· Case processing block 16 ··· Module management file 17 ··· Data storage block 18 ··· External module call block 19 and 20 ··· Noise filter 21 ···・ A / D
Converter 22 ... External filter circuit 22b Adder circuit 22b-1 Adder 23 ... D / A
Converter 100, 200 ... data bus

[Table 6]

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (6)

(57) [Claims] A circuit design program including a circuit description parametrically described and having a regularity, and a circuit description parametrically described and having no regularity, which is defined by a circuit description language and a synthesis control instruction. Means for storing the decoded circuit description language; first data generating means for generating data corresponding to the decoded circuit description described in the parametric and having regularity; A second data generating means for generating data corresponding to the decoded circuit description having no regularity not described in the parametric; and storing the data generated by the first and second data generating means. A circuit comprising: a second storage unit; and a unit that edits data stored in the first and second storage units and synthesizes a circuit. Predicates synthesis device. 2. The method according to claim 1, wherein the second data generation means describes a partial synthesis circuit as a combination of the circuits having the regularity in accordance with a predetermined procedure in accordance with the circuit description having no regularity. claim 1 to generate new data
Described circuit description synthesis device. 3. A was defined using previously predetermined factor circuit description without the inherent regularity, the second data generating means, according to claim 2, wherein the synthesizing circuit in regularity depending on the factors Circuit description synthesizer. 4. The module according to claim 1, wherein the second data generating means stores a module management file for managing the circuit modules having regularity and the circuit modules having no regularity, and data of the circuit module having no regularity. 4. The circuit description synthesizing apparatus according to claim 3 , comprising: a data storage block; and an external module call block for calling a circuit module having no regularity. Wherein said second data generating means further claim 4 having a size conversion block for converting the size of the circuit module, and a case divided processing block for processing a case divided instructions decoded by said decoding means Described circuit description synthesis device. 6. The circuit description language allows a description indicating that the same circuit description repeats continuously, and wherein the first data generating means generates the same circuit description by the number of repetitions in response to the repeated description. 5. The circuit description synthesizing apparatus according to claim 1, wherein said circuit description synthesizing unit stores the information in said first storage unit.