JPS59178544A - Memory access circuit - Google Patents

Abstract

PURPOSE:To realize a circuit that does not require complicated arithmetic circuit and does not lower access speed to a data memory by providing an address memory that stores address information for a data memory. CONSTITUTION:Data output of an address memory 22 is given to a data memory RAM 12 and the data memory 12 outputs data accumulated corresponding to the address. An arithmetic unit 14 holds data from a bus 13 by registers 23, 24 and takes in an arithmetic element 25, and the result of operation and data from the bus 13 are added up by an accumulator 26 and fed back to the arithmetic element 25. Address operation necessary for execution of DSP (digital signal processing device) 10 is made at the time of system set up or in waiting time of execution of DSP and accumulated in the address memory 22. A counter 21 advances the counted value one by one at each data storing, and the results of operation are accumulated in the address memory 22 corresponding to respective address.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a memory access circuit for generating addresses of data memory in a processor system that operates according to microinstructions.

Conventional Technology and Problems An example of a processor system that operates according to microinstructions is a digital decoding processor (DSP). In a DSP, for example, a digital filter is realized by digitally processing an audio signal, and the process No. 46 of Article 46 is performed to perform voice synthesis. Generally, such processing is performed in various ways depending on the purpose. According to the function of
It is performed by calculating the desired transfer function in real time by relating the takes of the large violet, and the calculations in this case can usually be reduced to simple calculations such as four arithmetic operations. There are many cases. Generally, for such calculations, a data memory is prepared, in which the takes required for the calculation and the take of the 101 arithmetic results are stored, and addresses are specified as the calculation progresses, and the takes are taken from the memory. is read out and given to the arithmetic unit.

The simplest method for multiplying and reading takes in such a take mesori is to store the takes in order from the 0th area of the memory, read them sequentially from the 0th area, and use them for calculations. After outputting the take, the address can be advanced by one position and the take at the next address can be read. However, the arithmetic method in a DSP is not always just f+il as described above, and therefore a very specific method of accessing the data memory is required.

FIG. 1 shows an example of a conventional memory access method in a DSP. In the figure, 1 is a counter which can load one box from the outside and generates a count value by instructing an increment or a tick increment.

A data memory 2 receives the count value of the counter 1 as an address and outputs stored data corresponding to the address.

FIG. 2 shows another example of the conventional memory access method. In the figure, 6 is a microinstruction,
By writing a memory address directly in the operand 4 of the microinstruction 6 and giving this to the data memory 2 as an address, the required data is output.

FIG. 6 shows still another example of the conventional memory access method. In the figure, numeral 5 is an index register that can be loaded with a command. 6 is an adder which adds the value loaded into the index register 5 and the memory area described in the operand 4 of the microinstruction 6 and gives it to the data memory 2 as an address, thereby adding the value loaded into the index register 5 and the memory area described in the operand 4 of the microinstruction 6; data is output.

Complex addressing can be achieved using these various methods, but if even more complex addressing is required, the methods explained in Figures 1 to 6 may be combined or used. Methods are being used to increase the number of available counters, or (1) to perform address calculations using an arithmetic unit normally included in the SP, and to access memory based on the results.

However, as complex address calculations are required, complex address calculation circuits are required.
Along with this, the circuit scale becomes larger. In addition, when address calculation is performed by a DSP arithmetic unit, the address M
Since the cycle is divided into a cycle for performing % and a cycle for actually accessing the memory depending on the result, the speed of accessing the memory decreases.

OBJECTS OF THE INVENTION The present invention attempts to solve the problems encountered in the prior art, and its purpose is to eliminate the need to perform complex address operations when accessing data memory in a processor system that operates according to microinstructions. The purpose of the present invention is to provide a circuit formation that does not require a complicated arithmetic circuit and does not reduce the access speed to a data memory even when there is a casing.

Structure of the Invention The memory access circuit of the present invention does not perform address calculation for each instruction to access the memory, but reduces the time required for system set-up, DsF wait time, etc.
During the time when p is not accessing the memory, the address information obtained by performing calculations in advance is stored in the address memory in order, and when the data memory is accessed, the address of the address memory is accessed by the counter and the read data is stored as data. It is designed to be used as a memory address.

Embodiment of the Invention FIG. 4 shows the configuration of an embodiment of the memory access circuit of the invention. In the figure, 10 beams indicate SP. In DSPLo, 11 is an address circuit, 12 is a data memory, 16 is a data bus, and 14 is a processor.

In the short address circuit 11, 21 is a counter, 22
is an address memory, and in the arithmetic unit 14, 23.2
4 is an input register, 25 is an arithmetic operation element (ILU)
, 26 are accumulators.

In the address circuit 11, the counter 21 outputs a count value by loading a value or performing a counting operation according to a command. Address memory 22 is &
By being given the count value of the counter 21 as an address from the storage memory (RAM),
Data that has been read in advance in correspondence with an address is read out and output.

Data memory 12 is given the data output of address memory 22 as an address, and outputs stored data corresponding to the address to data bus 16.

On the other hand, the arithmetic unit 14 has input registers 25 and 24 that hold data input from the data bus 13, and takes the data into the arithmetic register 25 and accumulates the arithmetic results and data from the data bus 16 in an accumulator 26. It performs calculations that are calculated and returned to the arithmetic element 25. During system setup or during DSP execution waiting time, address calculations necessary for DSP processing and execution are performed, and the results are sent to the address. Store it in memory 22. At this time, the counter 21 increments its count value by one each time data is stored, thereby accumulating the calculation results in the address memory 22 in correspondence with each address.

When DSPLo performs processing using data stored in the data memory 12, it sequentially reads out the contents of the address memory 22 by incrementing the counter 21 one by one, and accesses the data memory 12 using the output, that is, the execution address. do.

In the memory access circuit shown in FIG. 4, since the address calculation is performed in advance using the arithmetic unit inherent in the DSP, it is possible to handle complex address calculations, and the address calculation circuit does not become complicated due to this. Since the results of address calculations that have been performed in advance are stored and addressing is performed based on the stored results, there is no problem with slow speeds when accessing data memory even when complex address calculations are required. No weight is generated.

FIG. 5 shows the configuration of another embodiment of the memory access circuit of the present invention. In the same figure, 15 is an input/output ('/
Q) It shows the part.

In FIG. 5, a 110 unit 15 stores address data obtained in advance into the address memory 22 from outside the DSP. At this time, the counter 21 increments the count value one by one while specifying the data write address in the address memory 22, as in the case of FIG. 4.

In this way, in the embodiment shown in FIG. 5, the data memory can be addressed using the result of external address calculation, so compared to the embodiment shown in FIG. This has the advantage that it is not necessary to add a function for address calculation to the .

FIG. 6 shows the configuration of yet another embodiment of the memory access circuit of the present invention. In the same figure, unlike the embodiment shown in FIG. 4 or 5, the address circuit 11 includes an address memory 2 consisting of a read-only memory (ROM) instead of an address memory 22 consisting of a RAM.
It has 7.

In the embodiment shown in FIG. 6, the address memory 27 is given the count value of the counter 21 as an address, and reads and outputs the data stored in advance in correspondence with the address. The address memory 27 consists of a ROM, and is loaded with necessary address data in advance.

Therefore, the embodiment shown in FIG. 6 has the advantage that the address data can be easily changed by replacing or replacing the ROM constituting the address memory 27 depending on the purpose of use of the DSP.

According to the memory access circuit of the present invention, an address memory for storing address information for the data memory is provided, and the data memory is accessed using the output of the address memory as an address. A digital signal processing device that reads and processes data stored in a memory does not require a complex arithmetic circuit even when it is necessary to perform complex address arithmetic, and the access speed to data memory does not slow down. .

[Brief explanation of drawings]

1 to 6 are diagrams each showing a conventional memory access method, and FIGS. 4 to 6 are diagrams each showing a configuration of an embodiment of a memory access circuit according to the present invention. DESCRIPTION OF SYMBOLS 1... Counter, 2... Data memory, 6... Microphone instruction, 4... Operand, 5... Index register, 6... Adder, 10... Digital signal processing equipment 1 A (DSF), 11...address circuit, 12...take memory, 16...take bus, 1
4... Arithmetic unit, 15... Input/output ('10) section, 21
. . . Counter, 22 . . . Address memory, 26.
24...Input register, 25...Miscellaneous elements (ALU), 26...Accumulator, 27...Address memory patent author Fujitsu Limited Patent attorney Hisashi Tamamushi Department (6 people) Figure 1 Output Figure 2 236- Figure 3

Claims (1)

[Claims] In a data processing device that reads and processes takes stored in a data memory by specifying an address of the data memory, an address memory capable of storing address information for the data memory is provided, and the output of the address memory is provided. A memory access circuit characterized in that the data memory is accessed using the address as an address.